147 lines
3.5 KiB
C
147 lines
3.5 KiB
C
/** @defgroup ssp_file SSP
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@ingroup LPC43xx
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@brief <b>libopencm3 LPC43xx SSP</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2012/2014 Benjamin Vernoux <bvernoux@gmail.com>
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Benjamin Vernoux <bvernoux@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/lpc43xx/ssp.h>
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#include <libopencm3/lpc43xx/ccu.h>
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#include <libopencm3/lpc43xx/cgu.h>
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/* Disable SSP */
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void ssp_disable(ssp_num_t ssp_num)
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{
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uint32_t ssp_port;
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if (ssp_num == SSP0_NUM) {
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ssp_port = SSP0;
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} else {
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ssp_port = SSP1;
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}
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/* Disable SSP */
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SSP_CR1(ssp_port) = 0x0;
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}
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/*
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* SSP Init function
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*/
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void ssp_init(ssp_num_t ssp_num,
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ssp_datasize_t data_size,
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ssp_frame_format_t frame_format,
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ssp_cpol_cpha_t cpol_cpha_format,
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uint8_t serial_clock_rate,
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uint8_t clk_prescale,
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ssp_mode_t mode,
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ssp_master_slave_t master_slave,
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ssp_slave_option_t slave_option)
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{
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uint32_t ssp_port;
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uint32_t clock;
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if (ssp_num == SSP0_NUM)
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{
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ssp_port = SSP0;
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CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_CLK_SEL(CGU_SRC_PLL1)
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| CGU_BASE_SSP0_CLK_AUTOBLOCK(1);
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CCU1_CLK_M4_SSP0_CFG |= 1; /* Enable SSP0 Clock */
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/* use PLL1 as clock source for SSP0 */
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} else
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{
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ssp_port = SSP1;
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/* use PLL1 as clock source for SSP1 */
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CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1)
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| CGU_BASE_SSP1_CLK_AUTOBLOCK(1);
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CCU1_CLK_M4_SSP1_CFG |= 1; /* Enable SSP1 Clock */
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}
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/* Disable SSP before to configure it */
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SSP_CR1(ssp_port) = 0x0;
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/* Configure SSP */
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clock = serial_clock_rate;
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SSP_CPSR(ssp_port) = clk_prescale;
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SSP_CR0(ssp_port) =
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(data_size | frame_format | cpol_cpha_format | (clock<<8));
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/* Enable SSP */
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SSP_CR1(ssp_port) = (SSP_ENABLE | mode | master_slave | slave_option);
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}
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static void ssp_wait_until_not_busy(ssp_num_t ssp_num)
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{
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uint32_t ssp_port;
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if (ssp_num == SSP0_NUM) {
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ssp_port = SSP0;
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} else {
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ssp_port = SSP1;
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}
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while ((SSP_SR(ssp_port) & SSP_SR_BSY));
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}
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/* This Function Wait Data TX Ready, and Write Data to SSP */
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uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data)
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{
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uint32_t ssp_port;
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if (ssp_num == SSP0_NUM) {
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ssp_port = SSP0;
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} else {
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ssp_port = SSP1;
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}
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/* Wait Until FIFO not full */
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while ((SSP_SR(ssp_port) & SSP_SR_TNF) == 0);
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SSP_DR(ssp_port) = data;
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/* Wait for not busy, since we're controlling CS# of
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* devices manually and need to wait for the data to
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* be sent. It may also be important to wait here
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* in case we're configuring devices via SPI and also
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* with GPIO control -- we need to know when SPI
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* commands are effective before altering a device's
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* state with GPIO. I'm thinking the MAX2837, for
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* example...
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*/
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ssp_wait_until_not_busy(ssp_num);
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/* Wait Until Data Received (Rx FIFO not Empty) */
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while ((SSP_SR(ssp_port) & SSP_SR_RNE) == 0);
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return SSP_DR(ssp_port);
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}
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/**@}*/
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