699 lines
33 KiB
ArmAsm
699 lines
33 KiB
ArmAsm
/*
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* Copyright 2019-2022 Great Scott Gadgets
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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/*
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Introduction
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============
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This file contains the code that runs on the Cortex-M0 core of the LPC43xx.
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The M0 core is used to implement all the timing-critical usage of the SGPIO
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peripheral, which interfaces to the MAX5864 ADC/DAC via the CPLD.
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The M0 reads or writes 32 bytes at a time from the SGPIO registers,
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transferring these bytes to or from a shared USB bulk buffer. The M4 core
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handles transferring data between this buffer and the USB host.
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The SGPIO peripheral is set up and enabled by the M4 core. All the M0 needs to
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do is handle the SGPIO exchange interrupt, which indicates that new data can
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now be read from or written to the SGPIO shadow registers.
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To implement the different functions of HackRF, the M0 operates in one of
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five modes, configured by the M4:
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IDLE: Do nothing.
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WAIT: Do nothing, but increment byte counter for timing purposes.
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RX: Read data from SGPIO and write it to the buffer.
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TX_START: Write zeroes to SGPIO until there is data in the buffer.
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TX_RUN: Read data from the buffer and write it to SGPIO.
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In all modes except IDLE, the M0 advances a byte counter, which increases by
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32 each time that many bytes are exchanged with the buffer (or skipped over,
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in WAIT mode).
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As the M4 core produces or consumes these bytes, it advances its own counter.
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The difference between the two counter values therefore indicates the number
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of bytes available.
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If the M4 does not advance its count in time, a TX underrun or RX overrun
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occurs. Collectively, these events are referred to as shortfalls, and the
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handling is similar for both.
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In an RX shortfall, data is discarded. In TX mode, zeroes are written to
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SGPIO. When in a shortfall, the byte counter does not advance.
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The M0 maintains statistics on the the number of shortfalls, and the length of
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the longest shortfall.
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The M0 can be configured to abort TX or RX and return to IDLE mode, if the
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length of a shortfall exceeds a configured limit.
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The M0 can also be configured to switch modes automatically when its byte
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counter matches a threshold value. This feature can be used to implement
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timed operations.
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Timing
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======
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This code has tight timing constraints.
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We have to complete a read or write from SGPIO every 163 cycles.
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The CPU clock is 204MHz. We exchange 32 bytes at a time in the SGPIO
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registers, which is 16 samples worth of IQ data. At the maximum sample rate of
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20MHz, the SGPIO update rate is 20 / 16 = 1.25MHz. So we have 204 / 1.25 =
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163.2 cycles available.
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Access to the SGPIO peripheral is slow, due to the asynchronous bridge that
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connects it to the AHB bus matrix. Section 20.4.1 of the LPC43xx user manual
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(UM10503) specifies the access latencies as:
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Read: 4 x MCLK + 4 x CLK_PERIPH_SGPIO
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Write: 4 x MCLK + 2 x CLK_PERIPH_SGPIO
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In our case both these clocks are at 204MHz so reads add 8 cycles and writes
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add 6. These are latencies that add to the usual M0 instruction timings, so an
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ldr from SGPIO takes 10 cycles, and an str to SGPIO takes 8 cycles.
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These latencies are assumed to apply to all accesses to the SGPIO peripheral's
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address space, which includes its interrupt control registers as well as the
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shadow registers.
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There are four key code paths, with the following worst-case timings:
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RX, normal: 152 cycles
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RX, overrun: 76 cycles
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TX, normal: 140 cycles
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TX, underrun: 145 cycles
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Design
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======
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Due to the timing constraints, this code is highly optimised.
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This is the only code that runs on the M0, so it does not need to follow
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calling conventions, nor use features of the architecture in standard ways.
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The SGPIO handling does not run as an ISR. It polls the interrupt status.
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This saves the cycle costs of interrupt entry and exit, and allows all
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registers to be used freely.
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All possible registers, including the stack pointer and link register, can be
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used to store values needed in the code, to minimise memory loads and stores.
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There are no function calls. There is no stack usage. All values are in
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registers and fixed memory addresses.
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Structure
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=========
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Each mode has its own loop routine. TX_START and TX_RUN use a single TX loop.
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Code shared between different modes is implemented in macros and duplicated
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within each mode's own loop.
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At startup, the main routine sets up registers and memory, then falls through
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to the idle loop.
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The idle loop waits for a mode to be set, then jumps to that mode's start
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label.
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Code following the start label is executed only on a transition from IDLE. It
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is at this point that the buffer statistics are reset.
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Each mode's start code then falls through to its loop label.
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The first step in each loop is to wait for an SGPIO interrupt and clear it,
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which is implemented by the await_sgpio macro.
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Then, the mode setting is loaded from memory. If the M4 has reset the mode to
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idle, control jumps back to the idle loop after handling any cleanup needed.
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Next, any SGPIO operations are carried out. For RX and TX, this begins with
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calculating the buffer margin, and branching if there is a shortfall. Then
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the pointer within the buffer is updated.
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SGPIO reads and writes are implemented in 16-byte chunks. The four lowest
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registers, r0-r3, are used to temporarily hold the data for each chunk. Data
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is stored in-order in the buffer, but out-of-order in the SGPIO shadow
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registers, due to the SGPIO architecture. A combination of single and
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multiple load/stores is used to reorder the data in each chunk.
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After completing SGPIO operations, counters are updated and the threshold
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setting is checked. If the byte count has reached the threshold, the next
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mode is set and a jump is made directly to the corresponding loop label.
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Code at the start label of the new mode is not executed, so stats and
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counters are maintained across a sequence of TX/RX/WAIT operations.
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When a shortfall occurs, a branch is taken to a separate handler routine,
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which branches back to the mode's normal loop when complete.
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Most of the code for shortfall handling is common to RX and TX, and is
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implemented in the handle_shortfall macro. This is primarily concerned with
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updating statistics, but also handles switching back to IDLE mode if a
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shortfall exceeds the configured limit.
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There is a rollback mechanism implemented in the shortfall handling. This is
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necessary because it is common for a harmless shortfall to occur during
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shutdown, which produces misleading statistics. The code detects this case
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when the mode is changed to IDLE whilst a shortfall is ongoing. If this
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happens, statistics are rolled back to their values at the beginning of the
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shortfall.
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The backup of previous values is implemented in handle_shortfall when a new
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shortfall is detected, and the rollback is implemented by the
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checked_rollback routine. This routine is executed by the TX and RX loops
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before returning to the idle loop.
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Organisation
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============
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The rest of this file is organised as follows:
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- Constant definitions
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- Fixed register allocations
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- Macros
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- Ordering constraints
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- Finally, the actual code!
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*/
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// Constants that point to registers we'll need to modify in the SGPIO block.
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.equ SGPIO_SHADOW_REGISTERS_BASE, 0x40101100
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.equ SGPIO_EXCHANGE_INTERRUPT_BASE, 0x40101F00
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// Offsets into the interrupt control registers.
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.equ INT_CLEAR, 0x30
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.equ INT_STATUS, 0x2C
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// Buffer that we're funneling data to/from.
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.equ TARGET_DATA_BUFFER, 0x20008000
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.equ TARGET_BUFFER_SIZE, 0x8000
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.equ TARGET_BUFFER_MASK, 0x7fff
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// Base address of the state structure.
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.equ STATE_BASE, 0x20007000
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// Offsets into the state structure.
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.equ REQUESTED_MODE, 0x00
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.equ ACTIVE_MODE, 0x04
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.equ M0_COUNT, 0x08
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.equ M4_COUNT, 0x0C
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.equ NUM_SHORTFALLS, 0x10
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.equ LONGEST_SHORTFALL, 0x14
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.equ SHORTFALL_LIMIT, 0x18
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.equ THRESHOLD, 0x1C
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.equ NEXT_MODE, 0x20
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.equ ERROR, 0x24
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// Private variables stored after state.
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.equ PREV_LONGEST_SHORTFALL, 0x28
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// Operating modes.
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.equ MODE_IDLE, 0
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.equ MODE_WAIT, 1
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.equ MODE_RX, 2
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.equ MODE_TX_START, 3
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.equ MODE_TX_RUN, 4
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// Error codes.
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.equ ERROR_NONE, 0
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.equ ERROR_RX_TIMEOUT, 1
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.equ ERROR_TX_TIMEOUT, 2
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// Our slice chain is set up as follows (ascending data age; arrows are reversed for flow):
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// L -> F -> K -> C -> J -> E -> I -> A
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// Which has equivalent shadow register offsets:
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// 44 -> 20 -> 40 -> 8 -> 36 -> 16 -> 32 -> 0
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.equ SLICE0, 44
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.equ SLICE1, 20
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.equ SLICE2, 40
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.equ SLICE3, 8
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.equ SLICE4, 36
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.equ SLICE5, 16
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.equ SLICE6, 32
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.equ SLICE7, 0
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/* Allocations of single-use registers */
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buf_size_minus_32 .req r14
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state .req r13
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buf_base .req r12
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buf_mask .req r11
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shortfall_length .req r10
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hi_zero .req r9
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sgpio_data .req r7
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sgpio_int .req r6
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count .req r5
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buf_ptr .req r4
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/* Macros */
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.macro await_sgpio name
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// Wait for, then clear, SGPIO exchange interrupt flag.
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//
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// Clobbers:
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int_status .req r0
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scratch .req r1
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// The worst case timing is assumed to occur when reading the interrupt
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// status register *just* misses the flag being set - so we include the
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// cycles required to check it a second time.
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//
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// We also assume that we can spend a full 10 cycles doing an ldr from
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// SGPIO the first time (2 for ldr, plus 8 for SGPIO-AHB bus latency),
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// and still miss a flag that was set at the start of those 10 cycles.
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//
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// This latter asssumption is probably slightly pessimistic, since the
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// sampling of the flag on the SGPIO side must occur some time after
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// the ldr instruction begins executing on the M0. However, we avoid
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// relying on any assumptions about the timing details of a read over
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// the SGPIO to AHB bridge.
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\name\()_int_wait:
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// Spin on the exchange interrupt status, shifting the slice A flag to the carry flag.
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ldr int_status, [sgpio_int, #INT_STATUS] // int_status = SGPIO_STATUS_1 // 10, twice
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lsr scratch, int_status, #1 // scratch = int_status >> 1 // 1, twice
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bcc \name\()_int_wait // if !carry: goto int_wait // 3, then 1
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// Clear the interrupt pending bits that were set.
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str int_status, [sgpio_int, #INT_CLEAR] // SGPIO_CLR_STATUS_1 = int_status // 8
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.endm
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.macro on_request label
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// Check if a new mode change request was made, and if so jump to the given label.
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mode .req r3
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flag .req r2
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ldr mode, [state, #REQUESTED_MODE] // mode = state.requested_mode // 2
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lsr flag, mode, #16 // flag = mode >> 16 // 1
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bne \label // if flag != 0: goto label // 1 thru, 3 taken
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.endm
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.macro update_buf_ptr
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// Update the address of the buffer segment we want to write to / read from.
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mov buf_ptr, buf_mask // buf_ptr = buf_mask // 1
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and buf_ptr, count // buf_ptr &= count // 1
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add buf_ptr, buf_base // buf_ptr += buf_base // 1
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.endm
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.macro update_counts
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// Update counts after successful SGPIO operation.
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// Update the byte count and store the new value.
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add count, #32 // count += 32 // 1
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str count, [state, #M0_COUNT] // state.m0_count = count // 2
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// We didn't have a shortfall, so the current shortfall length is zero.
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mov shortfall_length, hi_zero // shortfall_length = hi_zero // 1
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.endm
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.macro jump_next_mode name
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// Jump to next mode if the byte count threshold has been reached.
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//
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// Clobbers:
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threshold .req r0
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new_mode .req r1
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// Check count against threshold. If not a match, return to start of current loop.
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ldr threshold, [state, #THRESHOLD] // threshold = state.threshold // 2
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cmp count, threshold // if count != threshold: // 1
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bne \name\()_loop // goto loop // 1 thru, 3 taken
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// Otherwise, load and set new mode.
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ldr new_mode, [state, #NEXT_MODE] // new_mode = state.next_mode // 2
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str new_mode, [state, #ACTIVE_MODE] // state.active_mode = new_mode // 2
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// Branch according to new mode.
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cmp new_mode, #MODE_RX // if new_mode == RX: // 1
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beq rx_loop // goto rx_loop // 1 thru, 3 taken
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bgt tx_loop // elif new_mode > RX: goto tx_loop // 1 thru, 3 taken
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cmp new_mode, #MODE_WAIT // if new_mode == WAIT: // 1
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beq wait_loop // goto wait_loop // 1 thru, 3 taken
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b idle // goto idle // 3
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.endm
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.macro handle_shortfall name
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// Handle a shortfall.
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//
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// Clobbers:
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length .req r0
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num .req r1
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prev .req r1
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longest .req r1
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limit .req r1
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// Get current shortfall length from high register.
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mov length, shortfall_length // length = shortfall_length // 1
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// Is this a new shortfall?
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cmp length, #0 // if length > 0: // 1
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bgt \name\()_extend_shortfall // goto extend_shortfall // 1 thru, 3 taken
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// If so, increase the shortfall count.
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ldr num, [state, #NUM_SHORTFALLS] // num = state.num_shortfalls // 2
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add num, #1 // num += 1 // 1
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str num, [state, #NUM_SHORTFALLS] // state.num_shortfalls = num // 2
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// Back up previous longest shortfall.
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ldr prev, [state, #LONGEST_SHORTFALL] // prev = state.longest_shortfall // 2
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str prev, [state, #PREV_LONGEST_SHORTFALL] // prev_longest_shortfall = prev // 2
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\name\()_extend_shortfall:
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// Extend the length of the current shortfall, and store back in high register.
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add length, #32 // length += 32 // 1
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mov shortfall_length, length // shortfall_length = length // 1
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// Is this now the longest shortfall?
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ldr longest, [state, #LONGEST_SHORTFALL] // longest = state.longest_shortfall // 2
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cmp length, longest // if length <= longest: // 1
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blt \name\()_loop // goto loop // 1 thru, 3 taken
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str length, [state, #LONGEST_SHORTFALL] // state.longest_shortfall = length // 2
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// Is this shortfall long enough to trigger a timeout?
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ldr limit, [state, #SHORTFALL_LIMIT] // limit = state.shortfall_limit // 2
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cmp limit, #0 // if limit == 0: // 1
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beq \name\()_loop // goto loop // 1 thru, 3 taken
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cmp length, limit // if length < limit: // 1
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blt \name\()_loop // goto loop // 1 thru, 3 taken
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// If so, reset mode to idle and return to idle loop, logging an error.
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//
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// Modes are mapped to errors as follows:
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//
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// MODE_RX (2) -> ERROR_RX_TIMEOUT (1)
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// MODE_TX_RUN (4) -> ERROR_TX_TIMEOUT (2)
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//
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// As such, the error code can be obtained by shifting the mode right by 1 bit.
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mode .req r3
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error .req r2
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ldr mode, [state, #ACTIVE_MODE] // mode = state.active_mode // 2
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lsr error, mode, #1 // error = mode >> 1 // 1
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str error, [state, #ERROR] // state.error = error // 2
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mov mode, #MODE_IDLE // mode = MODE_IDLE // 1
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str mode, [state, #ACTIVE_MODE] // state.active_mode = mode // 2
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b idle // goto idle // 3
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.endm
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/*
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Ordering constraints
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====================
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The following routines are in an unusual order, to preserve the ability to
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use PC-relative conditional branches between them ("b<cond> label"). The
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ordering has been chosen to ensure that all routines are close enough to each
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other for the limited range of these instructions (−256 bytes to +254 bytes).
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The ordering of routines, and which others each needs to be able to reach, is
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as follows:
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Routine: Uses conditional branches to:
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idle tx_loop, wait_loop
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tx_zeros tx_loop
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checked_rollback idle
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tx_loop tx_zeros, checked_rollback, rx_loop, wait_loop
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wait_loop rx_loop, tx_loop
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rx_loop rx_shortfall, checked_rollback, tx_loop, wait_loop
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rx_shortfall rx_loop
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If any of these routines are reordered, or made longer, you may get an error
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from the assembler saying that a branch is out of range.
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*/
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// Entry point. At this point, the libopencm3 startup code has set things up as
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// normal; .data and .bss are initialised, the stack is set up, etc. However,
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// we don't actually use any of that. All the code in this file would work
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// fine if the M0 jumped straight to main at reset.
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.global main
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.thumb_func
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main: // Cycle counts:
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// Initialise registers used for constant values.
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value .req r0
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ldr sgpio_int, =SGPIO_EXCHANGE_INTERRUPT_BASE // sgpio_int = SGPIO_INT_BASE // 2
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ldr sgpio_data, =SGPIO_SHADOW_REGISTERS_BASE // sgpio_data = SGPIO_REG_SS // 2
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ldr value, =(TARGET_BUFFER_SIZE - 32) // value = TARGET_BUFFER_SIZE - 32 // 2
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mov buf_size_minus_32, value // buf_size_minus_32 = value // 1
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ldr value, =TARGET_DATA_BUFFER // value = TARGET_DATA_BUFFER // 2
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mov buf_base, value // buf_base = value // 1
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ldr value, =TARGET_BUFFER_MASK // value = TARGET_DATA_MASK // 2
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mov buf_mask, value // buf_mask = value // 1
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ldr value, =STATE_BASE // value = STATE_BASE // 2
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mov state, value // state = value // 1
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zero .req r0
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mov zero, #0 // zero = 0 // 1
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mov hi_zero, zero // hi_zero = zero // 1
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// Initialise state.
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str zero, [state, #REQUESTED_MODE] // state.requested_mode = zero // 2
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str zero, [state, #ACTIVE_MODE] // state.active_mode = zero // 2
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str zero, [state, #M0_COUNT] // state.m0_count = zero // 2
|
||
str zero, [state, #M4_COUNT] // state.m4_count = zero // 2
|
||
str zero, [state, #NUM_SHORTFALLS] // state.num_shortfalls = zero // 2
|
||
str zero, [state, #LONGEST_SHORTFALL] // state.longest_shortfall = zero // 2
|
||
str zero, [state, #SHORTFALL_LIMIT] // state.shortfall_limit = zero // 2
|
||
str zero, [state, #THRESHOLD] // state.threshold = zero // 2
|
||
str zero, [state, #NEXT_MODE] // state.next_mode = zero // 2
|
||
str zero, [state, #ERROR] // state.error = zero // 2
|
||
|
||
idle:
|
||
// Wait for a mode to be requested, then set up the new mode and acknowledge the request.
|
||
mode .req r3
|
||
flag .req r2
|
||
zero .req r0
|
||
|
||
// Read the requested mode and check flag to see if this is a new request. If not, ignore.
|
||
ldr mode, [state, #REQUESTED_MODE] // mode = state.requested_mode // 2
|
||
lsr flag, mode, #16 // flag = mode >> 16 // 1
|
||
beq idle // if flag == 0: goto idle // 1 thru, 3 taken
|
||
|
||
// Otherwise, this is a new request. The M4 is blocked at this point,
|
||
// waiting for us to clear the request flag. So we can safely write to
|
||
// all parts of the state.
|
||
|
||
// Set the new mode as both active & next.
|
||
uxth mode, mode // mode = mode & 0xFFFF // 1
|
||
str mode, [state, #ACTIVE_MODE] // state.active_mode = mode // 2
|
||
str mode, [state, #NEXT_MODE] // state.next_mode = mode // 2
|
||
|
||
// Don't reset counts on a transition to IDLE.
|
||
cmp mode, #MODE_IDLE // if mode == IDLE: // 1
|
||
beq ack_request // goto ack_request // 1 thru, 3 taken
|
||
|
||
// For all other transitions, reset counts.
|
||
mov zero, #0 // zero = 0 // 1
|
||
str zero, [state, #M0_COUNT] // state.m0_count = zero // 2
|
||
str zero, [state, #M4_COUNT] // state.m4_count = zero // 2
|
||
str zero, [state, #NUM_SHORTFALLS] // state.num_shortfalls = zero // 2
|
||
str zero, [state, #LONGEST_SHORTFALL] // state.longest_shortfall = zero // 2
|
||
str zero, [state, #THRESHOLD] // state.threshold = zero // 2
|
||
str zero, [state, #PREV_LONGEST_SHORTFALL] // prev_longest_shortfall = zero // 2
|
||
str zero, [state, #ERROR] // state.error = zero // 2
|
||
mov shortfall_length, zero // shortfall_length = zero // 1
|
||
mov count, zero // count = zero // 1
|
||
|
||
ack_request:
|
||
// Clear SGPIO interrupt flag, which the M4 set to get our attention.
|
||
str flag, [sgpio_int, #INT_CLEAR] // SGPIO_CLR_STATUS_1 = flag // 8
|
||
|
||
// Write back requested mode with the flag cleared to acknowledge the request.
|
||
str mode, [state, #REQUESTED_MODE] // state.requested_mode = mode // 2
|
||
|
||
// Dispatch to appropriate loop.
|
||
//
|
||
// This code is arranged such that the branch to rx_loop is the
|
||
// unconditional one - which is necessary since it's too far away to
|
||
// use a conditional branch instruction.
|
||
cmp mode, #MODE_WAIT // if mode < WAIT: // 1
|
||
blt idle // goto idle // 1 thru, 3 taken
|
||
beq wait_loop // elif mode == WAIT: goto wait_loop // 1 thru, 3 taken
|
||
cmp mode, #MODE_RX // if mode > RX: // 1
|
||
bgt tx_loop // goto tx_loop // 1 thru, 3 taken
|
||
b rx_loop // goto rx_loop // 3
|
||
|
||
tx_zeros:
|
||
|
||
// Write zeros to SGPIO.
|
||
mov zero, #0 // zero = 0 // 1
|
||
str zero, [sgpio_data, #SLICE0] // SGPIO_REG_SS[SLICE0] = zero // 8
|
||
str zero, [sgpio_data, #SLICE1] // SGPIO_REG_SS[SLICE1] = zero // 8
|
||
str zero, [sgpio_data, #SLICE2] // SGPIO_REG_SS[SLICE2] = zero // 8
|
||
str zero, [sgpio_data, #SLICE3] // SGPIO_REG_SS[SLICE3] = zero // 8
|
||
str zero, [sgpio_data, #SLICE4] // SGPIO_REG_SS[SLICE4] = zero // 8
|
||
str zero, [sgpio_data, #SLICE5] // SGPIO_REG_SS[SLICE5] = zero // 8
|
||
str zero, [sgpio_data, #SLICE6] // SGPIO_REG_SS[SLICE6] = zero // 8
|
||
str zero, [sgpio_data, #SLICE7] // SGPIO_REG_SS[SLICE7] = zero // 8
|
||
|
||
// If in TX start mode, don't count this as a shortfall.
|
||
ldr mode, [state, #ACTIVE_MODE] // mode = state.active_mode // 2
|
||
cmp mode, #MODE_TX_START // if mode == TX_START: // 1
|
||
beq tx_loop // goto tx_loop // 1 thru, 3 taken
|
||
|
||
// Run common shortfall handling and jump back to TX loop start.
|
||
handle_shortfall tx // handle_shortfall() // 24
|
||
|
||
checked_rollback:
|
||
// Checked rollback handler. This code is run when the M0 is in a TX or RX mode, and is
|
||
// placed back into IDLE mode by the M4. If there is an ongoing shortfall at this point,
|
||
// it is assumed to be a shutdown artifact and rolled back.
|
||
|
||
// If there is no ongoing shortfall, there's nothing to do - jump back to idle loop.
|
||
length .req r0
|
||
mov length, shortfall_length // length = shortfall_length // 1
|
||
cmp length, #0 // if length == 0: // 1
|
||
beq idle // goto idle // 3
|
||
|
||
// Otherwise, roll back the state to ignore the current shortfall, then jump to idle.
|
||
prev .req r0
|
||
ldr prev, [state, #PREV_LONGEST_SHORTFALL] // prev = prev_longest_shortfall // 2
|
||
str prev, [state, #LONGEST_SHORTFALL] // state.longest_shortfall = prev // 2
|
||
ldr prev, [state, #NUM_SHORTFALLS] // prev = num_shortfalls // 2
|
||
sub prev, #1 // prev -= 1 // 1
|
||
str prev, [state, #NUM_SHORTFALLS] // state.num_shortfalls = prev // 2
|
||
|
||
b idle // goto idle // 3
|
||
|
||
tx_loop:
|
||
|
||
// Wait for and clear SGPIO interrupt.
|
||
await_sgpio tx // await_sgpio() // 34
|
||
|
||
// Check if there is a mode change request.
|
||
// If so, we may need to roll back shortfall stats.
|
||
on_request checked_rollback // 4
|
||
|
||
// Check if there is enough data in the buffer.
|
||
//
|
||
// The number of bytes in the buffer is given by (m4_count - m0_count).
|
||
// We need 32 bytes available to proceed. So our margin, which we want
|
||
// to be positive or zero, is:
|
||
//
|
||
// buf_margin = m4_count - m0_count - 32
|
||
//
|
||
// If there is insufficient data, transmit zeros instead.
|
||
buf_margin .req r0
|
||
ldr buf_margin, [state, #M4_COUNT] // buf_margin = m4_count // 2
|
||
sub buf_margin, count // buf_margin -= count // 1
|
||
sub buf_margin, #32 // buf_margin -= 32 // 1
|
||
bmi tx_zeros // if buf_margin < 0: goto tx_zeros // 1 thru, 3 taken
|
||
|
||
// Update buffer pointer.
|
||
update_buf_ptr // update_buf_ptr() // 3
|
||
|
||
// At this point we know there is TX data available.
|
||
// Set active mode to TX_RUN (it might still be TX_START).
|
||
mov mode, #MODE_TX_RUN // mode = TX_RUN // 1
|
||
str mode, [state, #ACTIVE_MODE] // state.active_mode = mode // 2
|
||
|
||
// Write data to SGPIO.
|
||
ldm buf_ptr!, {r0-r3} // r0-r3 = buf_ptr[0:16]; buf_ptr += 16 // 5
|
||
str r0, [sgpio_data, #SLICE0] // SGPIO_REG_SS[SLICE0] = r0 // 8
|
||
str r1, [sgpio_data, #SLICE1] // SGPIO_REG_SS[SLICE1] = r1 // 8
|
||
str r2, [sgpio_data, #SLICE2] // SGPIO_REG_SS[SLICE2] = r2 // 8
|
||
str r3, [sgpio_data, #SLICE3] // SGPIO_REG_SS[SLICE3] = r3 // 8
|
||
ldm buf_ptr!, {r0-r3} // r0-r3 = buf_ptr[0:16]; buf_ptr += 16 // 5
|
||
str r0, [sgpio_data, #SLICE4] // SGPIO_REG_SS[SLICE4] = r0 // 8
|
||
str r1, [sgpio_data, #SLICE5] // SGPIO_REG_SS[SLICE5] = r1 // 8
|
||
str r2, [sgpio_data, #SLICE6] // SGPIO_REG_SS[SLICE6] = r2 // 8
|
||
str r3, [sgpio_data, #SLICE7] // SGPIO_REG_SS[SLICE7] = r3 // 8
|
||
|
||
// Update counts.
|
||
update_counts // update_counts() // 4
|
||
|
||
// Jump to next mode if threshold reached, or back to TX loop start.
|
||
jump_next_mode tx // jump_next_mode() // 13
|
||
|
||
wait_loop:
|
||
|
||
// Wait for and clear SGPIO interrupt.
|
||
await_sgpio wait // await_sgpio() // 34
|
||
|
||
// Check if there is a mode change request.
|
||
// If so, return to idle.
|
||
on_request idle // 4
|
||
|
||
// Update counts.
|
||
update_counts // update_counts() // 4
|
||
|
||
// Jump to next mode if threshold reached, or back to wait loop start.
|
||
jump_next_mode wait // jump_next_mode() // 15
|
||
|
||
rx_loop:
|
||
|
||
// Wait for and clear SGPIO interrupt.
|
||
await_sgpio rx // await_sgpio() // 34
|
||
|
||
// Check if there is a mode change request.
|
||
// If so, we may need to roll back shortfall stats.
|
||
on_request checked_rollback // 4
|
||
|
||
// Check if there is enough space in the buffer.
|
||
//
|
||
// The number of bytes in the buffer is given by (m0_count - m4_count).
|
||
// We need space for another 32 bytes to proceed. So our margin, which
|
||
// we want to be positive or zero, is:
|
||
//
|
||
// buf_margin = buf_size - (m0_count - state.m4_count) - 32
|
||
//
|
||
// which can be rearranged for efficiency as:
|
||
//
|
||
// buf_margin = m4_count + (buf_size - 32) - m0_count
|
||
//
|
||
// If there is insufficient space, jump to shortfall handling.
|
||
buf_margin .req r0
|
||
ldr buf_margin, [state, #M4_COUNT] // buf_margin = state.m4_count // 2
|
||
add buf_margin, buf_size_minus_32 // buf_margin += buf_size_minus_32 // 1
|
||
sub buf_margin, count // buf_margin -= count // 1
|
||
bmi rx_shortfall // if buf_margin < 0: goto rx_shortfall // 1 thru, 3 taken
|
||
|
||
// Update buffer pointer.
|
||
update_buf_ptr // update_buf_ptr() // 3
|
||
|
||
// Read data from SGPIO.
|
||
ldr r0, [sgpio_data, #SLICE0] // r0 = SGPIO_REG_SS[SLICE0] // 10
|
||
ldr r1, [sgpio_data, #SLICE1] // r1 = SGPIO_REG_SS[SLICE1] // 10
|
||
ldr r2, [sgpio_data, #SLICE2] // r2 = SGPIO_REG_SS[SLICE2] // 10
|
||
ldr r3, [sgpio_data, #SLICE3] // r3 = SGPIO_REG_SS[SLICE3] // 10
|
||
stm buf_ptr!, {r0-r3} // buf_ptr[0:16] = r0-r3; buf_ptr += 16 // 5
|
||
ldr r0, [sgpio_data, #SLICE4] // r0 = SGPIO_REG_SS[SLICE4] // 10
|
||
ldr r1, [sgpio_data, #SLICE5] // r1 = SGPIO_REG_SS[SLICE5] // 10
|
||
ldr r2, [sgpio_data, #SLICE6] // r2 = SGPIO_REG_SS[SLICE6] // 10
|
||
ldr r3, [sgpio_data, #SLICE7] // r3 = SGPIO_REG_SS[SLICE7] // 10
|
||
stm buf_ptr!, {r0-r3} // buf_ptr[0:16] = r0-r3; buf_ptr += 16 // 5
|
||
|
||
// Update counts.
|
||
update_counts // update_counts() // 4
|
||
|
||
// Jump to next mode if threshold reached, or back to RX loop start.
|
||
jump_next_mode rx // jump_next_mode() // 12
|
||
|
||
rx_shortfall:
|
||
|
||
// Run common shortfall handling and jump back to RX loop.
|
||
handle_shortfall rx // handle_shortfall() // 24
|
||
|
||
// The linker will put a literal pool here, so add a label for clearer objdump output:
|
||
constants:
|