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This commit is contained in:
RocketGod
2022-09-22 09:26:57 -07:00
parent fee0ab05fd
commit 957ea3d712
4511 changed files with 1943182 additions and 0 deletions
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5
Software/portapack-mayhem/hardware/.gitignore vendored Normal file
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# Common
*.bak
# KiCad
*.kicad_pcb-bak

55
Software/portapack-mayhem/hardware/portapack_h1/README Normal file
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PortaPack H1 is portability add-on hardware for the HackRF One
software-defined radio (SDR).
Schematic
=========
The schematic was drawn using KiCad 4.0.6.
Schematic symbols are cached in the design files, but are also
available in a separate repository:
https://github.com/sharebrained/library-kicad/
PCB
===
The circuit board was designed using KiCad.
PCB footprints are cached in the design files, but are also
avaliable in a separate repository:
https://github.com/sharebrained/library-kicad/
The PCB is a four-layer design. Services such as OSHPark.com have suitable
four-layer stack ups.
CPLD
====
The CPLD bitstream is prepared using Altera Quartus tools.
The CPLD is programmed from within the PortaPack firmware, by bit-banging
the JTAG pins from the HackRF One's microcontroller.
License
=======
Copyright (C) 2013-2017 Jared Boone, ShareBrained Technology, Inc.
These files are part of PortaPack.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Street,
Boston, MA 02110-1301, USA.

911
Software/portapack-mayhem/hardware/portapack_h1/audio.sch Normal file
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EESchema Schematic File Version 4
LIBS:portapack_h1-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 6
Title "PortaPack H1"
Date "2018-10-29"
Rev "20181029"
Comp "ShareBrained Technology, Inc."
Comment1 "Copyright © 2014-2018 Jared Boone"
Comment2 "License: GNU General Public License, version 2"
Comment3 ""
Comment4 ""
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I2C Addresses on HackRF I2C bus (I2C0?):\n\n0b1100000: Si5351C-B\n0b0010010: AK4951 audio codec
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1 5100 4800
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$EndComp
$Comp
L header:HEADER_1X3 J1
U 1 1 58F82DA0
P 5800 2100
F 0 "J1" H 5800 1850 60 0000 C CNN
F 1 "HEADER_1X3" H 5800 1850 60 0001 C CNN
F 2 "jst:JST_S3B-PH-SM4-TB" H 5800 1900 60 0001 C CNN
F 3 "http://www.jst-mfg.com/product/pdf/eng/ePH.pdf" H 5800 1900 60 0001 C CNN
F 4 "JST" H 5800 2100 60 0001 C CNN "Mfr"
F 5 "S3B-PH-SM4-TB" H 5800 2100 60 0001 C CNN "Part"
F 6 "DNP" H 5800 2100 60 0000 C CNN "DNP"
1 5800 2100
1 0 0 1
$EndComp
$Comp
L power:GND #PWR018
U 1 1 58F8315C
P 5400 2100
F 0 "#PWR018" H 5400 2100 30 0001 C CNN
F 1 "GND" H 5400 2030 30 0001 C CNN
F 2 "" H 5400 2100 60 0000 C CNN
F 3 "" H 5400 2100 60 0000 C CNN
1 5400 2100
0 1 1 0
$EndComp
Wire Wire Line
9000 1900 10300 1900
Wire Wire Line
4600 1500 6400 1500
Wire Wire Line
4700 1600 6800 1600
Connection ~ 6400 1500
Wire Wire Line
5200 2900 5200 2800
Wire Wire Line
3800 3400 3900 3400
Wire Wire Line
2700 3800 2800 3800
Wire Wire Line
5700 3400 5800 3400
Wire Wire Line
5100 2900 5100 2800
Wire Wire Line
3900 3700 4000 3700
Wire Wire Line
4800 2900 4800 2800
Wire Wire Line
1000 6900 1200 6900
Connection ~ 1200 6900
Wire Wire Line
3200 6900 3400 6900
Connection ~ 3400 6900
Wire Wire Line
4300 6900 4500 6900
Connection ~ 4500 6900
Wire Wire Line
4500 2600 4500 2900
Wire Wire Line
3900 2600 4500 2600
Wire Wire Line
4000 3500 3100 3500
Wire Wire Line
3100 3500 3100 3000
Wire Wire Line
3100 3000 2800 3000
Wire Wire Line
2800 3600 4000 3600
Wire Wire Line
5700 4000 5800 4000
Wire Wire Line
5800 4100 5700 4100
Wire Wire Line
4700 2900 4700 1600
Wire Wire Line
4600 1500 4600 2900
Wire Wire Line
5700 3900 5800 3900
Wire Wire Line
5700 3800 6700 3800
Wire Wire Line
5700 3700 6700 3700
Wire Wire Line
5700 3600 6700 3600
Wire Wire Line
5700 3500 5800 3500
Wire Wire Line
5200 4600 5200 4700
Wire Wire Line
5200 4700 5400 4700
Wire Wire Line
4800 5300 4800 4600
Wire Wire Line
5000 6000 4700 6000
Connection ~ 4700 6000
Connection ~ 5400 4700
Wire Wire Line
4700 6400 5200 6400
Wire Wire Line
4000 4300 3900 4300
Wire Wire Line
9000 2000 10300 2000
Wire Wire Line
9200 3200 9100 3200
Wire Wire Line
9700 3800 9700 3700
Wire Wire Line
9000 2100 10300 2100
Wire Wire Line
5000 5300 4800 5300
Connection ~ 6800 1600
Wire Wire Line
9000 2200 10100 2200
Wire Wire Line
10100 2200 10100 2400
Wire Wire Line
10100 2400 10300 2400
Wire Wire Line
10900 3100 10200 3100
Wire Wire Line
10900 3200 10200 3200
Wire Wire Line
10900 3300 10200 3300
Wire Wire Line
10900 3400 10200 3400
Wire Wire Line
8600 3400 9200 3400
Wire Wire Line
8600 3300 9200 3300
Wire Wire Line
8600 3100 9200 3100
Wire Wire Line
4500 4700 4500 4600
Wire Wire Line
4600 4700 4600 4600
Wire Wire Line
4900 4700 4900 4600
Wire Wire Line
5000 4700 5000 4600
Wire Wire Line
5100 4700 5100 4600
Wire Wire Line
3700 4100 4000 4100
Connection ~ 3900 3400
Wire Wire Line
3700 4100 3700 4700
Wire Wire Line
4000 4000 3500 4000
Wire Wire Line
3500 4000 3500 4300
Wire Wire Line
4000 3900 3400 3900
Wire Wire Line
3400 3900 3400 4000
Wire Wire Line
2800 3800 2800 4000
Connection ~ 2800 3800
Connection ~ 2800 4000
Wire Wire Line
5500 2000 4900 2000
Wire Wire Line
4900 2000 4900 2900
Wire Wire Line
5500 2200 5000 2200
Wire Wire Line
5000 2200 5000 2900
Wire Wire Line
5500 2100 5400 2100
$Comp
L passive:RPACK4 RP1
U 1 1 58F9564A
P 6900 3750
F 0 "RP1" H 6900 4000 60 0000 C CNN
F 1 "220R" H 6900 3500 60 0000 C CNN
F 2 "ipc_rescax:IPC_RESCAXS8P80_320X160X60L30X45N" H 6900 3750 60 0001 C CNN
F 3 "https://industrial.panasonic.com/cdbs/www-data/pdf/AOC0000/AOC0000C14.pdf" H 6900 3750 60 0001 C CNN
F 4 "Panasonic" H 6900 3750 60 0001 C CNN "Mfr"
F 5 "EXB-38V221JV" H 6900 3750 60 0001 C CNN "Part"
1 6900 3750
1 0 0 -1
$EndComp
Wire Wire Line
6700 3900 6600 3900
Wire Wire Line
6600 3900 6600 4700
Wire Wire Line
7100 3600 7200 3600
Wire Wire Line
7200 3700 7100 3700
Wire Wire Line
7100 3800 7200 3800
Wire Wire Line
7200 3900 7100 3900
Text Label 6200 3600 0 60 ~ 0
BICK_R
Text Label 6200 3700 0 60 ~ 0
LRCK_R
Text Label 6200 3800 0 60 ~ 0
SDTO_R
Text Label 5600 4700 0 60 ~ 0
PDN#_R
Text Label 5100 2000 0 60 ~ 0
SPP
Text Label 5100 2200 0 60 ~ 0
SPN
Wire Wire Line
2100 6900 2300 6900
Text Notes 1800 7700 0 60 ~ 0
No 10U on DVDD, very near regulator 10U.
Text Notes 4250 7700 0 60 ~ 0
No 10U on SVDD to comply with USB inrush spec.
Wire Wire Line
6400 1500 7600 1500
Wire Wire Line
1200 6900 1600 6900
Wire Wire Line
3400 6900 3800 6900
Wire Wire Line
4500 6900 4900 6900
Wire Wire Line
4700 6000 4700 6400
Wire Wire Line
5400 4700 6600 4700
Wire Wire Line
6800 1600 7600 1600
Wire Wire Line
3900 3400 4000 3400
Wire Wire Line
2800 3800 4000 3800
Wire Wire Line
2800 4000 2800 4300
Wire Wire Line
3900 2600 3900 2950
Wire Wire Line
3900 3250 3900 3400
Wire Wire Line
2800 3000 2800 3150
Wire Wire Line
2800 3600 2800 3450
Wire Wire Line
2800 4000 2950 4000
Wire Wire Line
2800 4300 2950 4300
Wire Wire Line
3250 4300 3500 4300
Wire Wire Line
3250 4000 3400 4000
Wire Wire Line
4700 4600 4700 5450
Wire Wire Line
4700 5750 4700 6000
Wire Wire Line
5000 5300 5000 5500
Wire Wire Line
5000 5800 5000 6000
Wire Wire Line
5400 5200 5400 5400
Wire Wire Line
5400 4700 5400 4900
Wire Wire Line
6400 2550 6400 2750
Wire Wire Line
6400 2000 6400 2250
Wire Wire Line
6400 1500 6400 1700
Wire Wire Line
6800 1600 6800 1700
Wire Wire Line
6800 2000 6800 2250
Wire Wire Line
6800 2550 6800 2750
Wire Wire Line
1200 6900 1200 7050
Wire Wire Line
1200 7350 1200 7500
Wire Wire Line
1600 7350 1600 7500
Wire Wire Line
1600 6900 1600 7050
Wire Wire Line
2300 6900 2300 7050
Wire Wire Line
2300 7350 2300 7500
Wire Wire Line
3400 7350 3400 7500
Wire Wire Line
3400 6900 3400 7050
Wire Wire Line
3800 6900 3800 7050
Wire Wire Line
3800 7350 3800 7500
Wire Wire Line
4500 7350 4500 7500
Wire Wire Line
4500 6900 4500 7050
Wire Wire Line
4900 6900 4900 7050
Wire Wire Line
4900 7350 4900 7500
$EndSCHEMATC

14
Software/portapack-mayhem/hardware/portapack_h1/cpld/.gitignore vendored Normal file
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@@ -0,0 +1,14 @@
**/*.qws
**/*.chg
**/smart.log
**/db/
**/incremental_db/
**/output_files/*.done
**/output_files/*.smsg
**/output_files/*.summary
**/output_files/*.jdi
**/output_files/*.pin
**/output_files/*.pof
**/output_files/*.rpt
**/output_files/*.sld
**/simulation/

108
Software/portapack-mayhem/hardware/portapack_h1/cpld/20150901/Makefile Normal file
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@@ -0,0 +1,108 @@
#
# Copyright (C) 2017 Jared Boone, ShareBrained Technology, Inc.
#
# This file is part of PortaPack.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
# Makefile based on Altera Quartus documentation example, topic
# "About Using Quartus II from the Command Line"
###################################################################
# Project Configuration:
#
# Specify the name of the design (project) and Quartus II Settings
# File (.qsf) and the list of source files used.
###################################################################
PROJECT=portapack_h1_cpld
SOURCE_FILES=top.vhd
ASSIGNMENT_FILES=$(PROJECT).qpf $(PROJECT).qsf $(PROJECT).sdc
OUTPUT_DIR=output_files
###################################################################
# Main Targets
#
# all: build everything
# clean: remove output files and database
###################################################################
all: smart.log $(OUTPUT_DIR)/$(PROJECT).asm.rpt $(OUTPUT_DIR)/$(PROJECT).sta.rpt
clean:
rm -rf *.chg *.qws smart.log db/ incremental_db/ $(OUTPUT_DIR)/
map: smart.log $(OUTPUT_DIR)/$(PROJECT).map.rpt
fit: smart.log $(OUTPUT_DIR)/$(PROJECT).fit.rpt
asm: smart.log $(OUTPUT_DIR)/$(PROJECT).asm.rpt
sta: smart.log $(OUTPUT_DIR)/$(PROJECT).sta.rpt
smart: smart.log
###################################################################
# Executable Configuration
###################################################################
MAP_ARGS=
FIT_ARGS=
ASM_ARGS=
STA_ARGS=
###################################################################
# Target implementations
###################################################################
STAMP = echo done >
$(OUTPUT_DIR)/$(PROJECT).map.rpt: $(SOURCE_FILES)
quartus_map $(MAP_ARGS) $(PROJECT)
$(STAMP) fit.chg
$(OUTPUT_DIR)/$(PROJECT).fit.rpt: fit.chg $(OUTPUT_DIR)/$(PROJECT).map.rpt
quartus_fit $(FIT_ARGS) $(PROJECT)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(OUTPUT_DIR)/$(PROJECT).asm.rpt: asm.chg $(OUTPUT_DIR)/$(PROJECT).fit.rpt
quartus_asm $(ASM_ARGS) $(PROJECT)
$(OUTPUT_DIR)/$(PROJECT).sta.rpt: sta.chg $(OUTPUT_DIR)/$(PROJECT).fit.rpt
quartus_sta $(STA_ARGS) $(PROJECT)
smart.log: $(ASSIGNMENT_FILES) $(OUTPUT_DIR)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
###################################################################
# Project initialization
###################################################################
$(OUTPUT_DIR):
mkdir $(OUTPUT_DIR)
$(ASSIGNMENT_FILES): $(OUTPUT_DIR)
quartus_sh --prepare $(PROJECT)
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg

11651
Software/portapack-mayhem/hardware/portapack_h1/cpld/20150901/output_files/portapack_h1_cpld.svf Normal file
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File diff suppressed because it is too large Load Diff

30
Software/portapack-mayhem/hardware/portapack_h1/cpld/20150901/portapack_h1_cpld.qpf Normal file
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@@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:24:55 April 29, 2014
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "21:24:55 April 29, 2014"
# Revisions
PROJECT_REVISION = "portapack_h1_cpld"

319
Software/portapack-mayhem/hardware/portapack_h1/cpld/20150901/portapack_h1_cpld.qsf Normal file
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@@ -0,0 +1,319 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:24:55 April 29, 2014
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# portapack_h1_cpld_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX V"
set_global_assignment -name DEVICE 5M40ZE64C5
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:24:55 APRIL 29, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 64
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SDC_FILE portapack_h1_cpld.sdc
set_global_assignment -name VHDL_FILE top.vhd
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
set_location_assignment PIN_46 -to LCD_DB[15]
set_location_assignment PIN_47 -to LCD_DB[14]
set_location_assignment PIN_48 -to LCD_DB[13]
set_location_assignment PIN_49 -to LCD_DB[12]
set_location_assignment PIN_50 -to LCD_DB[11]
set_location_assignment PIN_51 -to LCD_DB[10]
set_location_assignment PIN_52 -to LCD_DB[9]
set_location_assignment PIN_53 -to LCD_DB[8]
set_location_assignment PIN_54 -to LCD_DB[7]
set_location_assignment PIN_55 -to LCD_DB[6]
set_location_assignment PIN_56 -to LCD_DB[5]
set_location_assignment PIN_58 -to LCD_DB[4]
set_location_assignment PIN_59 -to LCD_DB[3]
set_location_assignment PIN_60 -to LCD_DB[2]
set_location_assignment PIN_61 -to LCD_DB[1]
set_location_assignment PIN_62 -to LCD_DB[0]
set_location_assignment PIN_44 -to LCD_RDX
set_location_assignment PIN_43 -to LCD_RS
set_location_assignment PIN_63 -to LCD_TE
set_location_assignment PIN_45 -to LCD_WRX
set_location_assignment PIN_10 -to SW_D
set_location_assignment PIN_28 -to SW_L
set_location_assignment PIN_9 -to SW_R
set_location_assignment PIN_11 -to SW_ROT_A
set_location_assignment PIN_12 -to SW_ROT_B
set_location_assignment PIN_13 -to SW_SEL
set_location_assignment PIN_25 -to SW_U
set_location_assignment PIN_1 -to TP_D
set_location_assignment PIN_2 -to TP_L
set_location_assignment PIN_64 -to TP_R
set_location_assignment PIN_3 -to TP_U
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_D
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_L
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_R
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_A
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_B
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_SEL
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_U
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_D
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_L
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_R
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_U
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[15]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[14]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[13]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[12]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[11]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[10]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[9]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[8]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[7]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[6]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[5]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RDX
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RS
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_TE
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_WRX
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH top_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME top_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME uut -section_id top_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME top_tb -section_id top_tb
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id top_tb
set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.vhd -section_id top_tb
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR /home/jboone/src/portapack/portapack_hackrf/hardware/portapack_h1/cpld -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name GENERATE_RBF_FILE OFF
set_global_assignment -name GENERATE_SVF_FILE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH BUS-HOLD"
set_location_assignment PIN_38 -to LCD_RESETX
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RESETX
set_location_assignment PIN_18 -to MCU_D[7]
set_location_assignment PIN_19 -to MCU_D[6]
set_location_assignment PIN_21 -to MCU_D[5]
set_location_assignment PIN_20 -to MCU_D[4]
set_location_assignment PIN_22 -to MCU_D[3]
set_location_assignment PIN_24 -to MCU_D[2]
set_location_assignment PIN_27 -to MCU_D[1]
set_location_assignment PIN_26 -to MCU_D[0]
set_location_assignment PIN_33 -to MCU_ADDR
set_location_assignment PIN_42 -to MCU_DIR
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_ADDR
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_DIR
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_D
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_L
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_R
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_U
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_B
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_SEL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_A
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RDX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RESETX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_TE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_WRX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_ADDR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_L
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_R
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_A
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_B
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_SEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_U
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_L
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_R
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_U
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[15]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[14]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[13]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[12]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[11]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[10]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[9]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[8]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[7]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[6]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[5]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[4]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[3]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[2]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[1]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[0]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RDX
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RESETX
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RS
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_TE
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_WRX
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_ADDR
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[7]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[6]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[5]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[4]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[3]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[2]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[1]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[0]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_DIR
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_D
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_L
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_R
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_A
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_B
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_SEL
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_U
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_D
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_L
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_R
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_U
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
set_global_assignment -name IOBANK_VCCIO 1.8V -section_id 2
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
set_instance_assignment -name PCI_IO OFF -to MCU_DIR
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER ON
set_location_assignment PIN_4 -to LCD_BACKLIGHT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_BACKLIGHT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_BACKLIGHT
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_BACKLIGHT
set_location_assignment PIN_30 -to MCU_LCD_RDX
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_RDX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_RDX
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_RDX
set_location_assignment PIN_40 -to MCU_LCD_WRX
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_WRX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_WRX
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_WRX
set_instance_assignment -name PCI_IO OFF -to MCU_LCD_WRX
set_location_assignment PIN_32 -to MCU_IO_STBX
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_IO_STBX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_IO_STBX
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_IO_STBX
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_R
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_D
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_L
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_U
set_location_assignment PIN_31 -to MCU_LCD_TE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_TE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_TE
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_TE
set_location_assignment PIN_34 -to MCU_P2_8
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_P2_8
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_P2_8
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_P2_8
set_instance_assignment -name PCI_IO OFF -to MCU_P2_8
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[15]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[14]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[13]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[12]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[11]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[10]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[9]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[8]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_ADDR
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_DIR
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_IO_STBX
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_LCD_RDX
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_LCD_WRX
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_P2_8

116
Software/portapack-mayhem/hardware/portapack_h1/cpld/20150901/portapack_h1_cpld.sdc Normal file
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## Generated SDC file "portapack_hackrf_one_cpld.sdc"
## Copyright (C) 1991-2014 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
## DATE "Sat May 3 10:22:18 2014"
##
## DEVICE "5M40ZE64C5"
##
# RS = 0, D = DB[15:8]
# wait max(tast = 0 ns, CPLD setup = ?)
# WR = 0, D = DB[7:0]
# wait max(CPLD )
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
set mcu_clk_period 4.9
set lcd_data_wr_setup 10.0
set lcd_data_wr_hold 10.0
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {MCU_LCD_WRX} -period 66.000 -waveform { 0.000 33.000 } [get_ports {MCU_LCD_WRX}]
#create_clock -name strobe_virt -period 66.000
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
#set_input_delay -clock strobe_virt [get_ports {D[*]}]
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#set_false_path -from [get_clocks {MCU_IO_STBX}] -to [get_ports {TP_D TP_L TP_R TP_U}]
#set_false_path -from [get_ports {SW_D SW_L SW_R SW_ROT_A SW_ROT_B SW_SEL SW_U}] -to [get_ports {MCU_D[*]}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

167
Software/portapack-mayhem/hardware/portapack_h1/cpld/20150901/top.vhd Normal file
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--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WRX : in std_logic;
MCU_ADDR : in std_logic;
MCU_LCD_TE : out std_logic;
MCU_P2_8 : in std_logic;
MCU_LCD_RDX : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_LCD_TE <= LCD_TE;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
lcd_read_strobe <= (MCU_LCD_RDX = '0');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= MCU_LCD_RDX;
LCD_WRX <= MCU_LCD_WRX;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
LCD_RESETX <= not lcd_reset_q;
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WRX, mcu_data_in)
begin
if falling_edge(MCU_LCD_WRX) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RDX, lcd_data_in)
begin
if rising_edge(MCU_LCD_RDX) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;

185
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--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top_tb is
end top_tb;
architecture behavior of top_tb is
component top
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_MODE : in std_logic;
MCU_STROBE : in std_logic;
MCU_ADDR : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(17 downto 0);
LCD_TE : in std_logic
);
end component;
signal mcu_d : std_logic_vector(7 downto 0);
signal mcu_strobe : std_logic;
signal mcu_dir : std_logic;
signal mcu_mode : std_logic;
signal mcu_addr : std_logic;
signal tp_u : std_logic;
signal tp_d : std_logic;
signal tp_l : std_logic;
signal tp_r : std_logic;
signal sw_sel : std_logic;
signal sw_rot_a : std_logic;
signal sw_rot_b : std_logic;
signal sw_u : std_logic;
signal sw_d : std_logic;
signal sw_l : std_logic;
signal sw_r : std_logic;
signal lcd_resetx : std_logic;
signal lcd_rs : std_logic;
signal lcd_wrx : std_logic;
signal lcd_rdx : std_logic;
signal lcd_db : std_logic_vector(17 downto 0);
signal lcd_te : std_logic := '0';
begin
uut : top
port map (
MCU_D => mcu_d,
MCU_STROBE => mcu_strobe,
MCU_DIR => mcu_dir,
MCU_MODE => mcu_mode,
MCU_ADDR => mcu_addr,
TP_U => tp_u,
TP_D => tp_d,
TP_L => tp_l,
TP_R => tp_r,
SW_SEL => sw_sel,
SW_ROT_A => sw_rot_a,
SW_ROT_B => sw_rot_b,
SW_U => sw_u,
SW_D => sw_d,
SW_L => sw_l,
SW_R => sw_r,
LCD_RESETX => lcd_resetx,
LCD_RS => lcd_rs,
LCD_WRX => lcd_wrx,
LCD_RDX => lcd_rdx,
LCD_DB => lcd_db,
LCD_TE => lcd_te
);
stimulus: process is
begin
sw_sel <= '0';
sw_rot_a <= '0';
sw_rot_b <= '0';
sw_u <= '0';
sw_d <= '0';
sw_l <= '0';
sw_r <= '0';
mcu_d <= (others => 'Z');
mcu_mode <= '1';
mcu_dir <= '1';
mcu_addr <= '1';
mcu_strobe <= '1';
wait for 50.0 ns;
-- Write to resistive touch panel
mcu_mode <= '0'; -- Target: I/O
mcu_dir <= '0'; -- Direction: MCU -> CPLD
mcu_addr <= '0'; -- LCD reset signal
wait for 19.6 ns; -- 4 cycles: Wait for CPLD D to reach Hi-Z
mcu_d <= "11000101";
wait for 14.7 ns; -- 3 cycles: Setup time on D before STROBE.
mcu_strobe <= '0';
wait for 9.8 ns; -- 2 cycles
mcu_strobe <= '1';
wait for 49.0 ns;
-- Write to LCD (command, then 16-bit data)
mcu_mode <= '1'; -- Target: LCD
mcu_dir <= '0'; -- Direction: MCU -> CPLD
mcu_addr <= '0'; -- Address: RS = 0 (command)
wait for 19.6 ns; -- 4 cycles: Wait for CPLD D to reach Hi-Z
mcu_d <= "10100101";
wait for 14.7 ns; -- 3 cycles: Setup time on D before STROBE.
mcu_strobe <= '0';
wait for 9.8 ns; -- 2 cycles
mcu_d <= "00001111";
wait for 24.5 ns; -- 5 cycles: Prop from D to LCD_DB[7:0], WRX# minimum low time.
mcu_strobe <= '1';
wait for 9.8 ns; -- 2 cycles: Part of prop from STROBE to LCD_WRX, delay to keep RS after WRX deassert.
mcu_addr <= '1'; -- Address: RS = 1 (data)
wait for 9.8 ns; -- 2 cycles: Part of prop from STROBE to LCD_WRX.
mcu_d <= "01011010";
wait for 14.7 ns; -- 3 cycles: Setup time on D before STROBE.
mcu_strobe <= '0';
wait for 9.8 ns; -- 2 cycles
mcu_d <= "11110000";
wait for 24.5 ns; -- 5 cycles: Prop from D to LCD_DB[7:0], WRX# minimum low time.
mcu_strobe <= '1';
wait for 19.6 ns; -- 4 cycles: Prop from STROBE to LCD_WRX.
mcu_d <= "01010101";
wait for 14.7 ns; -- 3 cycles: Setup time on D before STROBE.
mcu_strobe <= '0';
wait for 9.8 ns; -- 2 cycles
mcu_d <= "10101010";
wait for 24.5 ns; -- 5 cycles: Prop from D to LCD_DB[7:0], WRX# minimum low time.
mcu_strobe <= '1';
wait for 19.6 ns; -- 4 cycles: Prop from STROBE to LCD_WRX.
-- Read from switches
mcu_d <= (others => 'Z');
mcu_mode <= '0'; -- Target: I/O
mcu_dir <= '1'; -- Direction: MCU <- CPLD
wait for 49.0 ns;
end process;
end architecture behavior;

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#
# Copyright (C) 2017 Jared Boone, ShareBrained Technology, Inc.
#
# This file is part of PortaPack.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
# Makefile based on Altera Quartus documentation example, topic
# "About Using Quartus II from the Command Line"
###################################################################
# Project Configuration:
#
# Specify the name of the design (project) and Quartus II Settings
# File (.qsf) and the list of source files used.
###################################################################
PROJECT=portapack_h1_cpld
SOURCE_FILES=top.vhd
ASSIGNMENT_FILES=$(PROJECT).qpf $(PROJECT).qsf $(PROJECT).sdc
OUTPUT_DIR=output_files
###################################################################
# Main Targets
#
# all: build everything
# clean: remove output files and database
###################################################################
all: smart.log $(OUTPUT_DIR)/$(PROJECT).asm.rpt $(OUTPUT_DIR)/$(PROJECT).sta.rpt
clean:
rm -rf *.chg *.qws smart.log db/ incremental_db/ $(OUTPUT_DIR)/
map: smart.log $(OUTPUT_DIR)/$(PROJECT).map.rpt
fit: smart.log $(OUTPUT_DIR)/$(PROJECT).fit.rpt
asm: smart.log $(OUTPUT_DIR)/$(PROJECT).asm.rpt
sta: smart.log $(OUTPUT_DIR)/$(PROJECT).sta.rpt
smart: smart.log
###################################################################
# Executable Configuration
###################################################################
MAP_ARGS=
FIT_ARGS=
ASM_ARGS=
STA_ARGS=
###################################################################
# Target implementations
###################################################################
STAMP = echo done >
$(OUTPUT_DIR)/$(PROJECT).map.rpt: $(SOURCE_FILES)
quartus_map $(MAP_ARGS) $(PROJECT)
$(STAMP) fit.chg
$(OUTPUT_DIR)/$(PROJECT).fit.rpt: fit.chg $(OUTPUT_DIR)/$(PROJECT).map.rpt
quartus_fit $(FIT_ARGS) $(PROJECT)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(OUTPUT_DIR)/$(PROJECT).asm.rpt: asm.chg $(OUTPUT_DIR)/$(PROJECT).fit.rpt
quartus_asm $(ASM_ARGS) $(PROJECT)
$(OUTPUT_DIR)/$(PROJECT).sta.rpt: sta.chg $(OUTPUT_DIR)/$(PROJECT).fit.rpt
quartus_sta $(STA_ARGS) $(PROJECT)
smart.log: $(ASSIGNMENT_FILES) $(OUTPUT_DIR)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
###################################################################
# Project initialization
###################################################################
$(OUTPUT_DIR):
mkdir $(OUTPUT_DIR)
$(ASSIGNMENT_FILES): $(OUTPUT_DIR)
quartus_sh --prepare $(PROJECT)
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg

11651
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Software/portapack-mayhem/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:24:55 April 29, 2014
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "21:24:55 April 29, 2014"
# Revisions
PROJECT_REVISION = "portapack_h1_cpld"

347
Software/portapack-mayhem/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:24:55 April 29, 2014
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# portapack_h1_cpld_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX V"
set_global_assignment -name DEVICE 5M40ZE64C5
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:24:55 APRIL 29, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 64
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SDC_FILE portapack_h1_cpld.sdc
set_global_assignment -name VHDL_FILE top.vhd
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
set_location_assignment PIN_43 -to LCD_DB[15]
set_location_assignment PIN_44 -to LCD_DB[14]
set_location_assignment PIN_45 -to LCD_DB[13]
set_location_assignment PIN_46 -to LCD_DB[12]
set_location_assignment PIN_47 -to LCD_DB[11]
set_location_assignment PIN_48 -to LCD_DB[10]
set_location_assignment PIN_49 -to LCD_DB[9]
set_location_assignment PIN_50 -to LCD_DB[8]
set_location_assignment PIN_51 -to LCD_DB[7]
set_location_assignment PIN_52 -to LCD_DB[6]
set_location_assignment PIN_53 -to LCD_DB[5]
set_location_assignment PIN_54 -to LCD_DB[4]
set_location_assignment PIN_55 -to LCD_DB[3]
set_location_assignment PIN_56 -to LCD_DB[2]
set_location_assignment PIN_58 -to LCD_DB[1]
set_location_assignment PIN_59 -to LCD_DB[0]
set_location_assignment PIN_60 -to LCD_RDX
set_location_assignment PIN_62 -to LCD_RS
set_location_assignment PIN_63 -to LCD_TE
set_location_assignment PIN_61 -to LCD_WRX
set_location_assignment PIN_10 -to SW_D
set_location_assignment PIN_28 -to SW_L
set_location_assignment PIN_9 -to SW_R
set_location_assignment PIN_11 -to SW_ROT_A
set_location_assignment PIN_12 -to SW_ROT_B
set_location_assignment PIN_13 -to SW_SEL
set_location_assignment PIN_25 -to SW_U
set_location_assignment PIN_1 -to TP_D
set_location_assignment PIN_2 -to TP_L
set_location_assignment PIN_64 -to TP_R
set_location_assignment PIN_3 -to TP_U
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_D
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_L
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_R
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_A
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_B
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_SEL
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_U
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_D
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_L
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_R
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_U
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[15]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[14]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[13]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[12]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[11]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[10]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[9]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[8]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[7]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[6]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[5]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RDX
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RS
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_TE
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_WRX
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH top_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME top_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME uut -section_id top_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME top_tb -section_id top_tb
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id top_tb
set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.vhd -section_id top_tb
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR /home/jboone/src/portapack/portapack_hackrf/hardware/portapack_h1/cpld -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name GENERATE_RBF_FILE OFF
set_global_assignment -name GENERATE_SVF_FILE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH BUS-HOLD"
set_location_assignment PIN_38 -to LCD_RESETX
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RESETX
set_location_assignment PIN_18 -to MCU_D[7]
set_location_assignment PIN_19 -to MCU_D[6]
set_location_assignment PIN_21 -to MCU_D[5]
set_location_assignment PIN_20 -to MCU_D[4]
set_location_assignment PIN_22 -to MCU_D[3]
set_location_assignment PIN_24 -to MCU_D[2]
set_location_assignment PIN_27 -to MCU_D[1]
set_location_assignment PIN_26 -to MCU_D[0]
set_location_assignment PIN_33 -to MCU_ADDR
set_location_assignment PIN_42 -to MCU_DIR
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_ADDR
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_DIR
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_D
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_L
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_R
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_U
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_B
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_SEL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_A
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RDX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RESETX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_TE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_WRX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_ADDR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_L
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_R
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_A
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_B
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_SEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_U
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_L
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_R
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_U
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[15]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[14]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[13]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[12]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[11]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[10]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[9]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[8]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[7]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[6]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[5]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[4]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[3]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[2]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[1]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[0]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RDX
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RESETX
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RS
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_TE
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_WRX
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_ADDR
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[7]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[6]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[5]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[4]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[3]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[2]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[1]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[0]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_DIR
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_D
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_L
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_R
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_A
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_B
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_SEL
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_U
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_D
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_L
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_R
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_U
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
set_global_assignment -name IOBANK_VCCIO 1.8V -section_id 2
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
set_instance_assignment -name PCI_IO OFF -to MCU_DIR
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER ON
set_location_assignment PIN_37 -to LCD_BACKLIGHT
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_BACKLIGHT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_BACKLIGHT
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_BACKLIGHT
set_location_assignment PIN_4 -to AUDIO_RESETX
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_RESETX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AUDIO_RESETX
set_instance_assignment -name SLOW_SLEW_RATE ON -to AUDIO_RESETX
set_location_assignment PIN_30 -to MCU_LCD_RDX
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_RDX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_RDX
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_RDX
set_location_assignment PIN_40 -to MCU_LCD_WRX
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_WRX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_WRX
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_WRX
set_instance_assignment -name PCI_IO OFF -to MCU_LCD_WRX
set_location_assignment PIN_32 -to MCU_IO_STBX
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_IO_STBX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_IO_STBX
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_IO_STBX
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_R
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_D
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_L
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_U
set_location_assignment PIN_31 -to MCU_LCD_TE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_TE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_TE
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_TE
set_location_assignment PIN_34 -to MCU_P2_8
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_P2_8
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_P2_8
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_P2_8
set_instance_assignment -name PCI_IO OFF -to MCU_P2_8
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[15]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[14]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[13]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[12]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[11]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[10]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[9]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[8]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to LCD_DB[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_D[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_ADDR
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_DIR
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_IO_STBX
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_LCD_RDX
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_LCD_WRX
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MCU_P2_8
set_location_assignment PIN_35 -to GPS_TIMEPULSE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_TIMEPULSE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_TIMEPULSE
set_instance_assignment -name SLOW_SLEW_RATE ON -to GPS_TIMEPULSE
set_instance_assignment -name PCI_IO OFF -to GPS_TIMEPULSE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPS_TIMEPULSE
set_location_assignment PIN_36 -to GPS_TX_READY
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_TX_READY
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_TX_READY
set_instance_assignment -name SLOW_SLEW_RATE ON -to GPS_TX_READY
set_instance_assignment -name PCI_IO OFF -to GPS_TX_READY
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPS_TX_READY
set_location_assignment PIN_5 -to REF_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to REF_EN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to REF_EN
set_instance_assignment -name SLOW_SLEW_RATE ON -to REF_EN
set_location_assignment PIN_7 -to GPS_RESETX
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPS_RESETX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to GPS_RESETX
set_instance_assignment -name SLOW_SLEW_RATE ON -to GPS_RESETX

116
Software/portapack-mayhem/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.sdc Normal file
View File

@@ -0,0 +1,116 @@
## Generated SDC file "portapack_hackrf_one_cpld.sdc"
## Copyright (C) 1991-2014 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
## DATE "Sat May 3 10:22:18 2014"
##
## DEVICE "5M40ZE64C5"
##
# RS = 0, D = DB[15:8]
# wait max(tast = 0 ns, CPLD setup = ?)
# WR = 0, D = DB[7:0]
# wait max(CPLD )
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
set mcu_clk_period 4.9
set lcd_data_wr_setup 10.0
set lcd_data_wr_hold 10.0
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {MCU_LCD_WRX} -period 66.000 -waveform { 0.000 33.000 } [get_ports {MCU_LCD_WRX}]
#create_clock -name strobe_virt -period 66.000
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
#set_input_delay -clock strobe_virt [get_ports {D[*]}]
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#set_false_path -from [get_clocks {MCU_IO_STBX}] -to [get_ports {TP_D TP_L TP_R TP_U}]
#set_false_path -from [get_ports {SW_D SW_L SW_R SW_ROT_A SW_ROT_B SW_SEL SW_U}] -to [get_ports {MCU_D[*]}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

187
Software/portapack-mayhem/hardware/portapack_h1/cpld/20170522/top.vhd Normal file
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@@ -0,0 +1,187 @@
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WRX : in std_logic;
MCU_ADDR : in std_logic;
MCU_LCD_TE : out std_logic;
MCU_P2_8 : in std_logic;
MCU_LCD_RDX : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic;
AUDIO_RESETX : out std_logic;
REF_EN : out std_logic;
GPS_RESETX : out std_logic;
GPS_TX_READY : in std_logic;
GPS_TIMEPULSE : in std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal audio_reset_q : std_logic := '1';
signal ref_en_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_LCD_TE <= LCD_TE;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
lcd_read_strobe <= (MCU_LCD_RDX = '0');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= MCU_LCD_RDX;
LCD_WRX <= MCU_LCD_WRX;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
-- Reference clock
REF_EN <= ref_en_q;
-- Peripheral reset control
LCD_RESETX <= not lcd_reset_q;
AUDIO_RESETX <= not audio_reset_q;
GPS_RESETX <= '1';
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WRX, mcu_data_in)
begin
if falling_edge(MCU_LCD_WRX) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RDX, lcd_data_in)
begin
if rising_edge(MCU_LCD_RDX) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
audio_reset_q <= mcu_data_in(1);
ref_en_q <= mcu_data_in(6);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;

30
Software/portapack-mayhem/hardware/portapack_h1/fp-lib-table Normal file
View File

@@ -0,0 +1,30 @@
(fp_lib_table
(lib (name alps)(type KiCad)(uri ${KISBLIB}/alps.pretty)(options "")(descr ""))
(lib (name bat_coin)(type KiCad)(uri ${KISBLIB}/bat_coin.pretty)(options "")(descr ""))
(lib (name ck)(type KiCad)(uri ${KISBLIB}/ck.pretty)(options "")(descr ""))
(lib (name cui)(type KiCad)(uri ${KISBLIB}/cui.pretty)(options "")(descr ""))
(lib (name eastrising)(type KiCad)(uri ${KISBLIB}/eastrising.pretty)(options "")(descr ""))
(lib (name fiducial)(type KiCad)(uri ${KISBLIB}/fiducial.pretty)(options "")(descr ""))
(lib (name header)(type KiCad)(uri ${KISBLIB}/header.pretty)(options "")(descr ""))
(lib (name hole)(type KiCad)(uri ${KISBLIB}/hole.pretty)(options "")(descr ""))
(lib (name ipc_capae)(type KiCad)(uri ${KISBLIB}/ipc_capae.pretty)(options "")(descr ""))
(lib (name ipc_capc)(type KiCad)(uri ${KISBLIB}/ipc_capc.pretty)(options "")(descr ""))
(lib (name ipc_indc)(type KiCad)(uri ${KISBLIB}/ipc_indc.pretty)(options "")(descr ""))
(lib (name ipc_qfn)(type KiCad)(uri ${KISBLIB}/ipc_qfn.pretty)(options "")(descr ""))
(lib (name ipc_qfp)(type KiCad)(uri ${KISBLIB}/ipc_qfp.pretty)(options "")(descr ""))
(lib (name ipc_resc)(type KiCad)(uri ${KISBLIB}/ipc_resc.pretty)(options "")(descr ""))
(lib (name ipc_son)(type KiCad)(uri ${KISBLIB}/ipc_son.pretty)(options "")(descr ""))
(lib (name ipc_sop)(type KiCad)(uri ${KISBLIB}/ipc_sop.pretty)(options "")(descr ""))
(lib (name ipc_sot)(type KiCad)(uri ${KISBLIB}/ipc_sot.pretty)(options "")(descr ""))
(lib (name jst)(type KiCad)(uri ${KISBLIB}/jst.pretty)(options "")(descr ""))
(lib (name molex)(type KiCad)(uri ${KISBLIB}/molex.pretty)(options "")(descr ""))
(lib (name on_semi)(type KiCad)(uri ${KISBLIB}/on_semi.pretty)(options "")(descr ""))
(lib (name tp)(type KiCad)(uri ${KISBLIB}/tp.pretty)(options "")(descr ""))
(lib (name ipc_ledc)(type KiCad)(uri ${KISBLIB}/ipc_ledc.pretty)(options "")(descr ""))
(lib (name sharebrained)(type KiCad)(uri ${KISBLIB}/sharebrained.pretty)(options "")(descr ""))
(lib (name ipc_rescax)(type KiCad)(uri ${KISBLIB}/ipc_rescax.pretty)(options "")(descr ""))
(lib (name ipc_osccc)(type KiCad)(uri ${KISBLIB}/ipc_osccc.pretty)(options "")(descr ""))
(lib (name ipc_beadc)(type KiCad)(uri ${KISBLIB}/ipc_beadc.pretty)(options "")(descr ""))
(lib (name ublox)(type KiCad)(uri ${KISBLIB}/ublox.pretty)(options "")(descr ""))
(lib (name amp_te)(type KiCad)(uri ${KISBLIB}/amp_te.pretty)(options "")(descr ""))
)

370
Software/portapack-mayhem/hardware/portapack_h1/gps.sch Normal file
View File

@@ -0,0 +1,370 @@
EESchema Schematic File Version 4
LIBS:portapack_h1-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 6 6
Title "PortaPack H1"
Date "2018-10-29"
Rev "20181029"
Comp "ShareBrained Technology, Inc."
Comment1 "Copyright © 2014-2018 Jared Boone"
Comment2 "License: GNU General Public License, version 2"
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L ublox:MAX-M8 U8
U 1 1 5B7E0C1A
P 5800 2900
F 0 "U8" H 5800 3650 60 0000 C CNN
F 1 "MAX-M8" H 5800 3550 60 0000 C CNN
F 2 "ublox:MAX-M8" H 5800 2900 60 0001 C CNN
F 3 "" H 5800 2900 60 0001 C CNN
F 4 "DNP" H 5800 3450 50 0000 C CNN "DNP"
1 5800 2900
1 0 0 -1
$EndComp
$Comp
L Device:C C19
U 1 1 5B7E0D14
P 4600 3450
F 0 "C19" V 4250 3450 50 0000 C CNN
F 1 "10N" V 4350 3450 50 0000 C CNN
F 2 "ipc_capc:IPC_CAPC100X50X55L25N" H 4638 3300 50 0001 C CNN
F 3 "~" H 4600 3450 50 0001 C CNN
F 4 "DNP" V 4450 3450 50 0000 C CNN "DNP"
1 4600 3450
1 0 0 -1
$EndComp
$Comp
L Device:L L1
U 1 1 5B7E0E02
P 4350 2900
F 0 "L1" H 4403 2946 50 0000 L CNN
F 1 "27N" H 4403 2855 50 0000 L CNN
F 2 "ipc_indc:IPC_INDC100X50X60L20N" H 4350 2900 50 0001 C CNN
F 3 "~" H 4350 2900 50 0001 C CNN
F 4 "DNP" H 4450 2750 50 0000 C CNN "DNP"
1 4350 2900
0 -1 -1 0
$EndComp
$Comp
L power:GND #PWR0108
U 1 1 5B7E0F42
P 4600 3700
F 0 "#PWR0108" H 4600 3450 50 0001 C CNN
F 1 "GND" H 4605 3527 50 0000 C CNN
F 2 "" H 4600 3700 50 0001 C CNN
F 3 "" H 4600 3700 50 0001 C CNN
1 4600 3700
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0109
U 1 1 5B7E0F5A
P 5100 3400
F 0 "#PWR0109" H 5100 3150 50 0001 C CNN
F 1 "GND" H 5105 3227 50 0000 C CNN
F 2 "" H 5100 3400 50 0001 C CNN
F 3 "" H 5100 3400 50 0001 C CNN
1 5100 3400
1 0 0 -1
$EndComp
Wire Wire Line
5200 2500 5100 2500
Wire Wire Line
5100 2500 5100 2700
Wire Wire Line
5200 2700 5100 2700
Connection ~ 5100 2700
Wire Wire Line
5100 2700 5100 3000
Wire Wire Line
5200 2600 4100 2600
Text HLabel 3200 3100 0 60 BiDi ~ 0
SDA
Text HLabel 3200 3500 0 60 BiDi ~ 0
SCL
$Comp
L power:GND #PWR0110
U 1 1 5B7E1247
P 6500 3400
F 0 "#PWR0110" H 6500 3150 50 0001 C CNN
F 1 "GND" H 6505 3227 50 0000 C CNN
F 2 "" H 6500 3400 50 0001 C CNN
F 3 "" H 6500 3400 50 0001 C CNN
1 6500 3400
1 0 0 -1
$EndComp
Wire Wire Line
6400 3300 6500 3300
Wire Wire Line
6500 3300 6500 3400
Text HLabel 7800 1800 2 60 Input ~ 0
V_BACKUP
Text HLabel 6650 1800 0 60 Input ~ 0
VCC
Wire Wire Line
6400 2600 6800 2600
Wire Wire Line
6400 2700 6800 2700
$Comp
L tp:TP TP7
U 1 1 5B7E1777
P 4900 3300
F 0 "TP7" H 4750 3300 50 0000 C CNN
F 1 "TP" H 4900 3300 50 0001 C CNN
F 2 "tp:TP_1MM" H 4900 3300 60 0001 C CNN
F 3 "" H 4900 3300 60 0001 C CNN
1 4900 3300
1 0 0 -1
$EndComp
Wire Wire Line
5000 3300 5200 3300
Text HLabel 6900 3000 2 60 Output ~ 0
TIMEPULSE
Wire Wire Line
6400 3000 6900 3000
$Comp
L tp:TP TP8
U 1 1 5B7E20D6
P 7000 2900
F 0 "TP8" H 6850 2900 50 0000 C CNN
F 1 "TP" H 7000 2900 50 0001 C CNN
F 2 "tp:TP_1MM" H 7000 2900 60 0001 C CNN
F 3 "" H 7000 2900 60 0001 C CNN
1 7000 2900
-1 0 0 1
$EndComp
Wire Wire Line
6400 2900 6900 2900
$Comp
L tp:TP TP9
U 1 1 5B7E27BE
P 7000 3100
F 0 "TP9" H 6850 3100 50 0000 C CNN
F 1 "TP" H 7000 3100 50 0001 C CNN
F 2 "tp:TP_1MM" H 7000 3100 60 0001 C CNN
F 3 "" H 7000 3100 60 0001 C CNN
1 7000 3100
-1 0 0 1
$EndComp
Wire Wire Line
6400 3100 6900 3100
Text HLabel 7800 2500 2 60 Input ~ 0
RESET#
Wire Wire Line
6400 2500 7700 2500
$Comp
L Device:C C20
U 1 1 5B7E512B
P 6800 3450
F 0 "C20" H 6915 3496 50 0000 L CNN
F 1 "100N" H 6915 3405 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC100X50X55L25N" H 6838 3300 50 0001 C CNN
F 3 "~" H 6800 3450 50 0001 C CNN
F 4 "DNP" H 7000 3300 50 0000 C CNN "DNP"
1 6800 3450
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0111
U 1 1 5B7E5197
P 6800 3700
F 0 "#PWR0111" H 6800 3450 50 0001 C CNN
F 1 "GND" H 6805 3527 50 0000 C CNN
F 2 "" H 6800 3700 50 0001 C CNN
F 3 "" H 6800 3700 50 0001 C CNN
1 6800 3700
1 0 0 -1
$EndComp
Wire Wire Line
6800 3600 6800 3700
Wire Wire Line
6800 2700 6800 2600
$Comp
L Device:R R25
U 1 1 5B7E62C8
P 7700 2750
F 0 "R25" H 7770 2796 50 0000 L CNN
F 1 "100K" V 7700 2650 50 0000 L CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 7630 2750 50 0001 C CNN
F 3 "~" H 7700 2750 50 0001 C CNN
F 4 "DNP" H 7850 2700 50 0000 C CNN "DNP"
1 7700 2750
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0112
U 1 1 5B7E633A
P 7700 3000
F 0 "#PWR0112" H 7700 2750 50 0001 C CNN
F 1 "GND" H 7705 2827 50 0000 C CNN
F 2 "" H 7700 3000 50 0001 C CNN
F 3 "" H 7700 3000 50 0001 C CNN
1 7700 3000
1 0 0 -1
$EndComp
Wire Wire Line
7700 2600 7700 2500
Connection ~ 7700 2500
Wire Wire Line
7700 2500 7800 2500
Wire Wire Line
7700 2900 7700 3000
$Comp
L passive:FBEAD FB1
U 1 1 5B7E9718
P 3550 3100
F 0 "FB1" H 3550 3300 50 0000 C CNN
F 1 "FBEAD" H 3544 3227 50 0001 C CNN
F 2 "ipc_beadc:IPC_BEADC160X80X95L40N" H 3544 3234 60 0001 C CNN
F 3 "" H 3550 3100 60 0000 C CNN
F 4 "DNP" H 3550 3200 50 0000 C CNN "DNP"
F 5 "Murata" H 0 0 50 0001 C CNN "Mfr"
F 6 "BLM18HE152SN1D" H 0 0 50 0001 C CNN "Part"
1 3550 3100
1 0 0 -1
$EndComp
$Comp
L passive:FBEAD FB3
U 1 1 5B7E9798
P 3550 3500
F 0 "FB3" H 3550 3700 50 0000 C CNN
F 1 "FBEAD" H 3544 3627 50 0001 C CNN
F 2 "ipc_beadc:IPC_BEADC160X80X95L40N" H 3550 3500 60 0001 C CNN
F 3 "" H 3550 3500 60 0000 C CNN
F 4 "DNP" H 3550 3600 50 0000 C CNN "DNP"
F 5 "Murata" H 0 0 50 0001 C CNN "Mfr"
F 6 "BLM18HE152SN1D" H 0 0 50 0001 C CNN "Part"
1 3550 3500
1 0 0 -1
$EndComp
Wire Wire Line
3200 3100 3300 3100
Wire Wire Line
3200 3500 3300 3500
Wire Wire Line
3800 3500 3900 3500
Wire Wire Line
3900 3500 3900 3200
Wire Wire Line
3900 3200 5200 3200
$Comp
L Device:R R24
U 1 1 5B7EC300
P 7550 1800
F 0 "R24" V 7450 1800 50 0000 C CNN
F 1 "0R" V 7550 1800 50 0000 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 7480 1800 50 0001 C CNN
F 3 "~" H 7550 1800 50 0001 C CNN
F 4 "DNP" V 7650 1800 50 0000 C CNN "DNP"
1 7550 1800
0 1 1 0
$EndComp
$Comp
L Device:R R23
U 1 1 5B7ED5AD
P 7050 1800
F 0 "R23" V 6950 1800 50 0000 C CNN
F 1 "0R" V 7050 1800 50 0000 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 6980 1800 50 0001 C CNN
F 3 "~" H 7050 1800 50 0001 C CNN
F 4 "DNP" V 7150 1800 50 0000 C CNN "DNP"
1 7050 1800
0 1 1 0
$EndComp
NoConn ~ 5200 2800
Wire Wire Line
5200 3000 5100 3000
Connection ~ 5100 3000
Wire Wire Line
5100 3000 5100 3400
Text HLabel 6900 3200 2 60 Output ~ 0
TX_READY
Wire Wire Line
6400 3200 6900 3200
$Comp
L conn_rf:CONN_COAX P1
U 1 1 5B78522B
P 2550 2600
F 0 "P1" H 2505 2844 60 0000 C CNN
F 1 "CONN_COAX" H 2505 2829 40 0001 C CNN
F 2 "amp_te:1909763-1" H 2505 2754 60 0001 C CNN
F 3 "" H 2550 2600 60 0000 C CNN
F 4 "DNP" H 2505 2746 50 0000 C CNN "DNP"
F 5 "AMP/TE" H 0 0 50 0001 C CNN "Mfr"
F 6 "1909763-1" H 0 0 50 0001 C CNN "Part"
1 2550 2600
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0113
U 1 1 5B7852CC
P 2550 2900
F 0 "#PWR0113" H 2550 2650 50 0001 C CNN
F 1 "GND" H 2555 2727 50 0000 C CNN
F 2 "" H 2550 2900 50 0001 C CNN
F 3 "" H 2550 2900 50 0001 C CNN
1 2550 2900
1 0 0 -1
$EndComp
Wire Wire Line
2550 2800 2550 2900
Wire Wire Line
3800 3100 5200 3100
$Comp
L Device:R R26
U 1 1 5B78A3E5
P 4850 2900
F 0 "R26" V 4750 2900 50 0000 C CNN
F 1 "10R" V 4850 2900 50 0000 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 4780 2900 50 0001 C CNN
F 3 "~" H 4850 2900 50 0001 C CNN
F 4 "DNP" V 4950 2900 50 0000 C CNN "DNP"
1 4850 2900
0 1 1 0
$EndComp
Wire Wire Line
5200 2900 5000 2900
Wire Wire Line
4700 2900 4600 2900
Wire Wire Line
4600 2900 4600 3300
Wire Wire Line
4600 3600 4600 3700
Wire Wire Line
4600 2900 4500 2900
Connection ~ 4600 2900
Wire Wire Line
4200 2900 4100 2900
Wire Wire Line
4100 2900 4100 2600
Connection ~ 4100 2600
Wire Wire Line
2700 2600 4100 2600
Wire Wire Line
7800 1800 7700 1800
Wire Wire Line
7400 1800 7300 1800
Wire Wire Line
6650 1800 6800 1800
Wire Wire Line
6800 2600 6800 1800
Connection ~ 6800 2600
Connection ~ 6800 1800
Wire Wire Line
6800 1800 6900 1800
Wire Wire Line
6400 2800 7300 2800
Wire Wire Line
7300 1800 7300 2800
Connection ~ 7300 1800
Wire Wire Line
7300 1800 7200 1800
Wire Wire Line
6800 2700 6800 3300
Connection ~ 6800 2700
$EndSCHEMATC

1186
Software/portapack-mayhem/hardware/portapack_h1/hackrf_if.sch Normal file
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File diff suppressed because it is too large Load Diff

791
Software/portapack-mayhem/hardware/portapack_h1/lcd_sw_sd.sch Normal file
View File

@@ -0,0 +1,791 @@
EESchema Schematic File Version 4
LIBS:portapack_h1-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 3 6
Title "PortaPack H1"
Date "2018-10-29"
Rev "20181029"
Comp "ShareBrained Technology, Inc."
Comment1 "Copyright © 2014-2018 Jared Boone"
Comment2 "License: GNU General Public License, version 2"
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L power:GND #PWR019
U 1 1 53A91608
P 9900 5100
F 0 "#PWR019" H 9900 5100 30 0001 C CNN
F 1 "GND" H 9900 5030 30 0001 C CNN
F 2 "" H 9900 5100 60 0000 C CNN
F 3 "" H 9900 5100 60 0000 C CNN
1 9900 5100
0 1 1 0
$EndComp
$Comp
L power:+3V3 #PWR020
U 1 1 53A91614
P 9800 5000
F 0 "#PWR020" H 9800 4960 30 0001 C CNN
F 1 "+3V3" H 9800 5110 30 0000 C CNN
F 2 "" H 9800 5000 60 0000 C CNN
F 3 "" H 9800 5000 60 0000 C CNN
1 9800 5000
0 -1 -1 0
$EndComp
$Comp
L power:GND #PWR021
U 1 1 53A91623
P 9900 6000
F 0 "#PWR021" H 9900 6000 30 0001 C CNN
F 1 "GND" H 9900 5930 30 0001 C CNN
F 2 "" H 9900 6000 60 0000 C CNN
F 3 "" H 9900 6000 60 0000 C CNN
1 9900 6000
0 1 1 0
$EndComp
Text Label 9300 3300 0 60 ~ 0
LCD_DB7
Text Label 9300 3400 0 60 ~ 0
LCD_DB6
Text Label 9300 3500 0 60 ~ 0
LCD_DB5
Text Label 9300 3600 0 60 ~ 0
LCD_DB4
Text Label 9300 3700 0 60 ~ 0
LCD_DB3
Text Label 9300 3800 0 60 ~ 0
LCD_DB2
Text Label 9300 3900 0 60 ~ 0
LCD_DB1
Text Label 9300 4000 0 60 ~ 0
LCD_DB0
Text Notes 7400 6200 0 60 ~ 0
LCD Mode:\n8080 MCU 16-bit bus interface I\nIM[3:0] = 0b0001, DB[15:0] active
Text Label 9300 3200 0 60 ~ 0
LCD_DB8
Text Label 9300 3100 0 60 ~ 0
LCD_DB9
Text Label 9300 3000 0 60 ~ 0
LCD_DB10
Text Label 9300 2900 0 60 ~ 0
LCD_DB11
Text Label 9300 2800 0 60 ~ 0
LCD_DB12
Text Label 9300 2700 0 60 ~ 0
LCD_DB13
Text Label 9300 2600 0 60 ~ 0
LCD_DB14
Text Label 9300 2500 0 60 ~ 0
LCD_DB15
$Comp
L Device:R R19
U 1 1 53A91657
P 8000 2150
F 0 "R19" V 8080 2150 50 0000 C CNN
F 1 "10K" V 8000 2150 50 0001 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 8000 2150 60 0001 C CNN
F 3 "" H 8000 2150 60 0000 C CNN
F 4 "DNP" V 8000 2150 60 0000 C CNN "DNP"
F 5 "Yageo" V 8000 2150 60 0001 C CNN "Mfr"
1 8000 2150
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR022
U 1 1 53A9165D
P 8000 2500
F 0 "#PWR022" H 8000 2500 30 0001 C CNN
F 1 "GND" H 8000 2430 30 0001 C CNN
F 2 "" H 8000 2500 60 0000 C CNN
F 3 "" H 8000 2500 60 0000 C CNN
1 8000 2500
1 0 0 -1
$EndComp
$Comp
L power:+1V8 #PWR023
U 1 1 53A91663
P 9800 4800
F 0 "#PWR023" H 9800 4940 20 0001 C CNN
F 1 "+1V8" H 9800 4910 30 0000 C CNN
F 2 "" H 9800 4800 60 0000 C CNN
F 3 "" H 9800 4800 60 0000 C CNN
1 9800 4800
0 -1 -1 0
$EndComp
$Comp
L sd:MICROSD_DETSW J2
U 1 1 53A8C6D0
P 3900 6300
F 0 "J2" H 3450 6950 60 0000 C CNN
F 1 "MICROSD_DETSW" H 4050 6950 60 0000 C CNN
F 2 "alps:ALPS_SCHA4B0419" H 3900 6300 60 0001 C CNN
F 3 "http://www.mouser.com/ds/2/15/alps_SCHA4B0419-780241.pdf" H 3900 6300 60 0001 C CNN
F 4 "ALPS" H 3900 6300 60 0001 C CNN "Mfr"
F 5 "SCHA4B0419" H 3900 6300 60 0001 C CNN "Part"
1 3900 6300
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR024
U 1 1 53A8C6D6
P 3100 6300
F 0 "#PWR024" H 3100 6300 30 0001 C CNN
F 1 "GND" H 3100 6230 30 0001 C CNN
F 2 "" H 3100 6300 60 0000 C CNN
F 3 "" H 3100 6300 60 0000 C CNN
1 3100 6300
0 1 1 0
$EndComp
$Comp
L power:GND #PWR025
U 1 1 53A8C6E2
P 3100 6700
F 0 "#PWR025" H 3100 6700 30 0001 C CNN
F 1 "GND" H 3100 6630 30 0001 C CNN
F 2 "" H 3100 6700 60 0000 C CNN
F 3 "" H 3100 6700 60 0000 C CNN
1 3100 6700
0 1 1 0
$EndComp
$Comp
L Device:C C27
U 1 1 53AA73CE
P 2800 7100
F 0 "C27" H 2850 7200 50 0000 L CNN
F 1 "100N" H 2850 7000 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC100X50X55L25N" H 2800 7100 60 0001 C CNN
F 3 "" H 2800 7100 60 0000 C CNN
F 4 "Murata" H 2800 7100 60 0001 C CNN "Mfr"
F 5 "GRM155R61A104KA01" H 2800 7100 60 0001 C CNN "Part"
1 2800 7100
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR026
U 1 1 53A8C6EF
P 2400 7400
F 0 "#PWR026" H 2400 7400 30 0001 C CNN
F 1 "GND" H 2400 7330 30 0001 C CNN
F 2 "" H 2400 7400 60 0000 C CNN
F 3 "" H 2400 7400 60 0000 C CNN
1 2400 7400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR027
U 1 1 53A8C6F5
P 4200 7200
F 0 "#PWR027" H 4200 7200 30 0001 C CNN
F 1 "GND" H 4200 7130 30 0001 C CNN
F 2 "" H 4200 7200 60 0000 C CNN
F 3 "" H 4200 7200 60 0000 C CNN
1 4200 7200
1 0 0 -1
$EndComp
$Comp
L ck:CK_TSWB-3N-CB SW1
U 1 1 53A8C6FD
P 2500 1450
F 0 "SW1" H 2500 2050 60 0000 C CNN
F 1 "CK_TSWB-3N-CB" H 2500 850 60 0000 C CNN
F 2 "ck:CK_TSWB-3N-CB222_LFS" H 2500 1450 60 0001 C CNN
F 3 "http://www.ckswitches.com/media/1346/tsw.pdf" H 2500 1450 60 0001 C CNN
F 4 "C&K" H 2500 1450 60 0001 C CNN "Mfr"
F 5 "TSWB-3N-CB222 LFS" H 2500 1450 60 0001 C CNN "Part"
1 2500 1450
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR028
U 1 1 53A8C70A
P 1400 2000
F 0 "#PWR028" H 1400 2000 30 0001 C CNN
F 1 "GND" H 1400 1930 30 0001 C CNN
F 2 "" H 1400 2000 60 0000 C CNN
F 3 "" H 1400 2000 60 0000 C CNN
1 1400 2000
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR029
U 1 1 53A8C710
P 3600 2000
F 0 "#PWR029" H 3600 2000 30 0001 C CNN
F 1 "GND" H 3600 1930 30 0001 C CNN
F 2 "" H 3600 2000 60 0000 C CNN
F 3 "" H 3600 2000 60 0000 C CNN
1 3600 2000
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR030
U 1 1 53A8C716
P 4000 7200
F 0 "#PWR030" H 4000 7200 30 0001 C CNN
F 1 "GND" H 4000 7130 30 0001 C CNN
F 2 "" H 4000 7200 60 0000 C CNN
F 3 "" H 4000 7200 60 0000 C CNN
1 4000 7200
1 0 0 -1
$EndComp
$Comp
L Device:C C26
U 1 1 53A8C71C
P 2400 7100
F 0 "C26" H 2450 7200 50 0000 L CNN
F 1 "10U" H 2450 7000 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC200X125X135L45N" H 2400 7100 60 0001 C CNN
F 3 "" H 2400 7100 60 0000 C CNN
F 4 "Murata" H 2400 7100 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 2400 7100 60 0001 C CNN "Part"
1 2400 7100
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR031
U 1 1 53A8C722
P 2800 7400
F 0 "#PWR031" H 2800 7400 30 0001 C CNN
F 1 "GND" H 2800 7330 30 0001 C CNN
F 2 "" H 2800 7400 60 0000 C CNN
F 3 "" H 2800 7400 60 0000 C CNN
1 2800 7400
1 0 0 -1
$EndComp
$Comp
L power:+3V3 #PWR032
U 1 1 53A8C728
P 2800 5700
F 0 "#PWR032" H 2800 5660 30 0001 C CNN
F 1 "+3V3" H 2800 5810 30 0000 C CNN
F 2 "" H 2800 5700 60 0000 C CNN
F 3 "" H 2800 5700 60 0000 C CNN
1 2800 5700
1 0 0 -1
$EndComp
Entry Wire Line
9100 2400 9200 2500
Entry Wire Line
9100 2500 9200 2600
Entry Wire Line
9100 2600 9200 2700
Entry Wire Line
9100 2700 9200 2800
Entry Wire Line
9100 2800 9200 2900
Entry Wire Line
9100 2900 9200 3000
Entry Wire Line
9100 3000 9200 3100
Entry Wire Line
9100 3100 9200 3200
Entry Wire Line
9100 3200 9200 3300
Entry Wire Line
9100 3300 9200 3400
Entry Wire Line
9100 3400 9200 3500
Entry Wire Line
9100 3500 9200 3600
Entry Wire Line
9100 3600 9200 3700
Entry Wire Line
9100 3700 9200 3800
Entry Wire Line
9100 3800 9200 3900
Entry Wire Line
9100 3900 9200 4000
Text HLabel 8950 2100 0 60 BiDi ~ 0
LCD_DB[15..0]
Text HLabel 9600 4500 0 60 Input ~ 0
LCD_RS
Text HLabel 9600 4300 0 60 Input ~ 0
LCD_RD#
Text HLabel 9600 4400 0 60 Input ~ 0
LCD_WR#
Text HLabel 7900 1800 0 60 Input ~ 0
LCD_RESET#
Text HLabel 1600 3000 0 60 Input ~ 0
LCD_BACKLIGHT
Text HLabel 9600 4700 0 60 Output ~ 0
LCD_TE
Text HLabel 9600 5200 0 60 BiDi ~ 0
TP_R
Text HLabel 9600 5300 0 60 BiDi ~ 0
TP_D
Text HLabel 9600 5400 0 60 BiDi ~ 0
TP_L
Text HLabel 9600 5500 0 60 BiDi ~ 0
TP_U
Text HLabel 1400 1000 0 60 Output ~ 0
SW_SEL
Text HLabel 1400 1100 0 60 Output ~ 0
SW_ROT_A
Text HLabel 1400 1200 0 60 Output ~ 0
SW_ROT_B
Text HLabel 3600 1000 2 60 Output ~ 0
SW_D
Text HLabel 3600 1100 2 60 Output ~ 0
SW_R
Text HLabel 3600 1200 2 60 Output ~ 0
SW_U
Text HLabel 3600 1300 2 60 Output ~ 0
SW_L
Text HLabel 2200 5800 0 60 BiDi ~ 0
SD_DAT2
Text HLabel 2200 5900 0 60 BiDi ~ 0
SD_DAT3
Text HLabel 2200 6000 0 60 BiDi ~ 0
SD_CMD
Text HLabel 2200 6200 0 60 Input ~ 0
SD_CLK
Text HLabel 2200 6400 0 60 BiDi ~ 0
SD_DAT0
Text HLabel 2200 6500 0 60 BiDi ~ 0
SD_DAT1
Text HLabel 2200 6800 0 60 Output ~ 0
SD_CD
$Comp
L eastrising:ER-TFT024-3_PANEL LCD1
U 1 1 58A60E03
P 8000 4600
F 0 "LCD1" H 8000 5650 60 0000 C CNN
F 1 "ER-TFT024-3_PANEL" H 8000 3650 60 0000 C CNN
F 2 "eastrising:ER-TFT024-3" H 8000 4600 60 0001 C CNN
F 3 "http://www.buydisplay.com/download/manual/ER-TFT024-3_Datasheet.pdf" H 8000 4600 60 0001 C CNN
F 4 "EastRising" H 8000 4600 60 0001 C CNN "Mfr"
F 5 "ER-TFT024-3" H 8000 4600 60 0001 C CNN "Part"
1 8000 4600
1 0 0 -1
$EndComp
$Comp
L eastrising:ER-TFT024-3_FPC J3
U 1 1 58AE3A81
P 10450 3350
F 0 "J3" H 10450 5950 60 0000 C CNN
F 1 "ER-TFT024-3_FPC" H 10450 550 60 0000 C CNN
F 2 "eastrising:ER-CON50HT-1" H 10350 3350 60 0001 C CNN
F 3 "http://www.buydisplay.com/download/connector/ER-CON50HT-1.pdf" H 10350 3350 60 0001 C CNN
F 4 "EastRising" H 10450 3350 60 0001 C CNN "Mfr"
F 5 "ER-CON50HT-1" H 10450 3350 60 0001 C CNN "Part"
1 10450 3350
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR033
U 1 1 58AE4008
P 9900 5800
F 0 "#PWR033" H 9900 5800 30 0001 C CNN
F 1 "GND" H 9900 5730 30 0001 C CNN
F 2 "" H 9900 5800 60 0000 C CNN
F 3 "" H 9900 5800 60 0000 C CNN
1 9900 5800
0 1 1 0
$EndComp
$Comp
L power:GND #PWR034
U 1 1 58AE4031
P 9900 5700
F 0 "#PWR034" H 9900 5700 30 0001 C CNN
F 1 "GND" H 9900 5630 30 0001 C CNN
F 2 "" H 9900 5700 60 0000 C CNN
F 3 "" H 9900 5700 60 0000 C CNN
1 9900 5700
0 1 1 0
$EndComp
$Comp
L power:GND #PWR035
U 1 1 58AE405A
P 9900 5600
F 0 "#PWR035" H 9900 5600 30 0001 C CNN
F 1 "GND" H 9900 5530 30 0001 C CNN
F 2 "" H 9900 5600 60 0000 C CNN
F 3 "" H 9900 5600 60 0000 C CNN
1 9900 5600
0 1 1 0
$EndComp
$Comp
L power:GND #PWR036
U 1 1 58AE9874
P 9800 1900
F 0 "#PWR036" H 9800 1900 30 0001 C CNN
F 1 "GND" H 9800 1830 30 0001 C CNN
F 2 "" H 9800 1900 60 0000 C CNN
F 3 "" H 9800 1900 60 0000 C CNN
1 9800 1900
0 1 1 0
$EndComp
$Comp
L power:GND #PWR037
U 1 1 58AE9CF2
P 9800 1600
F 0 "#PWR037" H 9800 1600 30 0001 C CNN
F 1 "GND" H 9800 1530 30 0001 C CNN
F 2 "" H 9800 1600 60 0000 C CNN
F 3 "" H 9800 1600 60 0000 C CNN
1 9800 1600
0 1 1 0
$EndComp
Text HLabel 9600 4600 0 60 Input ~ 0
LCD_CS#
$Comp
L power:GND #PWR038
U 1 1 58B079A0
P 9900 4200
F 0 "#PWR038" H 9900 4200 30 0001 C CNN
F 1 "GND" H 9900 4130 30 0001 C CNN
F 2 "" H 9900 4200 60 0000 C CNN
F 3 "" H 9900 4200 60 0000 C CNN
1 9900 4200
0 1 1 0
$EndComp
NoConn ~ 10000 4100
$Comp
L on_semi:CAT4004[_AB] U4
U 1 1 58B747DD
P 2400 3150
F 0 "U4" H 2000 3450 60 0000 L CNN
F 1 "CAT4004[_AB]" H 2500 2850 60 0000 L CNN
F 2 "ipc_son:IPC_SON9P50_200X200X55L32X24T90X160N" H 2400 3150 60 0001 C CNN
F 3 "http://www.onsemi.com/pub/Collateral/CAT4003B-D.PDF" H 2400 3150 60 0001 C CNN
F 4 "ON Semiconductor" H 2400 3150 60 0001 C CNN "Mfr"
F 5 "CAT4004BHU2−GT3" H 2400 3150 60 0001 C CNN "Part"
1 2400 3150
1 0 0 -1
$EndComp
Text Label 9650 1000 0 60 ~ 0
LEDK1
Text Label 9650 1100 0 60 ~ 0
LEDK2
Text Label 9650 1200 0 60 ~ 0
LEDK3
Text Label 9650 1300 0 60 ~ 0
LEDK4
Text Label 3100 3200 0 60 ~ 0
LEDK4
Text Label 3100 3300 0 60 ~ 0
LEDK3
Text Label 1300 3300 0 60 ~ 0
LEDK2
Text Label 1300 3200 0 60 ~ 0
LEDK1
$Comp
L power:GND #PWR039
U 1 1 58B750FD
P 2400 3700
F 0 "#PWR039" H 2400 3700 30 0001 C CNN
F 1 "GND" H 2400 3630 30 0001 C CNN
F 2 "" H 2400 3700 60 0000 C CNN
F 3 "" H 2400 3700 60 0000 C CNN
1 2400 3700
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR040
U 1 1 58B75120
P 1700 3100
F 0 "#PWR040" H 1700 3100 30 0001 C CNN
F 1 "GND" H 1700 3030 30 0001 C CNN
F 2 "" H 1700 3100 60 0000 C CNN
F 3 "" H 1700 3100 60 0000 C CNN
1 1700 3100
0 1 1 0
$EndComp
$Comp
L Device:R R20
U 1 1 58B751E2
P 3700 3350
F 0 "R20" V 3780 3350 50 0000 C CNN
F 1 "3K9" V 3700 3350 50 0001 C CNN
F 2 "ipc_resc:IPC_RESC100X50X40L25N" H 3700 3350 60 0001 C CNN
F 3 "" H 3700 3350 60 0000 C CNN
F 4 "DNP" V 3700 3350 60 0000 C CNN "DNP"
F 5 "Yageo" V 3700 3350 60 0001 C CNN "Mfr"
1 3700 3350
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR041
U 1 1 58B75265
P 3700 3700
F 0 "#PWR041" H 3700 3700 30 0001 C CNN
F 1 "GND" H 3700 3630 30 0001 C CNN
F 2 "" H 3700 3700 60 0000 C CNN
F 3 "" H 3700 3700 60 0000 C CNN
1 3700 3700
1 0 0 -1
$EndComp
Wire Wire Line
2400 3600 2400 3700
Wire Wire Line
3000 3100 3700 3100
Wire Wire Line
1700 3100 1800 3100
Wire Wire Line
3000 3000 4000 3000
Wire Wire Line
3500 3300 3000 3300
Wire Wire Line
3500 3200 3000 3200
Wire Wire Line
1200 3300 1800 3300
Wire Wire Line
1200 3200 1800 3200
Wire Wire Line
1600 3000 1800 3000
Wire Wire Line
9550 1300 10000 1300
Wire Wire Line
9550 1200 10000 1200
Wire Wire Line
9550 1100 10000 1100
Wire Wire Line
9550 1000 10000 1000
Wire Wire Line
9900 4200 10000 4200
Wire Wire Line
9600 4600 10000 4600
Connection ~ 9900 1600
Wire Wire Line
9900 1500 9900 1600
Wire Wire Line
9800 1600 9900 1600
Connection ~ 9900 1900
Connection ~ 9900 2300
Wire Wire Line
9900 2400 10000 2400
Connection ~ 9900 2200
Wire Wire Line
9900 2300 10000 2300
Connection ~ 9900 2100
Wire Wire Line
9900 2200 10000 2200
Connection ~ 9900 2000
Wire Wire Line
9900 2100 10000 2100
Wire Wire Line
9900 2000 10000 2000
Wire Wire Line
9900 1900 9900 2000
Wire Wire Line
9800 1900 9900 1900
Wire Wire Line
9900 1700 10000 1700
Wire Wire Line
10000 5800 9900 5800
Wire Wire Line
10000 5700 9900 5700
Wire Wire Line
10000 5600 9900 5600
Connection ~ 9900 4800
Wire Wire Line
9900 4900 9900 4800
Wire Wire Line
10000 4900 9900 4900
Wire Wire Line
9550 900 10000 900
Wire Wire Line
3200 6700 3100 6700
Wire Wire Line
3200 6800 2200 6800
Wire Bus Line
8950 2100 9100 2100
Wire Wire Line
4000 7100 4000 7200
Wire Wire Line
1400 1900 1400 2000
Wire Wire Line
1500 1900 1400 1900
Wire Wire Line
3600 1900 3600 2000
Wire Wire Line
3500 1900 3600 1900
Wire Wire Line
3600 1300 3500 1300
Wire Wire Line
3600 1200 3500 1200
Wire Wire Line
3600 1100 3500 1100
Wire Wire Line
3500 1000 3600 1000
Wire Wire Line
1400 1200 1500 1200
Wire Wire Line
1400 1100 1500 1100
Wire Wire Line
1400 1000 1500 1000
Wire Wire Line
4200 7100 4200 7200
Wire Wire Line
2400 6100 2800 6100
Wire Wire Line
3200 6300 3100 6300
Wire Wire Line
2200 6500 3200 6500
Wire Wire Line
2200 6400 3200 6400
Wire Wire Line
2200 6200 3200 6200
Wire Wire Line
2200 6000 3200 6000
Wire Wire Line
2200 5900 3200 5900
Wire Wire Line
2200 5800 3200 5800
Wire Wire Line
2800 5700 2800 6100
Connection ~ 2800 6100
Connection ~ 8000 1800
Wire Wire Line
9200 2500 10000 2500
Wire Wire Line
9200 2600 10000 2600
Wire Wire Line
9200 2700 10000 2700
Wire Wire Line
9200 2800 10000 2800
Wire Wire Line
9200 2900 10000 2900
Wire Wire Line
9200 3000 10000 3000
Wire Wire Line
9200 3100 10000 3100
Wire Wire Line
9200 3200 10000 3200
Wire Wire Line
9600 4400 10000 4400
Wire Wire Line
9600 4300 10000 4300
Wire Wire Line
7900 1800 8000 1800
Wire Wire Line
9600 4500 10000 4500
Wire Wire Line
9200 3300 10000 3300
Wire Wire Line
9200 3400 10000 3400
Wire Wire Line
9200 3500 10000 3500
Wire Wire Line
9200 3600 10000 3600
Wire Wire Line
9200 3700 10000 3700
Wire Wire Line
9200 3800 10000 3800
Wire Wire Line
9200 3900 10000 3900
Wire Wire Line
9200 4000 10000 4000
Wire Wire Line
9900 6000 10000 6000
Wire Wire Line
9600 5500 10000 5500
Wire Wire Line
9600 5400 10000 5400
Wire Wire Line
9600 5300 10000 5300
Wire Wire Line
10000 5200 9600 5200
Wire Wire Line
9600 4700 10000 4700
Wire Wire Line
9800 5000 10000 5000
Wire Wire Line
9800 4800 9900 4800
Wire Wire Line
10000 5100 9900 5100
Wire Wire Line
10000 1400 9900 1400
Wire Wire Line
10000 1500 9900 1500
$Comp
L power:+1V8 #PWR042
U 1 1 58BA7696
P 9900 1400
F 0 "#PWR042" H 9900 1540 20 0001 C CNN
F 1 "+1V8" H 9900 1510 30 0000 C CNN
F 2 "" H 9900 1400 60 0000 C CNN
F 3 "" H 9900 1400 60 0000 C CNN
1 9900 1400
0 -1 -1 0
$EndComp
Text HLabel 9550 900 0 60 Input ~ 0
LCD_VBL
Text Notes 1200 2700 0 60 ~ 0
EN/DIM: 200k PD internal, enable > 1.3V, disable < 0.4V\nRSET: not required, default 25mA current\nUVLO: 2.0V typ
Text HLabel 4100 3000 2 60 Input ~ 0
LCD_VBL
$Comp
L Device:C C14
U 1 1 58D0DFA2
P 4000 3300
F 0 "C14" H 4050 3400 50 0000 L CNN
F 1 "1U" H 4050 3200 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC160X80X90L35N" H 4000 3300 60 0001 C CNN
F 3 "" H 4000 3300 60 0000 C CNN
F 4 "Murata" H 4000 3300 60 0001 C CNN "Mfr"
F 5 "GRM188R61C105KA93D" H 4000 3300 60 0001 C CNN "Part"
1 4000 3300
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR043
U 1 1 58D0E0F8
P 4000 3600
F 0 "#PWR043" H 4000 3600 30 0001 C CNN
F 1 "GND" H 4000 3530 30 0001 C CNN
F 2 "" H 4000 3600 60 0000 C CNN
F 3 "" H 4000 3600 60 0000 C CNN
1 4000 3600
1 0 0 -1
$EndComp
Connection ~ 4000 3000
Wire Wire Line
9900 1600 9900 1700
Wire Wire Line
9900 1600 10000 1600
Wire Wire Line
9900 1900 10000 1900
Wire Wire Line
9900 2300 9900 2400
Wire Wire Line
9900 2200 9900 2300
Wire Wire Line
9900 2100 9900 2200
Wire Wire Line
9900 2000 9900 2100
Wire Wire Line
9900 4800 10000 4800
Wire Wire Line
2800 6100 3200 6100
Wire Wire Line
8000 1800 10000 1800
Wire Wire Line
4000 3000 4100 3000
Wire Wire Line
3700 3100 3700 3200
Wire Wire Line
3700 3500 3700 3700
Wire Wire Line
4000 3450 4000 3600
Wire Wire Line
4000 3000 4000 3150
Wire Wire Line
2400 6100 2400 6950
Wire Wire Line
2400 7250 2400 7400
Wire Wire Line
2800 7250 2800 7400
Wire Wire Line
2800 6100 2800 6950
Wire Wire Line
8000 1800 8000 2000
Wire Wire Line
8000 2300 8000 2500
Wire Bus Line
9100 2100 9100 3900
$EndSCHEMATC

7329
Software/portapack-mayhem/hardware/portapack_h1/portapack_h1.kicad_pcb Normal file
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File diff suppressed because it is too large Load Diff

2318
Software/portapack-mayhem/hardware/portapack_h1/portapack_h1.net Normal file
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File diff suppressed because it is too large Load Diff

BIN
Software/portapack-mayhem/hardware/portapack_h1/portapack_h1.pdf Normal file
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Binary file not shown.

42
Software/portapack-mayhem/hardware/portapack_h1/portapack_h1.pro Normal file
View File

@@ -0,0 +1,42 @@
update=Wed 25 Jul 2018 01:46:26 PM PDT
version=1
last_client=kicad
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[general]
version=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=portapack_h1.net
PadDrill=0
PadDrillOvalY=0
PadSizeH=2.25
PadSizeV=2.25
PcbTextSizeV=1.5
PcbTextSizeH=1.5
PcbTextThickness=0.3
ModuleTextSizeV=0.6095999999999999
ModuleTextSizeH=0.6095999999999999
ModuleTextSizeThickness=0.12
SolderMaskClearance=0.07619999999999999
SolderMaskMinWidth=0.1016
DrawSegmentWidth=0.1524
BoardOutlineThickness=0.09999999999999999
ModuleOutlineThickness=0.1524
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[eeschema]
version=1
LibDir=

412
Software/portapack-mayhem/hardware/portapack_h1/portapack_h1.sch Normal file
View File

@@ -0,0 +1,412 @@
EESchema Schematic File Version 4
LIBS:portapack_h1-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 6
Title "PortaPack H1"
Date "2018-10-29"
Rev "20181029"
Comp "ShareBrained Technology, Inc."
Comment1 "Copyright © 2014-2018 Jared Boone"
Comment2 "License: GNU General Public License, version 2"
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L hole:HOLE1 H2
U 1 1 5369BBD8
P 9500 1900
F 0 "H2" H 9500 2050 60 0000 C CNN
F 1 "HOLE1" H 9500 1750 60 0000 C CNN
F 2 "hole:HOLE_3200UM_VIAS" H 9500 1900 60 0001 C CNN
F 3 "" H 9500 1900 60 0000 C CNN
1 9500 1900
1 0 0 -1
$EndComp
$Comp
L hole:HOLE1 H3
U 1 1 5369BBEC
P 9500 2400
F 0 "H3" H 9500 2550 60 0000 C CNN
F 1 "HOLE1" H 9500 2250 60 0000 C CNN
F 2 "hole:HOLE_3200UM_VIAS" H 9500 2400 60 0001 C CNN
F 3 "" H 9500 2400 60 0000 C CNN
1 9500 2400
1 0 0 -1
$EndComp
$Comp
L hole:HOLE1 H4
U 1 1 5369BC00
P 9500 2900
F 0 "H4" H 9500 3050 60 0000 C CNN
F 1 "HOLE1" H 9500 2750 60 0000 C CNN
F 2 "hole:HOLE_3200UM_VIAS" H 9500 2900 60 0001 C CNN
F 3 "" H 9500 2900 60 0000 C CNN
1 9500 2900
1 0 0 -1
$EndComp
$Comp
L hole:HOLE1 H5
U 1 1 5369BC14
P 9500 3400
F 0 "H5" H 9500 3550 60 0000 C CNN
F 1 "HOLE1" H 9500 3250 60 0000 C CNN
F 2 "hole:HOLE_3200UM_VIAS" H 9500 3400 60 0001 C CNN
F 3 "" H 9500 3400 60 0000 C CNN
1 9500 3400
1 0 0 -1
$EndComp
$Sheet
S 2800 1600 900 4700
U 53A8BFC3
F0 "audio" 50
F1 "audio.sch" 50
F2 "SCL" I R 3700 2500 60
F3 "SDA" B R 3700 2600 60
F4 "PDN#" I R 3700 1700 60
F5 "BICK" B R 3700 2000 60
F6 "LRCK" B R 3700 2100 60
F7 "SDTO" O R 3700 2300 60
F8 "MCKI" I R 3700 1900 60
F9 "SDTI" I R 3700 2200 60
F10 "SVDD" I R 3700 6200 60
F11 "AVDD" I R 3700 6100 60
F12 "DVDD" I R 3700 6000 60
F13 "TVDD" I R 3700 5900 60
$EndSheet
Wire Wire Line
9800 1900 9700 1900
Wire Wire Line
9800 2400 9700 2400
Wire Wire Line
9800 2900 9700 2900
$Sheet
S 7600 1600 900 4700
U 53A9129D
F0 "lcd_sw_sd" 50
F1 "lcd_sw_sd.sch" 50
F2 "LCD_RS" I L 7600 2100 60
F3 "LCD_RD#" I L 7600 2200 60
F4 "LCD_WR#" I L 7600 2300 60
F5 "LCD_RESET#" I L 7600 1700 60
F6 "LCD_TE" O L 7600 2700 60
F7 "SW_SEL" O L 7600 4000 60
F8 "SW_ROT_A" O L 7600 3800 60
F9 "SW_ROT_B" O L 7600 3900 60
F10 "SW_D" O L 7600 3600 60
F11 "SW_R" O L 7600 3500 60
F12 "SW_U" O L 7600 3400 60
F13 "SW_L" O L 7600 3700 60
F14 "SD_DAT2" B L 7600 4700 60
F15 "SD_DAT3" B L 7600 4800 60
F16 "SD_CMD" B L 7600 4400 60
F17 "SD_CLK" I L 7600 4300 60
F18 "SD_DAT0" B L 7600 4500 60
F19 "SD_DAT1" B L 7600 4600 60
F20 "SD_CD" O L 7600 4200 60
F21 "TP_R" B L 7600 3000 60
F22 "TP_D" B L 7600 3100 60
F23 "TP_L" B L 7600 3200 60
F24 "TP_U" B L 7600 2900 60
F25 "LCD_DB[15..0]" B L 7600 2400 60
F26 "LCD_BACKLIGHT" I L 7600 1900 60
F27 "LCD_CS#" I L 7600 2000 60
F28 "LCD_VBL" I L 7600 6200 60
$EndSheet
Wire Bus Line
6600 2400 7600 2400
$Sheet
S 4700 1600 1900 3700
U 53A8C780
F0 "hackrf_if" 50
F1 "hackrf_if.sch" 50
F2 "LCD_TE" I R 6600 2700 60
F3 "SW_R" I R 6600 3500 60
F4 "SW_ROT_B" I R 6600 3900 60
F5 "SW_ROT_A" I R 6600 3800 60
F6 "SW_D" I R 6600 3600 60
F7 "SW_SEL" I R 6600 4000 60
F8 "SW_U" I R 6600 3400 60
F9 "SW_L" I R 6600 3700 60
F10 "LCD_RESET#" O R 6600 1700 60
F11 "LCD_RS" O R 6600 2100 60
F12 "LCD_RD#" O R 6600 2200 60
F13 "LCD_WR#" O R 6600 2300 60
F14 "TP_U" B R 6600 2900 60
F15 "TP_L" B R 6600 3200 60
F16 "TP_D" B R 6600 3100 60
F17 "TP_R" B R 6600 3000 60
F18 "I2S0_TX_SDA" O L 4700 2200 60
F19 "I2S0_MCLK" O L 4700 1900 60
F20 "SDA" B L 4700 2600 60
F21 "SCL" O L 4700 2500 60
F22 "SD_CD" I R 6600 4200 60
F23 "SD_DAT2" B R 6600 4700 60
F24 "SD_DAT0" B R 6600 4500 60
F25 "SD_CMD" B R 6600 4400 60
F26 "SD_CLK" O R 6600 4300 60
F27 "SD_DAT3" B R 6600 4800 60
F28 "SD_DAT1" B R 6600 4600 60
F29 "I2S0_RX_SDA" I L 4700 2300 60
F30 "LCD_DB[15..0]" B R 6600 2400 60
F31 "LCD_BACKLIGHT" O R 6600 1900 60
F32 "LCD_CS#" O R 6600 2000 60
F33 "AUDIO_RESET#" O L 4700 1700 60
F34 "I2S0_WS" B L 4700 2100 60
F35 "I2S0_SCK" B L 4700 2000 60
F36 "VIN" I R 6600 5200 60
F37 "VBUS" O R 6600 5000 60
F38 "VBUSCTRL" I R 6600 5100 60
F39 "VBAT" I L 4700 5200 60
F40 "CLKIN" B L 4700 4900 60
F41 "REF_EN" O L 4700 5000 60
F42 "GPS_TX_READY" I L 4700 2800 60
F43 "GPS_TIMEPULSE" I L 4700 2900 60
F44 "GPS_RESET#" O L 4700 3000 60
$EndSheet
Wire Wire Line
6600 1900 7600 1900
Wire Wire Line
7600 1700 6600 1700
Wire Wire Line
7600 2100 6600 2100
Wire Wire Line
6600 2200 7600 2200
Wire Wire Line
7600 2300 6600 2300
Wire Wire Line
6600 2700 7600 2700
Wire Wire Line
7600 2900 6600 2900
Wire Wire Line
6600 3000 7600 3000
Wire Wire Line
7600 3100 6600 3100
Wire Wire Line
6600 3200 7600 3200
Wire Wire Line
6600 3400 7600 3400
Wire Wire Line
7600 3500 6600 3500
Wire Wire Line
6600 3600 7600 3600
Wire Wire Line
7600 3700 6600 3700
Wire Wire Line
6600 3800 7600 3800
Wire Wire Line
7600 3900 6600 3900
Wire Wire Line
6600 4000 7600 4000
Wire Wire Line
6600 4200 7600 4200
Wire Wire Line
6600 4300 7600 4300
Wire Wire Line
7600 4400 6600 4400
Wire Wire Line
6600 4500 7600 4500
Wire Wire Line
7600 4600 6600 4600
Wire Wire Line
6600 4700 7600 4700
Wire Wire Line
7600 4800 6600 4800
Wire Wire Line
3700 1900 4700 1900
Wire Wire Line
4700 2000 3700 2000
Wire Wire Line
3700 2100 4700 2100
Wire Wire Line
4700 2200 3700 2200
Wire Wire Line
3700 2300 4700 2300
Wire Wire Line
4700 2500 4000 2500
Wire Wire Line
3700 2600 4100 2600
Wire Wire Line
9800 1900 9800 2400
Connection ~ 9800 2400
Connection ~ 9800 2900
$Comp
L fiducial:FIDUCIAL FID1
U 1 1 53B309AC
P 4100 7100
F 0 "FID1" H 4100 7225 60 0000 C CNN
F 1 "FIDUCIAL" H 4100 6975 60 0000 C CNN
F 2 "fiducial:FIDUCIAL_65MIL" H 4100 7100 60 0001 C CNN
F 3 "" H 4100 7100 60 0000 C CNN
1 4100 7100
1 0 0 -1
$EndComp
$Comp
L fiducial:FIDUCIAL FID2
U 1 1 53B30B4C
P 4100 7500
F 0 "FID2" H 4100 7625 60 0000 C CNN
F 1 "FIDUCIAL" H 4100 7375 60 0000 C CNN
F 2 "fiducial:FIDUCIAL_65MIL" H 4100 7500 60 0001 C CNN
F 3 "" H 4100 7500 60 0000 C CNN
1 4100 7500
1 0 0 -1
$EndComp
$Comp
L fiducial:FIDUCIAL FID3
U 1 1 53B30CEC
P 4700 7100
F 0 "FID3" H 4700 7225 60 0000 C CNN
F 1 "FIDUCIAL" H 4700 6975 60 0000 C CNN
F 2 "fiducial:FIDUCIAL_65MIL" H 4700 7100 60 0001 C CNN
F 3 "" H 4700 7100 60 0000 C CNN
1 4700 7100
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR01
U 1 1 53B3303D
P 9800 3500
F 0 "#PWR01" H 9800 3500 30 0001 C CNN
F 1 "GND" H 9800 3430 30 0001 C CNN
F 2 "" H 9800 3500 60 0000 C CNN
F 3 "" H 9800 3500 60 0000 C CNN
1 9800 3500
1 0 0 -1
$EndComp
Wire Wire Line
9700 3400 9800 3400
Connection ~ 9800 3400
Wire Wire Line
6600 2000 7600 2000
Wire Wire Line
4700 1700 3700 1700
$Sheet
S 4700 5600 1900 1000
U 58CFF3E3
F0 "power" 50
F1 "power.sch" 50
F2 "LCD_VBL" O R 6600 6200 60
F3 "AUDIO_SVDD" O L 4700 6200 60
F4 "AUDIO_AVDD" O L 4700 6100 60
F5 "AUDIO_DVDD" O L 4700 6000 60
F6 "AUDIO_TVDD" O L 4700 5900 60
F7 "VBUS" I R 6600 5700 60
F8 "VBUSCTRL" O R 6600 5800 60
F9 "VIN" O R 6600 5900 60
F10 "VBAT" O L 4700 5700 60
F11 "REF_CLK" O L 4700 6500 60
F12 "REF_EN" I L 4700 6400 60
F13 "GPS_VCC" O R 6600 6400 60
$EndSheet
Wire Wire Line
6600 6200 7600 6200
Wire Wire Line
3700 6200 4700 6200
Wire Wire Line
4700 6100 3700 6100
Wire Wire Line
3700 6000 4700 6000
Wire Wire Line
4700 5900 3700 5900
Wire Wire Line
4700 5700 4500 5700
Wire Wire Line
4500 5700 4500 5200
Wire Wire Line
4500 5200 4700 5200
Wire Wire Line
6600 5700 6800 5700
Wire Wire Line
6800 5700 6800 5000
Wire Wire Line
6800 5000 6600 5000
Wire Wire Line
6600 5100 6900 5100
Wire Wire Line
6900 5100 6900 5800
Wire Wire Line
6900 5800 6600 5800
Wire Wire Line
6600 5200 7000 5200
Wire Wire Line
7000 5200 7000 5900
Wire Wire Line
7000 5900 6600 5900
Wire Wire Line
9800 2400 9800 2900
Wire Wire Line
9800 2900 9800 3400
Wire Wire Line
9800 3400 9800 3500
Wire Wire Line
4700 5000 4300 5000
Wire Wire Line
4300 5000 4300 6400
Wire Wire Line
4300 6400 4700 6400
Wire Wire Line
4700 6500 4200 6500
Wire Wire Line
4200 6500 4200 4900
Wire Wire Line
4200 4900 4700 4900
$Sheet
S 4700 600 1900 800
U 5B7E0B2A
F0 "gps" 50
F1 "gps.sch" 50
F2 "SDA" B L 4700 800 60
F3 "SCL" B L 4700 700 60
F4 "V_BACKUP" I L 4700 1300 60
F5 "VCC" I R 6600 1300 60
F6 "TIMEPULSE" O L 4700 1000 60
F7 "RESET#" I L 4700 1100 60
F8 "TX_READY" O L 4700 900 60
$EndSheet
Wire Wire Line
4700 700 4000 700
Wire Wire Line
4000 700 4000 2500
Connection ~ 4000 2500
Wire Wire Line
4000 2500 3700 2500
Wire Wire Line
4700 800 4100 800
Wire Wire Line
4100 800 4100 2600
Connection ~ 4100 2600
Wire Wire Line
4100 2600 4700 2600
Wire Wire Line
4700 1300 4500 1300
Wire Wire Line
4500 1300 4500 5200
Connection ~ 4500 5200
Wire Wire Line
4200 2800 4700 2800
Wire Wire Line
4700 2900 4300 2900
Wire Wire Line
4700 900 4200 900
Wire Wire Line
4200 900 4200 2800
Wire Wire Line
4700 1000 4300 1000
Wire Wire Line
4300 1000 4300 2900
Wire Wire Line
4700 1100 4400 1100
Wire Wire Line
4400 1100 4400 3000
Wire Wire Line
4400 3000 4700 3000
Wire Wire Line
6600 6400 7100 6400
Wire Wire Line
7100 6400 7100 1300
Wire Wire Line
6600 1300 7100 1300
$EndSCHEMATC

1151
Software/portapack-mayhem/hardware/portapack_h1/power.sch Normal file
View File

File diff suppressed because it is too large Load Diff

25
Software/portapack-mayhem/hardware/portapack_h1/sym-lib-table Normal file
View File

@@ -0,0 +1,25 @@
(sym_lib_table
(lib (name hackrf_expansion)(type Legacy)(uri ${KISBLIB}/hackrf_expansion.lib)(options "")(descr ""))
(lib (name passive)(type Legacy)(uri ${KISBLIB}/passive.lib)(options "")(descr ""))
(lib (name trs_jack)(type Legacy)(uri ${KISBLIB}/trs_jack.lib)(options "")(descr ""))
(lib (name battery)(type Legacy)(uri ${KISBLIB}/battery.lib)(options "")(descr ""))
(lib (name sd)(type Legacy)(uri ${KISBLIB}/sd.lib)(options "")(descr ""))
(lib (name ck)(type Legacy)(uri ${KISBLIB}/ck.lib)(options "")(descr ""))
(lib (name altera)(type Legacy)(uri ${KISBLIB}/altera.lib)(options "")(descr ""))
(lib (name regulator)(type Legacy)(uri ${KISBLIB}/regulator.lib)(options "")(descr ""))
(lib (name tp)(type Legacy)(uri ${KISBLIB}/tp.lib)(options "")(descr ""))
(lib (name header)(type Legacy)(uri ${KISBLIB}/header.lib)(options "")(descr ""))
(lib (name hole)(type Legacy)(uri ${KISBLIB}/hole.lib)(options "")(descr ""))
(lib (name sharebrained)(type Legacy)(uri ${KISBLIB}/sharebrained.lib)(options "")(descr ""))
(lib (name fiducial)(type Legacy)(uri ${KISBLIB}/fiducial.lib)(options "")(descr ""))
(lib (name eastrising)(type Legacy)(uri ${KISBLIB}/eastrising.lib)(options "")(descr ""))
(lib (name on_semi)(type Legacy)(uri ${KISBLIB}/on_semi.lib)(options "")(descr ""))
(lib (name asahi_kasei)(type Legacy)(uri ${KISBLIB}/asahi_kasei.lib)(options "")(descr ""))
(lib (name ti)(type Legacy)(uri ${KISBLIB}/ti.lib)(options "")(descr ""))
(lib (name diode)(type Legacy)(uri ${KISBLIB}/diode.lib)(options "")(descr ""))
(lib (name esd)(type Legacy)(uri ${KISBLIB}/esd.lib)(options "")(descr ""))
(lib (name osc)(type Legacy)(uri ${KISBLIB}/osc.lib)(options "")(descr ""))
(lib (name logic)(type Legacy)(uri ${KISBLIB}/logic.lib)(options "")(descr ""))
(lib (name ublox)(type Legacy)(uri ${KISBLIB}/ublox.lib)(options "")(descr ""))
(lib (name conn_rf)(type Legacy)(uri ${KISBLIB}/conn_rf.lib)(options "")(descr ""))
)

7
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Enclosure
https://www.thingiverse.com/thing:4260973
Cover
https://www.thingiverse.com/thing:4278961

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