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This commit is contained in:
RocketGod
2022-09-22 09:26:57 -07:00
parent fee0ab05fd
commit 957ea3d712
4511 changed files with 1943182 additions and 0 deletions
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31
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/adc.h Normal file
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/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(STM32F0)
# include <libopencm3/stm32/f0/adc.h>
#elif defined(STM32F1)
# include <libopencm3/stm32/f1/adc.h>
#elif defined(STM32F3)
# include <libopencm3/stm32/f3/adc.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/adc.h>
#else
# error "stm32 family not defined."
#endif

679
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/can.h Normal file
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/** @defgroup can_defines CAN defines
@ingroup STM32F_defines
@brief <b>libopencm3 Defined Constants and Types for STM32 CAN </b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
@date 12 November 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CAN_H
#define LIBOPENCM3_CAN_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/**@{*/
/* --- Convenience macros -------------------------------------------------- */
/* CAN register base addresses (for convenience) */
/*****************************************************************************/
/** @defgroup can_reg_base CAN register base address
@ingroup can_defines
@{*/
#define CAN1 BX_CAN1_BASE
#define CAN2 BX_CAN2_BASE
/**@}*/
/* --- CAN registers ------------------------------------------------------- */
/* CAN master control register (CAN_MCR) */
#define CAN_MCR(can_base) MMIO32(can_base + 0x000)
/* CAN master status register (CAN_MSR) */
#define CAN_MSR(can_base) MMIO32(can_base + 0x004)
/* CAN transmit status register (CAN_TSR) */
#define CAN_TSR(can_base) MMIO32(can_base + 0x008)
/* CAN receive FIFO 0 register (CAN_RF0R) */
#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C)
/* CAN receive FIFO 1 register (CAN_RF1R) */
#define CAN_RF1R(can_base) MMIO32(can_base + 0x010)
/* CAN interrupt enable register (CAN_IER) */
#define CAN_IER(can_base) MMIO32(can_base + 0x014)
/* CAN error status register (CAN_ESR) */
#define CAN_ESR(can_base) MMIO32(can_base + 0x018)
/* CAN bit timing register (CAN_BTR) */
#define CAN_BTR(can_base) MMIO32(can_base + 0x01C)
/* Registers in the offset range 0x020 to 0x17F are reserved. */
/* --- CAN mailbox registers ----------------------------------------------- */
/* CAN mailbox / FIFO register offsets */
#define CAN_MBOX0 0x180
#define CAN_MBOX1 0x190
#define CAN_MBOX2 0x1A0
#define CAN_FIFO0 0x1B0
#define CAN_FIFO1 0x1C0
/* CAN TX mailbox identifier register (CAN_TIxR) */
#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0)
#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)
#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)
#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)
/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */
#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4)
#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0)
#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1)
#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2)
/* CAN mailbox data low register (CAN_TDLxR) */
#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8)
#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0)
#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1)
#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2)
/* CAN mailbox data high register (CAN_TDHxR) */
#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC)
#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0)
#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1)
#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2)
/* CAN RX FIFO identifier register (CAN_RIxR) */
#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0)
#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0)
#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1)
/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */
#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4)
#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0)
#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1)
/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */
#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8)
#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0)
#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1)
/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */
#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC)
#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0)
#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1)
/* --- CAN filter registers ------------------------------------------------ */
/* CAN filter master register (CAN_FMR) */
#define CAN_FMR(can_base) MMIO32(can_base + 0x200)
/* CAN filter mode register (CAN_FM1R) */
#define CAN_FM1R(can_base) MMIO32(can_base + 0x204)
/* Register offset 0x208 is reserved. */
/* CAN filter scale register (CAN_FS1R) */
#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C)
/* Register offset 0x210 is reserved. */
/* CAN filter FIFO assignement register (CAN_FFA1R) */
#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214)
/* Register offset 0x218 is reserved. */
/* CAN filter activation register (CAN_FA1R) */
#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C)
/* Register offset 0x220 is reserved. */
/* Registers with offset 0x224 to 0x23F are reserved. */
/* CAN filter bank registers (CAN_FiRx) */
/*
* Connectivity line devices have 28 banks so the bank ID spans 0..27
* all other devices have 14 banks so the bank ID spans 0..13.
*/
#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + \
(bank * 0x8) + 0x0)
#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + \
(bank * 0x8) + 0x4)
/* --- CAN_MCR values ------------------------------------------------------ */
/* 31:17 Reserved, forced by hardware to 0 */
/* DBF: Debug freeze */
#define CAN_MCR_DBF (1 << 16)
/* RESET: bxCAN software master reset */
#define CAN_MCR_RESET (1 << 15)
/* 14:8 Reserved, forced by hardware to 0 */
/* TTCM: Time triggered communication mode */
#define CAN_MCR_TTCM (1 << 7)
/* ABOM: Automatic bus-off management */
#define CAN_MCR_ABOM (1 << 6)
/* AWUM: Automatic wakeup mode */
#define CAN_MCR_AWUM (1 << 5)
/* NART: No automatic retransmission */
#define CAN_MCR_NART (1 << 4)
/* RFLM: Receive FIFO locked mode */
#define CAN_MCR_RFLM (1 << 3)
/* TXFP: Transmit FIFO priority */
#define CAN_MCR_TXFP (1 << 2)
/* SLEEP: Sleep mode request */
#define CAN_MCR_SLEEP (1 << 1)
/* INRQ: Initialization request */
#define CAN_MCR_INRQ (1 << 0)
/* --- CAN_MSR values ------------------------------------------------------ */
/* 31:12 Reserved, forced by hardware to 0 */
/* RX: CAN Rx signal */
#define CAN_MSR_RX (1 << 11)
/* SAMP: Last sample point */
#define CAN_MSR_SAMP (1 << 10)
/* RXM: Receive mode */
#define CAN_MSR_RXM (1 << 9)
/* TXM: Transmit mode */
#define CAN_MSR_TXM (1 << 8)
/* 7:5 Reserved, forced by hardware to 0 */
/* SLAKI: Sleep acknowledge interrupt */
#define CAN_MSR_SLAKI (1 << 4)
/* WKUI: Wakeup interrupt */
#define CAN_MSR_WKUI (1 << 3)
/* ERRI: Error interrupt */
#define CAN_MSR_ERRI (1 << 2)
/* SLAK: Sleep acknowledge */
#define CAN_MSR_SLAK (1 << 1)
/* INAK: Initialization acknowledge */
#define CAN_MSR_INAK (1 << 0)
/* --- CAN_TSR values ------------------------------------------------------ */
/* LOW2: Lowest priority flag for mailbox 2 */
#define CAN_TSR_LOW2 (1 << 31)
/* LOW1: Lowest priority flag for mailbox 1 */
#define CAN_TSR_LOW1 (1 << 30)
/* LOW0: Lowest priority flag for mailbox 0 */
#define CAN_TSR_LOW0 (1 << 29)
/* TME2: Transmit mailbox 2 empty */
#define CAN_TSR_TME2 (1 << 28)
/* TME1: Transmit mailbox 1 empty */
#define CAN_TSR_TME1 (1 << 27)
/* TME0: Transmit mailbox 0 empty */
#define CAN_TSR_TME0 (1 << 26)
/* CODE[1:0]: Mailbox code */
#define CAN_TSR_CODE_MASK (0x3 << 24)
/* ABRQ2: Abort request for mailbox 2 */
#define CAN_TSR_TABRQ2 (1 << 23)
/* 22:20 Reserved, forced by hardware to 0 */
/* TERR2: Transmission error for mailbox 2 */
#define CAN_TSR_TERR2 (1 << 19)
/* ALST2: Arbitration lost for mailbox 2 */
#define CAN_TSR_ALST2 (1 << 18)
/* TXOK2: Transmission OK for mailbox 2 */
#define CAN_TSR_TXOK2 (1 << 17)
/* RQCP2: Request completed mailbox 2 */
#define CAN_TSR_RQCP2 (1 << 16)
/* ABRQ1: Abort request for mailbox 1 */
#define CAN_TSR_ABRQ1 (1 << 15)
/* 14:12 Reserved, forced by hardware to 0 */
/* TERR1: Transmission error for mailbox 1 */
#define CAN_TSR_TERR1 (1 << 11)
/* ALST1: Arbitration lost for mailbox 1 */
#define CAN_TSR_ALST1 (1 << 10)
/* TXOK1: Transmission OK for mailbox 1 */
#define CAN_TSR_TXOK1 (1 << 9)
/* RQCP1: Request completed mailbox 1 */
#define CAN_TSR_RQCP1 (1 << 8)
/* ABRQ0: Abort request for mailbox 0 */
#define CAN_TSR_ABRQ0 (1 << 7)
/* 6:4 Reserved, forced by hardware to 0 */
/* TERR0: Transmission error for mailbox 0 */
#define CAN_TSR_TERR0 (1 << 3)
/* ALST0: Arbitration lost for mailbox 0 */
#define CAN_TSR_ALST0 (1 << 2)
/* TXOK0: Transmission OK for mailbox 0 */
#define CAN_TSR_TXOK0 (1 << 1)
/* RQCP0: Request completed mailbox 0 */
#define CAN_TSR_RQCP0 (1 << 0)
/* --- CAN_RF0R values ----------------------------------------------------- */
/* 31:6 Reserved, forced by hardware to 0 */
/* RFOM0: Release FIFO 0 output mailbox */
#define CAN_RF0R_RFOM0 (1 << 5)
/* FOVR0: FIFO 0 overrun */
#define CAN_RF0R_FAVR0 (1 << 4)
/* FULL0: FIFO 0 full */
#define CAN_RF0R_FULL0 (1 << 3)
/* 2 Reserved, forced by hardware to 0 */
/* FMP0[1:0]: FIFO 0 message pending */
#define CAN_RF0R_FMP0_MASK (0x3 << 0)
/* --- CAN_RF1R values ----------------------------------------------------- */
/* 31:6 Reserved, forced by hardware to 0 */
/* RFOM1: Release FIFO 1 output mailbox */
#define CAN_RF1R_RFOM1 (1 << 5)
/* FOVR1: FIFO 1 overrun */
#define CAN_RF1R_FAVR1 (1 << 4)
/* FULL1: FIFO 1 full */
#define CAN_RF1R_FULL1 (1 << 3)
/* 2 Reserved, forced by hardware to 0 */
/* FMP1[1:0]: FIFO 1 message pending */
#define CAN_RF1R_FMP1_MASK (0x3 << 0)
/* --- CAN_IER values ------------------------------------------------------ */
/* 32:18 Reserved, forced by hardware to 0 */
/* SLKIE: Sleep interrupt enable */
#define CAN_IER_SLKIE (1 << 17)
/* WKUIE: Wakeup interrupt enable */
#define CAN_IER_WKUIE (1 << 16)
/* ERRIE: Error interrupt enable */
#define CAN_IER_ERRIE (1 << 15)
/* 14:12 Reserved, forced by hardware to 0 */
/* LECIE: Last error code interrupt enable */
#define CAN_IER_LECIE (1 << 11)
/* BOFIE: Bus-off interrupt enable */
#define CAN_IER_BOFIE (1 << 10)
/* EPVIE: Error passive interrupt enable */
#define CAN_IER_EPVIE (1 << 9)
/* EWGIE: Error warning interrupt enable */
#define CAN_IER_EWGIE (1 << 8)
/* 7 Reserved, forced by hardware to 0 */
/* FOVIE1: FIFO overrun interrupt enable */
#define CAN_IER_FOVIE1 (1 << 6)
/* FFIE1: FIFO full interrupt enable */
#define CAN_IER_FFIE1 (1 << 5)
/* FMPIE1: FIFO message pending interrupt enable */
#define CAN_IER_FMPIE1 (1 << 4)
/* FOVIE0: FIFO overrun interrupt enable */
#define CAN_IER_FOVIE0 (1 << 3)
/* FFIE0: FIFO full interrupt enable */
#define CAN_IER_FFIE0 (1 << 2)
/* FMPIE0: FIFO message pending interrupt enable */
#define CAN_IER_FMPIE0 (1 << 1)
/* TMEIE: Transmit mailbox empty interrupt enable */
#define CAN_IER_TMEIE (1 << 0)
/* --- CAN_ESR values ------------------------------------------------------ */
/* REC[7:0]: Receive error counter */
#define CAN_ESR_REC_MASK (0xF << 24)
/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */
#define CAN_ESR_TEC_MASK (0xF << 16)
/* 15:7 Reserved, forced by hardware to 0 */
/* LEC[2:0]: Last error code */
#define CAN_ESR_LEC_NO_ERROR (0x0 << 4)
#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4)
#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4)
#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4)
#define CAN_ESR_LEC_REC_ERROR (0x4 << 4)
#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4)
#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4)
#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4)
#define CAN_ESR_LEC_MASK (0x7 << 4)
/* 3 Reserved, forced by hardware to 0 */
/* BOFF: Bus-off flag */
#define CAN_ESR_BOFF (1 << 2)
/* EPVF: Error passive flag */
#define CAN_ESR_EPVF (1 << 1)
/* EWGF: Error warning flag */
#define CAN_ESR_EWGF (1 << 0)
/* --- CAN_BTR values ------------------------------------------------------ */
/* SILM: Silent mode (debug) */
#define CAN_BTR_SILM (1 << 31)
/* LBKM: Loop back mode (debug) */
#define CAN_BTR_LBKM (1 << 30)
/* 29:26 Reserved, forced by hardware to 0 */
/* SJW[1:0]: Resynchronization jump width */
#define CAN_BTR_SJW_1TQ (0x0 << 24)
#define CAN_BTR_SJW_2TQ (0x1 << 24)
#define CAN_BTR_SJW_3TQ (0x2 << 24)
#define CAN_BTR_SJW_4TQ (0x3 << 24)
#define CAN_BTR_SJW_MASK (0x3 << 24)
#define CAN_BTR_SJW_SHIFT 24
/* 23 Reserved, forced by hardware to 0 */
/* TS2[2:0]: Time segment 2 */
#define CAN_BTR_TS2_1TQ (0x0 << 20)
#define CAN_BTR_TS2_2TQ (0x1 << 20)
#define CAN_BTR_TS2_3TQ (0x2 << 20)
#define CAN_BTR_TS2_4TQ (0x3 << 20)
#define CAN_BTR_TS2_5TQ (0x4 << 20)
#define CAN_BTR_TS2_6TQ (0x5 << 20)
#define CAN_BTR_TS2_7TQ (0x6 << 20)
#define CAN_BTR_TS2_8TQ (0x7 << 20)
#define CAN_BTR_TS2_MASK (0x7 << 20)
#define CAN_BTR_TS2_SHIFT 20
/* TS1[3:0]: Time segment 1 */
#define CAN_BTR_TS1_1TQ (0x0 << 16)
#define CAN_BTR_TS1_2TQ (0x1 << 16)
#define CAN_BTR_TS1_3TQ (0x2 << 16)
#define CAN_BTR_TS1_4TQ (0x3 << 16)
#define CAN_BTR_TS1_5TQ (0x4 << 16)
#define CAN_BTR_TS1_6TQ (0x5 << 16)
#define CAN_BTR_TS1_7TQ (0x6 << 16)
#define CAN_BTR_TS1_8TQ (0x7 << 16)
#define CAN_BTR_TS1_9TQ (0x8 << 16)
#define CAN_BTR_TS1_10TQ (0x9 << 16)
#define CAN_BTR_TS1_11TQ (0xA << 16)
#define CAN_BTR_TS1_12TQ (0xB << 16)
#define CAN_BTR_TS1_13TQ (0xC << 16)
#define CAN_BTR_TS1_14TQ (0xD << 16)
#define CAN_BTR_TS1_15TQ (0xE << 16)
#define CAN_BTR_TS1_16TQ (0xF << 16)
#define CAN_BTR_TS1_MASK (0xF << 16)
#define CAN_BTR_TS1_SHIFT 16
/* 15:10 Reserved, forced by hardware to 0 */
/* BRP[9:0]: Baud rate prescaler */
#define CAN_BTR_BRP_MASK (0x1FFUL << 0)
/* --- CAN_TIxR values ------------------------------------------------------ */
/* STID[10:0]: Standard identifier */
#define CAN_TIxR_STID_MASK (0x7FF << 21)
#define CAN_TIxR_STID_SHIFT 21
/* EXID[15:0]: Extended identifier */
#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3)
#define CAN_TIxR_EXID_SHIFT 3
/* IDE: Identifier extension */
#define CAN_TIxR_IDE (1 << 2)
/* RTR: Remote transmission request */
#define CAN_TIxR_RTR (1 << 1)
/* TXRQ: Transmit mailbox request */
#define CAN_TIxR_TXRQ (1 << 0)
/* --- CAN_TDTxR values ----------------------------------------------------- */
/* TIME[15:0]: Message time stamp */
#define CAN_TDTxR_TIME_MASK (0xFFFF << 15)
#define CAN_TDTxR_TIME_SHIFT 15
/* 15:6 Reserved, forced by hardware to 0 */
/* TGT: Transmit global time */
#define CAN_TDTxR_TGT (1 << 5)
/* 7:4 Reserved, forced by hardware to 0 */
/* DLC[3:0]: Data length code */
#define CAN_TDTxR_DLC_MASK (0xF << 0)
#define CAN_TDTxR_DLC_SHIFT 0
/* --- CAN_TDLxR values ----------------------------------------------------- */
/* DATA3[7:0]: Data byte 3 */
/* DATA2[7:0]: Data byte 2 */
/* DATA1[7:0]: Data byte 1 */
/* DATA0[7:0]: Data byte 0 */
/* --- CAN_TDHxR values ----------------------------------------------------- */
/* DATA7[7:0]: Data byte 7 */
/* DATA6[7:0]: Data byte 6 */
/* DATA5[7:0]: Data byte 5 */
/* DATA4[7:0]: Data byte 4 */
/* --- CAN_RIxR values ------------------------------------------------------ */
/* STID[10:0]: Standard identifier */
#define CAN_RIxR_STID_MASK (0x7FF)
#define CAN_RIxR_STID_SHIFT 21
/* EXID[15:0]: Extended identifier */
#define CAN_RIxR_EXID_MASK (0x1FFFFFFF)
#define CAN_RIxR_EXID_SHIFT 3
/* IDE: Identifier extension */
#define CAN_RIxR_IDE (1 << 2)
/* RTR: Remote transmission request */
#define CAN_RIxR_RTR (1 << 1)
/* 0 Reserved */
/* --- CAN_RDTxR values ----------------------------------------------------- */
/* TIME[15:0]: Message time stamp */
#define CAN_RDTxR_TIME_MASK (0xFFFF << 15)
#define CAN_RDTxR_TIME_SHIFT 15
/* FMI[7:0]: Filter match index */
#define CAN_RDTxR_FMI_MASK (0xFF << 8)
#define CAN_RDTxR_FMI_SHIFT 8
/* 7:4 Reserved, forced by hardware to 0 */
/* DLC[3:0]: Data length code */
#define CAN_RDTxR_DLC_MASK (0xF << 0)
#define CAN_RDTxR_DLC_SHIFT 0
/* --- CAN_RDLxR values ----------------------------------------------------- */
/* DATA3[7:0]: Data byte 3 */
/* DATA2[7:0]: Data byte 2 */
/* DATA1[7:0]: Data byte 1 */
/* DATA0[7:0]: Data byte 0 */
/* --- CAN_RDHxR values ----------------------------------------------------- */
/* DATA7[7:0]: Data byte 7 */
/* DATA6[7:0]: Data byte 6 */
/* DATA5[7:0]: Data byte 5 */
/* DATA4[7:0]: Data byte 4 */
/* --- CAN_FMR values ------------------------------------------------------- */
/* 31:14 Reserved, forced to reset value */
/*
* CAN2SB[5:0]: CAN2 start bank
* (only on connectivity line devices otherwise reserved)
*/
#define CAN_FMR_CAN2SB_MASK (0x3F << 8)
#define CAN_FMR_CAN2SB_SHIFT 15
/* 7:1 Reserved, forced to reset value */
/* FINIT: Filter init mode */
#define CAN_FMR_FINIT (1 << 0)
/* --- CAN_FM1R values ------------------------------------------------------ */
/* 31:28 Reserved, forced by hardware to 0 */
/*
* FBMx: Filter mode
* x is 0..27 should be calculated by a helper function making so many macros
* seems like an overkill?
*/
/* --- CAN_FS1R values ------------------------------------------------------ */
/* 31:28 Reserved, forced by hardware to 0 */
/*
* FSCx: Filter scale configuration
* x is 0..27 should be calculated by a helper function making so many macros
* seems like an overkill?
*/
/* --- CAN_FFA1R values ----------------------------------------------------- */
/* 31:28 Reserved, forced by hardware to 0 */
/*
* FFAx: Filter scale configuration
* x is 0..27 should be calculated by a helper function making so many macros
* seems like an overkill?
*/
/* --- CAN_FA1R values ------------------------------------------------------ */
/* 31:28 Reserved, forced by hardware to 0 */
/*
* FACTx: Filter active
* x is 0..27 should be calculated by a helper function making so many macros
* seems like an overkill?
*/
/* --- CAN_FiRx values ------------------------------------------------------ */
/* FB[31:0]: Filter bits */
/* --- CAN functions -------------------------------------------------------- */
BEGIN_DECLS
void can_reset(uint32_t canport);
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2,
uint32_t brp, bool loopback, bool silent);
void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit,
bool id_list_mode, uint32_t fr1, uint32_t fr2,
uint32_t fifo, bool enable);
void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1,
uint16_t mask1, uint16_t id2,
uint16_t mask2, uint32_t fifo, bool enable);
void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id,
uint32_t mask, uint32_t fifo, bool enable);
void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1,
uint16_t id2, uint16_t id3, uint16_t id4,
uint32_t fifo, bool enable);
void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1,
uint32_t id2, uint32_t fifo, bool enable);
void can_enable_irq(uint32_t canport, uint32_t irq);
void can_disable_irq(uint32_t canport, uint32_t irq);
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr,
uint8_t length, uint8_t *data);
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id,
bool *ext, bool *rtr, uint32_t *fmi, uint8_t *length,
uint8_t *data);
void can_fifo_release(uint32_t canport, uint8_t fifo);
bool can_available_mailbox(uint32_t canport);
END_DECLS
#endif

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/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(STM32F0)
# include <libopencm3/stm32/f0/cec.h>
#else
# error "stm32 family not defined."
#endif

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/** @addtogroup crc_defines
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H
The order of header inclusion is important. crc.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_CRC_H
/** @endcond */
#ifndef LIBOPENCM3_CRC_COMMON_ALL_H
#define LIBOPENCM3_CRC_COMMON_ALL_H
/**@{*/
#include <libopencm3/cm3/common.h>
/* --- CRC registers ------------------------------------------------------- */
/* Data register (CRC_DR) */
#define CRC_DR MMIO32(CRC_BASE + 0x00)
/* Independent data register (CRC_IDR) */
#define CRC_IDR MMIO32(CRC_BASE + 0x04)
/* Control register (CRC_CR) */
#define CRC_CR MMIO32(CRC_BASE + 0x08)
/* --- CRC_DR values ------------------------------------------------------- */
/* Bits [31:0]: Data register */
/* --- CRC_IDR values ------------------------------------------------------ */
/* Bits [31:8]: Reserved */
/* Bits [7:0]: General-purpose 8-bit data register bits */
/* --- CRC_CR values ------------------------------------------------------- */
/* Bits [31:1]: Reserved */
/* RESET bit */
#define CRC_CR_RESET (1 << 0)
/* --- CRC function prototypes --------------------------------------------- */
BEGIN_DECLS
/* TODO */
/**
* Reset the CRC calculator to initial values.
*/
void crc_reset(void);
/**
* Add a word to the CRC calculator and return the result.
* @param data new word to add to the CRC calculator
* @return final CRC calculator value
*/
uint32_t crc_calculate(uint32_t data);
/**
* Add a block of data to the CRC calculator and return the final result
* @param datap pointer to the start of a block of 32bit data words
* @param size length of data, in 32bit increments
* @return final CRC calculator value
*/
uint32_t crc_calculate_block(uint32_t *datap, int size);
END_DECLS
/**@}*/
#endif
/** @cond */
#else
#warning "crc_common_all.h should not be included explicitly, only via crc.h"
#endif
/** @endcond */

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/** @addtogroup crypto_defines
*
* @warning The CRYP subsystem is present only in a limited set of devices,
* see next section for list of supported devices.
*
* @section crypto_api_supported Supported devices
*
* - STM32F205
* - STM32F207
* - STM32F215
* - STM32F217
* - STM32F405
* - STM32F407
* - STM32F415
* - STM32F417 <i>(tested)</i>
* - STM32F427
* - STM32F437
*
* @section crypto_api_theory Theory of operation
*
*
*
* @section crypto_api_basic Basic handling API
*
*
* @b Example @b 1: Blocking mode
*
* @code
* //[enable-clocks]
* crypto_set_key(CRYPTO_KEY_128BIT,key);
* crypto_set_iv(iv); // only in CBC or CTR mode
* crypto_set_datatype(CRYPTO_DATA_16BIT);
* crypto_set_algorithm(ENCRYPT_AES_ECB);
* crypto_start();
* foreach(block in blocks)
* crypto_process_block(plaintext,ciphertext,blocksize);
* crypto_stop();
* @endcode
*
* @section crypto_api_interrupt Interrupt supported handling API
*
* @warning This operation mode is currently not supported.
*
* @b Example @b 2: Interrupt mode
*
* @code
* //[enable-clocks]
* crypto_set_key(CRYPTO_KEY_128BIT,key);
* crypto_set_iv(iv); // only in CBC or CTR mode
* crypto_set_datatype(CRYPTO_DATA_16BIT);
* crypto_set_algorithm(ENCRYPT_AES_ECB);
* crypto_start();
* [... API to be described later ...]
* crypto_stop();
* @endcode
*
* @section crypto_api_dma DMA handling API
*
* @warning This operation mode is currently not supported.
*
* @b Example @b 3: DMA mode
*
* @code
* //[enable-clocks]
* crypto_set_key(CRYPTO_KEY_128BIT,key);
* crypto_set_iv(iv); // only in CBC or CTR mode
* crypto_set_datatype(CRYPTO_DATA_16BIT);
* crypto_set_algorithm(ENCRYPT_AES_ECB);
* crypto_start();
* [... API to be described later ...]
* crypto_stop();
* @endcode
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRYP.H
The order of header inclusion is important. cryp.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_CRYPTO_H
/** @endcond */
#ifndef LIBOPENCM3_CRYPTO_COMMON_F24_H
#define LIBOPENCM3_CRYPTO_COMMON_F24_H
#include <libopencm3/cm3/common.h>
/**@{*/
/* --- CRYP registers ------------------------------------------------------ */
/** @defgroup crypto_registers_gen Registers (Generic)
*
* @brief Register access to the CRYP controller. (All chips)
*
* @ingroup crypto_defines
*/
/**@{*/
#define CRYP CRYP_BASE
/* CRYP Control Register (CRYP_CR) */
#define CRYP_CR MMIO32(CRYP_BASE + 0x00)
/* CRYP Status Register (CRYP_SR) */
#define CRYP_SR MMIO32(CRYP_BASE + 0x04)
/* CRYP Data Input Register (CRYP_DIN) */
#define CRYP_DIN MMIO32(CRYP_BASE + 0x08)
/** CRYP Data Output Register (CRYP_DOUT) @see blablabla */
#define CRYP_DOUT MMIO32(CRYP_BASE + 0x0C)
/* CRYP DMA Control Register (CRYP_DMACR) */
#define CRYP_DMACR MMIO32(CRYP_BASE + 0x10)
/* CRYP Interrupt mask set/clear register (CRYP_IMSCR) */
#define CRYP_IMSCR MMIO32(CRYP_BASE + 0x14)
/* CRYP Raw Interrupt status register (CRYP_RISR) */
#define CRYP_RISR MMIO32(CRYP_BASE + 0x18)
/* CRYP Masked Interrupt status register (CRYP_MISR) */
#define CRYP_MISR MMIO32(CRYP_BASE + 0x1C)
/* CRYP Key registers (CRYP_KxLR) x=0..3 */
#define CRYP_KR(i) MMIO64(CRYP_BASE + 0x20 + (i) * 8)
/* CRYP Initialization Vector Registers (CRYP_IVxLR) x=0..1 */
#define CRYP_IVR(i) MMIO32(CRYP_BASE + 0x40 + (i) * 8)
/* --- CRYP_CR values ------------------------------------------------------ */
/* ALGODIR: Algorithm direction */
#define CRYP_CR_ALGODIR (1 << 2)
/* ALGOMODE: Algorithm mode */
#define CRYP_CR_ALGOMODE_SHIFT 3
#define CRYP_CR_ALGOMODE (7 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_TDES_ECB (0 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_TDES_CBC (1 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_DES_ECB (2 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_DES_CBC (3 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_AES_ECB (4 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_AES_CBC (5 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_AES_CTR (6 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_AES_PREP (7 << CRYP_CR_ALGOMODE_SHIFT)
/* DATATYPE: Data type selection */
#define CRYP_CR_DATATYPE_SHIFT 6
#define CRYP_CR_DATATYPE (3 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_32 (0 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_16 (1 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_8 (2 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_BIT (3 << CRYP_CR_DATATYPE_SHIFT)
/* KEYSIZE: Key size selection (AES mode only)*/
#define CRYP_CR_KEYSIZE_SHIFT 8
#define CRYP_CR_KEYSIZE (3 << CRYP_CR_KEYSIZE_SHIFT)
#define CRYP_CR_KEYSIZE_128 (0 << CRYP_CR_KEYSIZE_SHIFT)
#define CRYP_CR_KEYSIZE_192 (1 << CRYP_CR_KEYSIZE_SHIFT)
#define CRYP_CR_KEYSIZE_256 (2 << CRYP_CR_KEYSIZE_SHIFT)
/* FFLUSH: FIFO Flush */
#define CRYP_CR_FFLUSH (1 << 14)
/* CRYPEN: Cryptographic processor enable*/
#define CRYP_CR_CRYPEN (1 << 15)
/* --- CRYP_SR values ------------------------------------------------------ */
/* IFEM: Input FIFO empty */
#define CRYP_SR_IFEM (1 << 0)
/* IFNF: Input FIFO not full */
#define CRYP_SR_IFNF (1 << 1)
/* OFNE: Output FIFO not empty */
#define CRYP_SR_OFNE (1 << 2)
/* OFFU: Output FIFO full */
#define CRYP_SR_OFFU (1 << 3)
/* BUSY: Busy bit */
#define CRYP_SR_BUSY (1 << 4)
/* --- CRYP_DMACR values --------------------------------------------------- */
/* DIEN: DMA input enable */
#define CRYP_DMACR_DIEN (1 << 0)
/* DOEN: DMA output enable */
#define CRYP_DMACR_DOEN (1 << 1)
/* --- CRYP_IMSCR values --------------------------------------------------- */
/* INIM: Input FIFO service interrupt mask */
#define CRYP_IMSCR_INIM (1 << 0)
/* OUTIM: Output FIFO service interrupt mask */
#define CRYP_IMSCR_OUTIM (1 << 1)
/* --- CRYP_RISR values ---------------------------------------------------- */
/* INRIS: Input FIFO service raw interrupt status */
#define CRYP_RISR_INRIS (1 << 0)
/* OUTRIS: Output FIFO service raw data */
#define CRYP_RISR_OUTRIS (1 << 0)
/* --- CRYP_MISR values ---------------------------------------------------- */
/* INMIS: Input FIFO service masked interrupt status */
#define CRYP_MISR_INMIS (1 << 0)
/* OUTMIS: Output FIFO service masked interrupt status */
#define CRYP_MISR_OUTMIS (1 << 0)
/**@}*/
/** @defgroup crypto_api_gen API (Generic)
*
* @brief API for the CRYP controller
*
* @ingroup crypto_defines
*/
/**@{*/
enum crypto_mode {
ENCRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB,
ENCRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC,
ENCRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB,
ENCRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC,
ENCRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB,
ENCRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC,
ENCRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR,
DECRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGODIR,
DECRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGODIR,
DECRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB | CRYP_CR_ALGODIR,
DECRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC | CRYP_CR_ALGODIR,
DECRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR,
DECRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR,
DECRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR,/* XOR is same ENC as DEC */
};
enum crypto_keysize {
CRYPTO_KEY_128BIT = 0,
CRYPTO_KEY_192BIT,
CRYPTO_KEY_256BIT,
};
enum crypto_datatype {
CRYPTO_DATA_32BIT = 0,
CRYPTO_DATA_16BIT,
CRYPTO_DATA_8BIT,
CRYPTO_DATA_BIT,
};
BEGIN_DECLS
void crypto_wait_busy(void);
void crypto_set_key(enum crypto_keysize keysize, uint64_t key[]);
void crypto_set_iv(uint64_t iv[]);
void crypto_set_datatype(enum crypto_datatype datatype);
void crypto_set_algorithm(enum crypto_mode mode);
void crypto_start(void);
void crypto_stop(void);
uint32_t crypto_process_block(uint32_t *inp, uint32_t *outp, uint32_t length);
END_DECLS
/**@}*/
/**@}*/
#endif
/** @cond */
#else
#warning "crypto_common_f24.h should not be included explicitly, "
"only via crypto.h"
#endif
/** @endcond */

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/** @addtogroup dac_defines
@author @htmlonly &copy; @endhtmlonly 2012
Felix Held <felix-libopencm3@felixheld.de>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H
The order of header inclusion is important. dac.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_DAC_H
/** @endcond */
#ifndef LIBOPENCM3_DAC_COMMON_ALL_H
#define LIBOPENCM3_DAC_COMMON_ALL_H
#include <libopencm3/cm3/common.h>
/* --- DAC registers ------------------------------------------------------- */
/* DAC control register (DAC_CR) */
#define DAC_CR MMIO32(DAC_BASE + 0x00)
/* DAC software trigger register (DAC_SWTRIGR) */
#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04)
/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08)
/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C)
/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10)
/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14)
/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18)
/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C)
/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20)
/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24)
/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28)
/* DAC channel1 data output register (DAC_DOR1) */
#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C)
/* DAC channel2 data output register (DAC_DOR2) */
#define DAC_DOR2 MMIO32(DAC_BASE + 0x30)
/* --- DAC_CR values ------------------------------------------------------- */
/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
/* doesn't exist in most members of the STM32F1 family */
#define DAC_CR_DMAUDRIE2 (1 << 29)
/* DMAEN2: DAC channel2 DMA enable */
#define DAC_CR_DMAEN2 (1 << 28)
/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
/* DAC_CR_MAMP2_n:
* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
*/
#define DAC_CR_MAMP2_SHIFT 24
/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude
values
@ingroup dac_defines
Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
@{*/
#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
/**@}*/
/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
/* Legend:
* DIS: wave generation disabled
* NOISE: Noise wave generation enabled
* TRI: Triangle wave generation enabled
*
* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
*/
#define DAC_CR_WAVE2_SHIFT 22
#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT)
/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
@ingroup dac_defines
@li NOISE: Noise wave generation enabled
@li TRI: Triangle wave generation enabled
@note: only used if bit TEN2 is set (DAC channel2 trigger enabled)
@{*/
#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
/**@}*/
/* TSEL2[2:0]: DAC channel2 trigger selection */
/* Legend:
*
* T6: Timer 6 TRGO event
* T3: Timer 3 TRGO event
* T8: Timer 8 TRGO event
* T7: Timer 7 TRGO event
* T5: Timer 5 TRGO event
* T15: Timer 15 TRGO event
* T2: Timer 2 TRGO event
* T4: Timer 4 TRGO event
* E9: External line9
* SW: Software trigger
*
* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
* Note: T3 == T8; T5 == T15; not both present on one device
* Note: this is *not* valid for the STM32L1 family
*/
#define DAC_CR_TSEL2_SHIFT 19
/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
@ingroup dac_defines
@li T6: Timer 6 TRGO event
@li T3: Timer 3 TRGO event
@li T8: Timer 8 TRGO event
@li T7: Timer 7 TRGO event
@li T5: Timer 5 TRGO event
@li T15: Timer 15 TRGO event
@li T2: Timer 2 TRGO event
@li T4: Timer 4 TRGO event
@li E9: External line9
@li SW: Software trigger
@note: Refer to the timer documentation for details of the TRGO event.
@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
@note: this is <b>not</b> valid for the STM32L1 family.
@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
@{*/
#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
/**@}*/
/* TEN2: DAC channel2 trigger enable */
#define DAC_CR_TEN2 (1 << 18)
/* BOFF2: DAC channel2 output buffer disable */
#define DAC_CR_BOFF2 (1 << 17)
/* EN2: DAC channel2 enable */
#define DAC_CR_EN2 (1 << 16)
/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
/* doesn't exist in most members of the STM32F1 family */
#define DAC_CR_DMAUDRIE1 (1 << 13)
/* DMAEN1: DAC channel1 DMA enable */
#define DAC_CR_DMAEN1 (1 << 12)
/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
/* DAC_CR_MAMP1_n:
* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
*/
#define DAC_CR_MAMP1_SHIFT 8
/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude
values
@ingroup dac_defines
Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
@{*/
#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
/**@}*/
/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
/* Legend:
* DIS: wave generation disabled
* NOISE: Noise wave generation enabled
* TRI: Triangle wave generation enabled
*
* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
*/
#define DAC_CR_WAVE1_SHIFT 6
#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT)
/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
@ingroup dac_defines
@li DIS: wave generation disabled
@li NOISE: Noise wave generation enabled
@li TRI: Triangle wave generation enabled
@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
@{*/
#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
/**@}*/
/* TSEL1[2:0]: DAC channel1 trigger selection */
/* Legend:
*
* T6: Timer 6 TRGO event
* T3: Timer 3 TRGO event in connectivity line devices
* T8: Timer 8 TRGO event in high-density and XL-density devices
* T7: Timer 7 TRGO event
* T5: Timer 5 TRGO event
* T15: Timer 15 TRGO event
* T2: Timer 2 TRGO event
* T4: Timer 4 TRGO event
* E9: External line9
* SW: Software trigger
*
* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
* Note: T3 == T8; T5 == T15; not both present on one device
* Note: this is *not* valid for the STM32L1 family
*/
#define DAC_CR_TSEL1_SHIFT 3
/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
@ingroup dac_defines
@li T6: Timer 6 TRGO event
@li T3: Timer 3 TRGO event
@li T8: Timer 8 TRGO event
@li T7: Timer 7 TRGO event
@li T5: Timer 5 TRGO event
@li T15: Timer 15 TRGO event
@li T2: Timer 2 TRGO event
@li T4: Timer 4 TRGO event
@li E9: External line 9
@li SW: Software trigger
@note: Refer to the timer documentation for details of the TRGO event.
@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
@note: this is <b>not</b> valid for the STM32L1 family.
@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled).
@{*/
#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
/**@}*/
/* TEN1: DAC channel1 trigger enable */
#define DAC_CR_TEN1 (1 << 2)
/* BOFF1: DAC channel1 output buffer disable */
#define DAC_CR_BOFF1 (1 << 1)
/* EN1: DAC channel1 enable */
#define DAC_CR_EN1 (1 << 0)
/* --- DAC_SWTRIGR values -------------------------------------------------- */
/* SWTRIG2: DAC channel2 software trigger */
#define DAC_SWTRIGR_SWTRIG2 (1 << 1)
/* SWTRIG1: DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
/* --- DAC_DHR12R1 values -------------------------------------------------- */
#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0)
#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0)
/* --- DAC_DHR12L1 values -------------------------------------------------- */
#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4)
#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4)
/* --- DAC_DHR8R1 values --------------------------------------------------- */
#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0)
#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0)
/* --- DAC_DHR12R2 values -------------------------------------------------- */
#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0)
#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0)
/* --- DAC_DHR12L2 values -------------------------------------------------- */
#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4)
#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4)
/* --- DAC_DHR8R2 values --------------------------------------------------- */
#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0)
#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0)
/* --- DAC_DHR12RD values -------------------------------------------------- */
#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16)
#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16)
#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0)
#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0)
/* --- DAC_DHR12LD values -------------------------------------------------- */
#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16)
#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20)
#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0)
#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4)
/* --- DAC_DHR8RD values --------------------------------------------------- */
#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8)
#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8)
#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0)
#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0)
/* --- DAC_DOR1 values ----------------------------------------------------- */
#define DAC_DOR1_DACC1DOR_LSB (1 << 0)
#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0)
/* --- DAC_DOR2 values ----------------------------------------------------- */
#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
/** DAC channel identifier */
typedef enum {
CHANNEL_1, CHANNEL_2, CHANNEL_D
} data_channel;
/** DAC data size (8/12 bits), alignment (right/left) */
typedef enum {
RIGHT8, RIGHT12, LEFT12
} data_align;
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void dac_enable(data_channel dac_channel);
void dac_disable(data_channel dac_channel);
void dac_buffer_enable(data_channel dac_channel);
void dac_buffer_disable(data_channel dac_channel);
void dac_dma_enable(data_channel dac_channel);
void dac_dma_disable(data_channel dac_channel);
void dac_trigger_enable(data_channel dac_channel);
void dac_trigger_disable(data_channel dac_channel);
void dac_set_trigger_source(uint32_t dac_trig_src);
void dac_set_waveform_generation(uint32_t dac_wave_ens);
void dac_disable_waveform_generation(data_channel dac_channel);
void dac_set_waveform_characteristics(uint32_t dac_mamp);
void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format,
data_channel dac_channel);
void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2,
data_align dac_data_format);
void dac_software_trigger(data_channel dac_channel);
END_DECLS
#endif
/** @cond */
#else
#warning "dac_common_all.h should not be included explicitly, only via dac.h"
#endif
/** @endcond */
/**@}*/

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Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/common/dma_common_f24.h Normal file
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@@ -0,0 +1,628 @@
/** @addtogroup dma_defines
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H
The order of header inclusion is important. dma.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_DMA_H
/** @endcond */
#ifndef LIBOPENCM3_DMA_COMMON_F24_H
#define LIBOPENCM3_DMA_COMMON_F24_H
/**@{*/
#include <libopencm3/cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */
/* DMA controller base addresses (for convenience) */
#define DMA1 DMA1_BASE
#define DMA2 DMA2_BASE
/* DMA stream base addresses (for API parameters) */
/** @defgroup dma_st_number DMA Stream Number
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_STREAM0 0
#define DMA_STREAM1 1
#define DMA_STREAM2 2
#define DMA_STREAM3 3
#define DMA_STREAM4 4
#define DMA_STREAM5 5
#define DMA_STREAM6 6
#define DMA_STREAM7 7
/**@}*/
#define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n)))
#define DMA1_STREAM(n) DMA_STREAM(DMA1, n)
#define DMA2_STREAM(n) DMA_STREAM(DMA2, n)
#define DMA1_STREAM0 DMA1_STREAM(0)
#define DMA1_STREAM1 DMA1_STREAM(1)
#define DMA1_STREAM2 DMA1_STREAM(2)
#define DMA1_STREAM3 DMA1_STREAM(3)
#define DMA1_STREAM4 DMA1_STREAM(4)
#define DMA1_STREAM5 DMA1_STREAM(5)
#define DMA1_STREAM6 DMA1_STREAM(6)
#define DMA1_STREAM7 DMA1_STREAM(7)
#define DMA2_STREAM0 DMA2_STREAM(0)
#define DMA2_STREAM1 DMA2_STREAM(1)
#define DMA2_STREAM2 DMA2_STREAM(2)
#define DMA2_STREAM3 DMA2_STREAM(3)
#define DMA2_STREAM4 DMA2_STREAM(4)
#define DMA2_STREAM5 DMA2_STREAM(5)
#define DMA2_STREAM6 DMA2_STREAM(6)
#define DMA2_STREAM7 DMA2_STREAM(7)
/* --- DMA controller registers -------------------------------------------- */
/* DMA low interrupt status register (DMAx_LISR) */
#define DMA_LISR(port) MMIO32(port + 0x00)
#define DMA1_LISR DMA_LISR(DMA1)
#define DMA2_LISR DMA_LISR(DMA2)
/* DMA high interrupt status register (DMAx_HISR) */
#define DMA_HISR(port) MMIO32(port + 0x04)
#define DMA1_HISR DMA_HISR(DMA1)
#define DMA2_HISR DMA_HISR(DMA2)
/* DMA low interrupt flag clear register (DMAx_LIFCR) */
#define DMA_LIFCR(port) MMIO32(port + 0x08)
#define DMA1_LIFCR DMA_LIFCR(DMA1)
#define DMA2_LIFCR DMA_LIFCR(DMA2)
/* DMA high interrupt flag clear register (DMAx_HIFCR) */
#define DMA_HIFCR(port) MMIO32(port + 0x0C)
#define DMA1_HIFCR DMA_HIFCR(DMA1)
#define DMA2_HIFCR DMA_HIFCR(DMA2)
/* --- DMA stream registers ------------------------------------------------ */
/* DMA Stream x configuration register (DMA_SxCR) */
#define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00)
#define DMA1_SCR(n) DMA_SCR(DMA1, n)
#define DMA2_SCR(n) DMA_SCR(DMA2, n)
#define DMA1_S0CR DMA1_SCR(0)
#define DMA1_S1CR DMA1_SCR(1)
#define DMA1_S2CR DMA1_SCR(2)
#define DMA1_S3CR DMA1_SCR(3)
#define DMA1_S4CR DMA1_SCR(4)
#define DMA1_S5CR DMA1_SCR(5)
#define DMA1_S6CR DMA1_SCR(6)
#define DMA1_S7CR DMA1_SCR(7)
#define DMA2_S0CR DMA2_SCR(0)
#define DMA2_S1CR DMA2_SCR(1)
#define DMA2_S2CR DMA2_SCR(2)
#define DMA2_S3CR DMA2_SCR(3)
#define DMA2_S4CR DMA2_SCR(4)
#define DMA2_S5CR DMA2_SCR(5)
#define DMA2_S6CR DMA2_SCR(6)
#define DMA2_S7CR DMA2_SCR(7)
/* DMA Stream x number of data register (DMA_SxNDTR) */
#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04)
#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n)
#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n)
#define DMA1_S0NDTR DMA1_SNDTR(0)
#define DMA1_S1NDTR DMA1_SNDTR(1)
#define DMA1_S2NDTR DMA1_SNDTR(2)
#define DMA1_S3NDTR DMA1_SNDTR(3)
#define DMA1_S4NDTR DMA1_SNDTR(4)
#define DMA1_S5NDTR DMA1_SNDTR(5)
#define DMA1_S6NDTR DMA1_SNDTR(6)
#define DMA1_S7NDTR DMA1_SNDTR(7)
#define DMA2_S0NDTR DMA2_SNDTR(0)
#define DMA2_S1NDTR DMA2_SNDTR(1)
#define DMA2_S2NDTR DMA2_SNDTR(2)
#define DMA2_S3NDTR DMA2_SNDTR(3)
#define DMA2_S4NDTR DMA2_SNDTR(4)
#define DMA2_S5NDTR DMA2_SNDTR(5)
#define DMA2_S6NDTR DMA2_SNDTR(6)
#define DMA2_S7NDTR DMA2_SNDTR(7)
/* DMA Stream x peripheral address register (DMA_SxPAR) */
#define DMA_SPAR(port, n) (*(volatile void **)\
(DMA_STREAM(port, n) + 0x08))
#define DMA1_SPAR(n) DMA_SPAR(DMA1, n)
#define DMA2_SPAR(n) DMA_SPAR(DMA2, n)
#define DMA1_S0PAR DMA1_SPAR(0)
#define DMA1_S1PAR DMA1_SPAR(1)
#define DMA1_S2PAR DMA1_SPAR(2)
#define DMA1_S3PAR DMA1_SPAR(3)
#define DMA1_S4PAR DMA1_SPAR(4)
#define DMA1_S5PAR DMA1_SPAR(5)
#define DMA1_S6PAR DMA1_SPAR(6)
#define DMA1_S7PAR DMA1_SPAR(7)
#define DMA2_S0PAR DMA2_SPAR(0)
#define DMA2_S1PAR DMA2_SPAR(1)
#define DMA2_S2PAR DMA2_SPAR(2)
#define DMA2_S3PAR DMA2_SPAR(3)
#define DMA2_S4PAR DMA2_SPAR(4)
#define DMA2_S5PAR DMA2_SPAR(5)
#define DMA2_S6PAR DMA2_SPAR(6)
#define DMA2_S7PAR DMA2_SPAR(7)
/* DMA Stream x memory address 0 register (DMA_SxM0AR) */
#define DMA_SM0AR(port, n) (*(volatile void **) \
(DMA_STREAM(port, n) + 0x0c))
#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n)
#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n)
#define DMA1_S0M0AR DMA1_SM0AR(0)
#define DMA1_S1M0AR DMA1_SM0AR(1)
#define DMA1_S2M0AR DMA1_SM0AR(2)
#define DMA1_S3M0AR DMA1_SM0AR(3)
#define DMA1_S4M0AR DMA1_SM0AR(4)
#define DMA1_S5M0AR DMA1_SM0AR(5)
#define DMA1_S6M0AR DMA1_SM0AR(6)
#define DMA1_S7M0AR DMA1_SM0AR(7)
#define DMA2_S0M0AR DMA2_SM0AR(0)
#define DMA2_S1M0AR DMA2_SM0AR(1)
#define DMA2_S2M0AR DMA2_SM0AR(2)
#define DMA2_S3M0AR DMA2_SM0AR(3)
#define DMA2_S4M0AR DMA2_SM0AR(4)
#define DMA2_S5M0AR DMA2_SM0AR(5)
#define DMA2_S6M0AR DMA2_SM0AR(6)
#define DMA2_S7M0AR DMA2_SM0AR(7)
/* DMA Stream x memory address 1 register (DMA_SxM1AR) */
#define DMA_SM1AR(port, n) (*(volatile void **)\
(DMA_STREAM(port, n) + 0x10))
#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n)
#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n)
#define DMA1_S0M1AR DMA1_SM1AR(0)
#define DMA1_S1M1AR DMA1_SM1AR(1)
#define DMA1_S2M1AR DMA1_SM1AR(2)
#define DMA1_S3M1AR DMA1_SM1AR(3)
#define DMA1_S4M1AR DMA1_SM1AR(4)
#define DMA1_S5M1AR DMA1_SM1AR(5)
#define DMA1_S6M1AR DMA1_SM1AR(6)
#define DMA1_S7M1AR DMA1_SM1AR(7)
#define DMA2_S0M1AR DMA2_SM1AR(0)
#define DMA2_S1M1AR DMA2_SM1AR(1)
#define DMA2_S2M1AR DMA2_SM1AR(2)
#define DMA2_S3M1AR DMA2_SM1AR(3)
#define DMA2_S4M1AR DMA2_SM1AR(4)
#define DMA2_S5M1AR DMA2_SM1AR(5)
#define DMA2_S6M1AR DMA2_SM1AR(6)
#define DMA2_S7M1AR DMA2_SM1AR(7)
/* DMA Stream x FIFO control register (DMA_SxFCR) */
#define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x14)
#define DMA1_SFCR(n) DMA_SFCR(DMA1, n)
#define DMA2_SFCR(n) DMA_SFCR(DMA2, n)
#define DMA1_S0FCR DMA1_SFCR(0)
#define DMA1_S1FCR DMA1_SFCR(1)
#define DMA1_S2FCR DMA1_SFCR(2)
#define DMA1_S3FCR DMA1_SFCR(3)
#define DMA1_S4FCR DMA1_SFCR(4)
#define DMA1_S5FCR DMA1_SFCR(5)
#define DMA1_S6FCR DMA1_SFCR(6)
#define DMA1_S7FCR DMA1_SFCR(7)
#define DMA2_S0FCR DMA2_SFCR(0)
#define DMA2_S1FCR DMA2_SFCR(1)
#define DMA2_S2FCR DMA2_SFCR(2)
#define DMA2_S3FCR DMA2_SFCR(3)
#define DMA2_S4FCR DMA2_SFCR(4)
#define DMA2_S5FCR DMA2_SFCR(5)
#define DMA2_S6FCR DMA2_SFCR(6)
#define DMA2_S7FCR DMA2_SFCR(7)
/* --- DMA Interrupt Flag offset values ------------------------------------- */
/* For API parameters. These are based on every interrupt flag and flag clear
being at the same relative location */
/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group.
@ingroup dma_defines
@{*/
/** Transfer Complete Interrupt Flag */
#define DMA_TCIF (1 << 5)
/** Half Transfer Interrupt Flag */
#define DMA_HTIF (1 << 4)
/** Transfer Error Interrupt Flag */
#define DMA_TEIF (1 << 3)
/** Direct Mode Error Interrupt Flag */
#define DMA_DMEIF (1 << 2)
/** FIFO Error Interrupt Flag */
#define DMA_FEIF (1 << 0)
/**@}*/
/* Offset within interrupt status register to start of stream interrupt flag
* field
*/
#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1))
#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \
DMA_FEIF)
#define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream))
/* --- DMA_LISR values ----------------------------------------------------- */
#define DMA_LISR_FEIF0 (1 << 0)
#define DMA_LISR_DMEIF0 (1 << 2)
#define DMA_LISR_TEIF0 (1 << 3)
#define DMA_LISR_HTIF0 (1 << 4)
#define DMA_LISR_TCIF0 (1 << 5)
#define DMA_LISR_FEIF1 (1 << 6)
#define DMA_LISR_DMEIF1 (1 << 8)
#define DMA_LISR_TEIF1 (1 << 9)
#define DMA_LISR_HTIF1 (1 << 10)
#define DMA_LISR_TCIF1 (1 << 11)
#define DMA_LISR_FEIF2 (1 << 16)
#define DMA_LISR_DMEIF2 (1 << 18)
#define DMA_LISR_TEIF2 (1 << 19)
#define DMA_LISR_HTIF2 (1 << 20)
#define DMA_LISR_TCIF2 (1 << 21)
#define DMA_LISR_FEIF3 (1 << 22)
#define DMA_LISR_DMEIF3 (1 << 24)
#define DMA_LISR_TEIF3 (1 << 25)
#define DMA_LISR_HTIF3 (1 << 26)
#define DMA_LISR_TCIF3 (1 << 27)
/* --- DMA_HISR values ----------------------------------------------------- */
#define DMA_HISR_FEIF4 (1 << 0)
#define DMA_HISR_DMEIF4 (1 << 2)
#define DMA_HISR_TEIF4 (1 << 3)
#define DMA_HISR_HTIF4 (1 << 4)
#define DMA_HISR_TCIF4 (1 << 5)
#define DMA_HISR_FEIF5 (1 << 6)
#define DMA_HISR_DMEIF5 (1 << 8)
#define DMA_HISR_TEIF5 (1 << 9)
#define DMA_HISR_HTIF5 (1 << 10)
#define DMA_HISR_TCIF5 (1 << 11)
#define DMA_HISR_FEIF6 (1 << 16)
#define DMA_HISR_DMEIF6 (1 << 18)
#define DMA_HISR_TEIF6 (1 << 19)
#define DMA_HISR_HTIF6 (1 << 20)
#define DMA_HISR_TCIF6 (1 << 21)
#define DMA_HISR_FEIF7 (1 << 22)
#define DMA_HISR_DMEIF7 (1 << 24)
#define DMA_HISR_TEIF7 (1 << 25)
#define DMA_HISR_HTIF7 (1 << 26)
#define DMA_HISR_TCIF7 (1 << 27)
/* --- DMA_LIFCR values ----------------------------------------------------- */
#define DMA_LIFCR_CFEIF0 (1 << 0)
#define DMA_LIFCR_CDMEIF0 (1 << 2)
#define DMA_LIFCR_CTEIF0 (1 << 3)
#define DMA_LIFCR_CHTIF0 (1 << 4)
#define DMA_LIFCR_CTCIF0 (1 << 5)
#define DMA_LIFCR_CFEIF1 (1 << 6)
#define DMA_LIFCR_CDMEIF1 (1 << 8)
#define DMA_LIFCR_CTEIF1 (1 << 9)
#define DMA_LIFCR_CHTIF1 (1 << 10)
#define DMA_LIFCR_CTCIF1 (1 << 11)
#define DMA_LIFCR_CFEIF2 (1 << 16)
#define DMA_LIFCR_CDMEIF2 (1 << 18)
#define DMA_LIFCR_CTEIF2 (1 << 19)
#define DMA_LIFCR_CHTIF2 (1 << 20)
#define DMA_LIFCR_CTCIF2 (1 << 21)
#define DMA_LIFCR_CFEIF3 (1 << 22)
#define DMA_LIFCR_CDMEIF3 (1 << 24)
#define DMA_LIFCR_CTEIF3 (1 << 25)
#define DMA_LIFCR_CHTIF3 (1 << 26)
#define DMA_LIFCR_CTCIF3 (1 << 27)
/* --- DMA_HIFCR values ----------------------------------------------------- */
#define DMA_HIFCR_CFEIF4 (1 << 0)
#define DMA_HIFCR_CDMEIF4 (1 << 2)
#define DMA_HIFCR_CTEIF4 (1 << 3)
#define DMA_HIFCR_CHTIF4 (1 << 4)
#define DMA_HIFCR_CTCIF4 (1 << 5)
#define DMA_HIFCR_CFEIF5 (1 << 6)
#define DMA_HIFCR_CDMEIF5 (1 << 8)
#define DMA_HIFCR_CTEIF5 (1 << 9)
#define DMA_HIFCR_CHTIF5 (1 << 10)
#define DMA_HIFCR_CTCIF5 (1 << 11)
#define DMA_HIFCR_CFEIF6 (1 << 16)
#define DMA_HIFCR_CDMEIF6 (1 << 18)
#define DMA_HIFCR_CTEIF6 (1 << 19)
#define DMA_HIFCR_CHTIF6 (1 << 20)
#define DMA_HIFCR_CTCIF6 (1 << 21)
#define DMA_HIFCR_CFEIF7 (1 << 22)
#define DMA_HIFCR_CDMEIF7 (1 << 24)
#define DMA_HIFCR_CTEIF7 (1 << 25)
#define DMA_HIFCR_CHTIF7 (1 << 26)
#define DMA_HIFCR_CTCIF7 (1 << 27)
/* --- DMA_SxCR values ----------------------------------------------------- */
/* EN: Stream enable */
#define DMA_SxCR_EN (1 << 0)
/* DMEIE: Direct Mode error interrupt enable */
#define DMA_SxCR_DMEIE (1 << 1)
/* TEIE: Transfer error interrupt enable */
#define DMA_SxCR_TEIE (1 << 2)
/* HTIE: Half transfer interrupt enable */
#define DMA_SxCR_HTIE (1 << 3)
/* TCIE: Transfer complete interrupt enable */
#define DMA_SxCR_TCIE (1 << 4)
/* PFCTRL: Peripheral Flow Controller */
#define DMA_SxCR_PFCTRL (1 << 5)
/* DIR[7:6]: Data transfer direction */
/** @defgroup dma_st_dir DMA Stream Data transfer direction
@ingroup dma_defines
@{*/
#define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0 << 6)
#define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1 << 6)
#define DMA_SxCR_DIR_MEM_TO_MEM (2 << 6)
/**@}*/
#define DMA_SxCR_DIR_SHIFT 6
#define DMA_SxCR_DIR_MASK (3 << 6)
/* CIRC: Circular mode */
#define DMA_SxCR_CIRC (1 << 8)
/* PINC: Peripheral increment mode */
#define DMA_SxCR_PINC (1 << 9)
/* MINC: Memory increment mode */
#define DMA_SxCR_MINC (1 << 10)
/* PSIZE[12:11]: Peripheral size */
/** @defgroup dma_st_perwidth DMA Stream Peripheral Word Width
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_SxCR_PSIZE_8BIT (0 << 11)
#define DMA_SxCR_PSIZE_16BIT (1 << 11)
#define DMA_SxCR_PSIZE_32BIT (2 << 11)
/**@}*/
#define DMA_SxCR_PSIZE_SHIFT 11
#define DMA_SxCR_PSIZE_MASK (3 << 11)
/* MSIZE[14:13]: Memory size */
/** @defgroup dma_st_memwidth DMA Stream Memory Word Width
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_SxCR_MSIZE_8BIT (0 << 13)
#define DMA_SxCR_MSIZE_16BIT (1 << 13)
#define DMA_SxCR_MSIZE_32BIT (2 << 13)
/**@}*/
#define DMA_SxCR_MSIZE_SHIFT 13
#define DMA_SxCR_MSIZE_MASK (3 << 13)
/* PINCOS: Peripheral increment offset size */
#define DMA_SxCR_PINCOS (1 << 15)
/* PL[17:16]: Stream priority level */
/** @defgroup dma_st_pri DMA Stream Priority Levels
@ingroup dma_defines
@{*/
#define DMA_SxCR_PL_LOW (0 << 16)
#define DMA_SxCR_PL_MEDIUM (1 << 16)
#define DMA_SxCR_PL_HIGH (2 << 16)
#define DMA_SxCR_PL_VERY_HIGH (3 << 16)
/**@}*/
#define DMA_SxCR_PL_SHIFT 16
#define DMA_SxCR_PL_MASK (3 << 16)
/* DBM: Double buffered mode */
#define DMA_SxCR_DBM (1 << 18)
/* CT: Current target (in double buffered mode) */
#define DMA_SxCR_CT (1 << 19)
/* Bit 20 reserved */
/* PBURST[13:12]: Peripheral Burst Configuration */
/** @defgroup dma_pburst DMA Peripheral Burst Length
@ingroup dma_defines
@{*/
#define DMA_SxCR_PBURST_SINGLE (0 << 21)
#define DMA_SxCR_PBURST_INCR4 (1 << 21)
#define DMA_SxCR_PBURST_INCR8 (2 << 21)
#define DMA_SxCR_PBURST_INCR16 (3 << 21)
/**@}*/
#define DMA_SxCR_PBURST_SHIFT 21
#define DMA_SxCR_PBURST_MASK (3 << 21)
/* MBURST[13:12]: Memory Burst Configuration */
/** @defgroup dma_mburst DMA Memory Burst Length
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_SxCR_MBURST_SINGLE (0 << 23)
#define DMA_SxCR_MBURST_INCR4 (1 << 23)
#define DMA_SxCR_MBURST_INCR8 (2 << 23)
#define DMA_SxCR_MBURST_INCR16 (3 << 23)
/**@}*/
#define DMA_SxCR_MBURST_SHIFT 23
#define DMA_SxCR_MBURST_MASK (3 << 23)
/* CHSEL[25:27]: Channel Select */
/** @defgroup dma_ch_sel DMA Channel Select
@ingroup dma_defines
@{*/
#define DMA_SxCR_CHSEL_0 (0 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_1 (1 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_2 (2 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_3 (3 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_4 (4 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_5 (5 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_6 (6 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_7 (7 << DMA_SxCR_CHSEL_SHIFT)
/**@}*/
#define DMA_SxCR_CHSEL_SHIFT 25
#define DMA_SxCR_CHSEL_MASK (7 << 25)
#define DMA_SxCR_CHSEL(n) (n << DMA_SxCR_CHSEL_SHIFT)
/* Reserved [31:28] */
/* --- DMA_SxNDTR values --------------------------------------------------- */
/* DMA_SxNDTR[15:0]: Number of data register. */
/* --- DMA_SxPAR values ---------------------------------------------------- */
/* DMA_SxPAR[31:0]: Peripheral address register. */
/* --- DMA_SxM0AR values --------------------------------------------------- */
/* DMA_SxM0AR[31:0]: Memory 0 address register. */
/* --- DMA_SxM1AR values --------------------------------------------------- */
/* DMA_SxM1AR[31:0]: Memory 1 address register. */
/* --- DMA_SxFCR values ---------------------------------------------------- */
/* FTH[1:0]: FIFO Threshold selection */
/** @defgroup dma_fifo_thresh FIFO Threshold selection
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_SxFCR_FTH_1_4_FULL (0 << 0)
#define DMA_SxFCR_FTH_2_4_FULL (1 << 0)
#define DMA_SxFCR_FTH_3_4_FULL (2 << 0)
#define DMA_SxFCR_FTH_4_4_FULL (3 << 0)
/**@}*/
#define DMA_SxFCR_FTH_SHIFT 0
#define DMA_SxFCR_FTH_MASK (3 << 0)
/* DMDIS: Direct Mode disable */
#define DMA_SxFCR_DMDIS (1 << 2)
/* FS[5:3]: FIFO Status */
/** @defgroup dma_fifo_status FIFO Status
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_SxFCR_FS_LT_1_4_FULL (0 << 0)
#define DMA_SxFCR_FS_LT_2_4_FULL (1 << 0)
#define DMA_SxFCR_FS_LT_3_4_FULL (2 << 0)
#define DMA_SxFCR_FS_LT_4_4_FULL (3 << 0)
#define DMA_SxFCR_FS_FULL (4 << 3)
#define DMA_SxFCR_FS_EMPTY (5 << 3)
/**@}*/
#define DMA_SxFCR_FS_SHIFT 3
#define DMA_SxFCR_FS_MASK (7 << 3)
/* [6]: reserved */
/* FEIE[7]: FIFO error interrupt enable */
#define DMA_SxFCR_FEIE (1 << 7)
/* [31:8]: Reserved */
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
/*
* Note: The F2 and F4 series have a completely new DMA peripheral with
* different configuration options.
*/
void dma_stream_reset(uint32_t dma, uint8_t stream);
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream,
uint32_t interrupts);
bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt);
void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction);
void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio);
void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size);
void dma_set_peripheral_size(uint32_t dma, uint8_t stream,
uint32_t peripheral_size);
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream);
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream);
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream);
void dma_enable_circular_mode(uint32_t dma, uint8_t stream);
void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel);
void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst);
void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst);
void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory);
uint8_t dma_get_target(uint32_t dma, uint8_t stream);
void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream);
void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream);
void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream);
void dma_set_dma_flow_control(uint32_t dma, uint8_t stream);
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream);
uint32_t dma_fifo_status(uint32_t dma, uint8_t stream);
void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_direct_mode(uint32_t dma, uint8_t stream);
void dma_enable_fifo_mode(uint32_t dma, uint8_t stream);
void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold);
void dma_enable_stream(uint32_t dma, uint8_t stream);
void dma_disable_stream(uint32_t dma, uint8_t stream);
void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address);
void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address);
void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address);
void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number);
END_DECLS
/**@}*/
#endif
/** @cond */
#else
#warning "dma_common_f24.h should not be included explicitly, only via dma.h"
#endif
/** @endcond */

427
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/common/dma_common_l1f013.h Normal file
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@@ -0,0 +1,427 @@
/** @addtogroup dma_defines
@author @htmlonly &copy; @endhtmlonly 2010
Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012
Piotr Esden-Tempski <piotr@esden.net>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H
The order of header inclusion is important. dma.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_DMA_H
/** @endcond */
#ifndef LIBOPENCM3_DMA_COMMON_F13_H
#define LIBOPENCM3_DMA_COMMON_F13_H
#include <libopencm3/cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */
/* DMA register base adresses (for convenience) */
#define DMA1 DMA1_BASE
#define DMA2 DMA2_BASE
/* --- DMA registers ------------------------------------------------------- */
/* DMA interrupt status register (DMAx_ISR) */
#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00)
#define DMA1_ISR DMA_ISR(DMA1)
#define DMA2_ISR DMA_ISR(DMA2)
/* DMA interrupt flag clear register (DMAx_IFCR) */
#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04)
#define DMA1_IFCR DMA_IFCR(DMA1)
#define DMA2_IFCR DMA_IFCR(DMA2)
/* DMA channel configuration register (DMAx_CCRy) */
#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \
(0x14 * ((channel) - 1)))
#define DMA1_CCR(channel) DMA_CCR(DMA1, channel)
#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1)
#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2)
#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3)
#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4)
#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5)
#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6)
#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7)
#define DMA2_CCR(channel) DMA_CCR(DMA2, channel)
#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1)
#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2)
#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3)
#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4)
#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5)
/* DMA number of data register (DMAx_CNDTRy) */
#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \
(0x14 * ((channel) - 1)))
#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel)
#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1)
#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2)
#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3)
#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4)
#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5)
#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6)
#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7)
#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel)
#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1)
#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2)
#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3)
#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4)
#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5)
/* DMA peripheral address register (DMAx_CPARy) */
#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \
(0x14 * ((channel) - 1)))
#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel)
#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1)
#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2)
#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3)
#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4)
#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5)
#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6)
#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7)
#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel)
#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1)
#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2)
#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3)
#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4)
#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5)
/* DMA memory address register (DMAx_CMARy) */
#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \
(0x14 * ((channel) - 1)))
#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel)
#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1)
#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2)
#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3)
#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4)
#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5)
#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6)
#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7)
#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel)
#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1)
#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2)
#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3)
#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4)
#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5)
/* --- DMA_ISR values ------------------------------------------------------ */
/* --- DMA Interrupt Flag offset values ------------------------------------- */
/* These are based on every interrupt flag and flag clear being at the same
* relative location
*/
/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag
group.
@ingroup dma_defines
@{*/
/** Transfer Error Interrupt Flag */
#define DMA_TEIF (1 << 3)
/** Half Transfer Interrupt Flag */
#define DMA_HTIF (1 << 2)
/** Transfer Complete Interrupt Flag */
#define DMA_TCIF (1 << 1)
/** Global Interrupt Flag */
#define DMA_GIF (1 << 0)
/**@}*/
/* Offset within interrupt status register to start of channel interrupt flag
* field
*/
#define DMA_FLAG_OFFSET(channel) (4*(channel - 1))
#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \
DMA_GIF)
#define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel))
/* TEIF: Transfer error interrupt flag */
#define DMA_ISR_TEIF_BIT DMA_TEIF
#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)
#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)
#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3)
#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4)
#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5)
#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6)
#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7)
/* HTIF: Half transfer interrupt flag */
#define DMA_ISR_HTIF_BIT DMA_HTIF
#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)
#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)
#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3)
#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4)
#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5)
#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6)
#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7)
/* TCIF: Transfer complete interrupt flag */
#define DMA_ISR_TCIF_BIT DMA_TCIF
#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)
#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)
#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3)
#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4)
#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5)
#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6)
#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7)
/* GIF: Global interrupt flag */
#define DMA_ISR_GIF_BIT DMA_GIF
#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)
#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)
#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3)
#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4)
#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5)
#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6)
#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7)
/* --- DMA_IFCR values ----------------------------------------------------- */
/* CTEIF: Transfer error clear */
#define DMA_IFCR_CTEIF_BIT DMA_TEIF
#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3)
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4)
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5)
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6)
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7)
/* CHTIF: Half transfer clear */
#define DMA_IFCR_CHTIF_BIT DMA_HTIF
#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3)
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4)
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5)
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6)
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7)
/* CTCIF: Transfer complete clear */
#define DMA_IFCR_CTCIF_BIT DMA_TCIF
#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3)
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4)
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5)
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6)
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7)
/* CGIF: Global interrupt clear */
#define DMA_IFCR_CGIF_BIT DMA_GIF
#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3)
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4)
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5)
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6)
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7)
/* Clear interrupts mask */
#define DMA_IFCR_CIF_BIT 0xF
#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)
#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)
#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3)
#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4)
#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5)
#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6)
#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7)
/* --- DMA_CCRx generic values --------------------------------------------- */
/* MEM2MEM: Memory to memory mode */
#define DMA_CCR_MEM2MEM (1 << 14)
/* PL[13:12]: Channel priority level */
/** @defgroup dma_ch_pri DMA Channel Priority Levels
@ingroup dma_defines
@{*/
#define DMA_CCR_PL_LOW (0x0 << 12)
#define DMA_CCR_PL_MEDIUM (0x1 << 12)
#define DMA_CCR_PL_HIGH (0x2 << 12)
#define DMA_CCR_PL_VERY_HIGH (0x3 << 12)
/**@}*/
#define DMA_CCR_PL_MASK (0x3 << 12)
#define DMA_CCR_PL_SHIFT 12
/* MSIZE[11:10]: Memory size */
/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width
@ingroup dma_defines
@{*/
#define DMA_CCR_MSIZE_8BIT (0x0 << 10)
#define DMA_CCR_MSIZE_16BIT (0x1 << 10)
#define DMA_CCR_MSIZE_32BIT (0x2 << 10)
/**@}*/
#define DMA_CCR_MSIZE_MASK (0x3 << 10)
#define DMA_CCR_MSIZE_SHIFT 10
/* PSIZE[9:8]: Peripheral size */
/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width
@ingroup dma_defines
@{*/
#define DMA_CCR_PSIZE_8BIT (0x0 << 8)
#define DMA_CCR_PSIZE_16BIT (0x1 << 8)
#define DMA_CCR_PSIZE_32BIT (0x2 << 8)
/**@}*/
#define DMA_CCR_PSIZE_MASK (0x3 << 8)
#define DMA_CCR_PSIZE_SHIFT 8
/* MINC: Memory increment mode */
#define DMA_CCR_MINC (1 << 7)
/* PINC: Peripheral increment mode */
#define DMA_CCR_PINC (1 << 6)
/* CIRC: Circular mode */
#define DMA_CCR_CIRC (1 << 5)
/* DIR: Data transfer direction */
#define DMA_CCR_DIR (1 << 4)
/* TEIE: Transfer error interrupt enable */
#define DMA_CCR_TEIE (1 << 3)
/* HTIE: Half transfer interrupt enable */
#define DMA_CCR_HTIE (1 << 2)
/* TCIE: Transfer complete interrupt enable */
#define DMA_CCR_TCIE (1 << 1)
/* EN: Channel enable */
#define DMA_CCR_EN (1 << 0)
/* --- DMA_CNDTRx values --------------------------------------------------- */
/* NDT[15:0]: Number of data to transfer */
/* --- DMA_CPARx values ---------------------------------------------------- */
/* PA[31:0]: Peripheral address */
/* --- DMA_CMARx values ---------------------------------------------------- */
/* MA[31:0]: Memory address */
/* --- Generic values ------------------------------------------------------ */
/** @defgroup dma_ch DMA Channel Number
@ingroup dma_defines
@{*/
#define DMA_CHANNEL1 1
#define DMA_CHANNEL2 2
#define DMA_CHANNEL3 3
#define DMA_CHANNEL4 4
#define DMA_CHANNEL5 5
#define DMA_CHANNEL6 6
#define DMA_CHANNEL7 7
/**@}*/
/* --- function prototypes ------------------------------------------------- */
BEGIN_DECLS
void dma_channel_reset(uint32_t dma, uint8_t channel);
void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel,
uint32_t interrupts);
bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupts);
void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel);
void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio);
void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size);
void dma_set_peripheral_size(uint32_t dma, uint8_t channel,
uint32_t peripheral_size);
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_circular_mode(uint32_t dma, uint8_t channel);
void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel);
void dma_set_read_from_memory(uint32_t dma, uint8_t channel);
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel);
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel);
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel);
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel);
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel);
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel);
void dma_enable_channel(uint32_t dma, uint8_t channel);
void dma_disable_channel(uint32_t dma, uint8_t channel);
void dma_set_peripheral_address(uint32_t dma, uint8_t channel,
uint32_t address);
void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address);
void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number);
END_DECLS
#endif
/** @cond */
#else
#warning "dma_common_f13.h should not be included explicitly, only via dma.h"
#endif
/** @endcond */
/**@}*/

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @cond */
#if defined(LIBOPENCM3_EXTI_H)
/** @endcond */
#ifndef LIBOPENCM3_EXTI_COMMON_ALL_H
#define LIBOPENCM3_EXTI_COMMON_ALL_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- EXTI registers ------------------------------------------------------ */
#define EXTI_IMR MMIO32(EXTI_BASE + 0x00)
#define EXTI_EMR MMIO32(EXTI_BASE + 0x04)
#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08)
#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c)
#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10)
#define EXTI_PR MMIO32(EXTI_BASE + 0x14)
/* EXTI number definitions */
#define EXTI0 (1 << 0)
#define EXTI1 (1 << 1)
#define EXTI2 (1 << 2)
#define EXTI3 (1 << 3)
#define EXTI4 (1 << 4)
#define EXTI5 (1 << 5)
#define EXTI6 (1 << 6)
#define EXTI7 (1 << 7)
#define EXTI8 (1 << 8)
#define EXTI9 (1 << 9)
#define EXTI10 (1 << 10)
#define EXTI11 (1 << 11)
#define EXTI12 (1 << 12)
#define EXTI13 (1 << 13)
#define EXTI14 (1 << 14)
#define EXTI15 (1 << 15)
#define EXTI16 (1 << 16)
#define EXTI17 (1 << 17)
#define EXTI18 (1 << 18)
#define EXTI19 (1 << 19)
/* Trigger types */
enum exti_trigger_type {
EXTI_TRIGGER_RISING,
EXTI_TRIGGER_FALLING,
EXTI_TRIGGER_BOTH,
};
BEGIN_DECLS
void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig);
void exti_enable_request(uint32_t extis);
void exti_disable_request(uint32_t extis);
void exti_reset_request(uint32_t extis);
void exti_select_source(uint32_t exti, uint32_t gpioport);
uint32_t exti_get_flag_status(uint32_t exti);
END_DECLS
#endif
/** @cond */
#else
#warning "exti_common_all.h should not be included directly, only via exti.h"
#endif
/** @endcond */

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @cond */
#if defined(LIBOPENCM3_EXTI_H)
/** @endcond */
#ifndef LIBOPENCM3_EXTI_COMMON_F24_H
#define LIBOPENCM3_EXTI_COMMON_F24_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/common/exti_common_all.h>
/* EXTI number definitions */
#define EXTI20 (1 << 20)
#define EXTI21 (1 << 21)
#define EXTI22 (1 << 22)
#endif
/** @cond */
#else
#warning "exti_common_f24.h should not be included directly, only via exti.h"
#endif
/** @endcond */

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* For details see:
* PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming
* September 2011, Doc ID 018520 Rev 1
* https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf
*/
/** @cond */
#ifdef LIBOPENCM3_FLASH_H
/** @endcond */
#ifndef LIBOPENCM3_FLASH_COMMON_F234_H
#define LIBOPENCM3_FLASH_COMMON_F234_H
#include <libopencm3/cm3/common.h>
/* --- FLASH registers ----------------------------------------------------- */
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_ACR_LATENCY_0WS 0x00
#define FLASH_ACR_LATENCY_1WS 0x01
#define FLASH_ACR_LATENCY_2WS 0x02
#define FLASH_ACR_LATENCY_3WS 0x03
#define FLASH_ACR_LATENCY_4WS 0x04
#define FLASH_ACR_LATENCY_5WS 0x05
#define FLASH_ACR_LATENCY_6WS 0x06
#define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
/* --- FLASH_CR values ----------------------------------------------------- */
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void flash_set_ws(uint32_t ws);
void flash_unlock(void);
void flash_lock(void);
void flash_clear_pgperr_flag(void);
void flash_clear_eop_flag(void);
void flash_clear_bsy_flag(void);
void flash_clear_status_flags(void);
void flash_wait_for_last_operation(void);
END_DECLS
#endif
/** @cond */
#else
#warning "flash_common_f234.h should not be included direcitly,"
#warning "only via flash.h"
#endif
/** @endcond */

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* For details see:
* PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming
* September 2011, Doc ID 018520 Rev 1
* https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf
*/
/** @cond */
#ifdef LIBOPENCM3_FLASH_H
/** @endcond */
#ifndef LIBOPENCM3_FLASH_COMMON_F24_H
#define LIBOPENCM3_FLASH_COMMON_F24_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/common/flash_common_f234.h>
/* --- FLASH registers ----------------------------------------------------- */
#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_ACR_DCRST (1 << 12)
#define FLASH_ACR_ICRST (1 << 11)
#define FLASH_ACR_DCE (1 << 10)
#define FLASH_ACR_ICE (1 << 9)
#define FLASH_ACR_PRFTEN (1 << 8)
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_SR_BSY (1 << 16)
#define FLASH_SR_PGSERR (1 << 7)
#define FLASH_SR_PGPERR (1 << 6)
#define FLASH_SR_PGAERR (1 << 5)
#define FLASH_SR_WRPERR (1 << 4)
#define FLASH_SR_OPERR (1 << 1)
#define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_CR_LOCK (1 << 31)
#define FLASH_CR_ERRIE (1 << 25)
#define FLASH_CR_EOPIE (1 << 24)
#define FLASH_CR_STRT (1 << 16)
#define FLASH_CR_MER (1 << 2)
#define FLASH_CR_SER (1 << 1)
#define FLASH_CR_PG (1 << 0)
#define FLASH_CR_SECTOR_0 (0x00 << 3)
#define FLASH_CR_SECTOR_1 (0x01 << 3)
#define FLASH_CR_SECTOR_2 (0x02 << 3)
#define FLASH_CR_SECTOR_3 (0x03 << 3)
#define FLASH_CR_SECTOR_4 (0x04 << 3)
#define FLASH_CR_SECTOR_5 (0x05 << 3)
#define FLASH_CR_SECTOR_6 (0x06 << 3)
#define FLASH_CR_SECTOR_7 (0x07 << 3)
#define FLASH_CR_SECTOR_8 (0x08 << 3)
#define FLASH_CR_SECTOR_9 (0x09 << 3)
#define FLASH_CR_SECTOR_10 (0x0a << 3)
#define FLASH_CR_SECTOR_11 (0x0b << 3)
#define FLASH_CR_PROGRAM_X8 (0x00 << 8)
#define FLASH_CR_PROGRAM_X16 (0x01 << 8)
#define FLASH_CR_PROGRAM_X32 (0x02 << 8)
#define FLASH_CR_PROGRAM_X64 (0x03 << 8)
/* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */
#define FLASH_OPTCR_NRST_STDBY (1 << 7)
#define FLASH_OPTCR_NRST_STOP (1 << 6)
#define FLASH_OPTCR_WDG_SW (1 << 5)
#define FLASH_OPTCR_OPTSTRT (1 << 1)
#define FLASH_OPTCR_OPTLOCK (1 << 0)
#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2)
#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2)
#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2)
#define FLASH_OPTCR_BOR_OFF (0x03 << 2)
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b)
#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f)
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void flash_unlock_option_bytes(void);
void flash_lock_option_bytes(void);
void flash_clear_pgserr_flag(void);
void flash_clear_wrperr_flag(void);
void flash_clear_pgaerr_flag(void);
void flash_dcache_enable(void);
void flash_dcache_disable(void);
void flash_icache_enable(void);
void flash_icache_disable(void);
void flash_prefetch_enable(void);
void flash_prefetch_disable(void);
void flash_dcache_reset(void);
void flash_icache_reset(void);
void flash_erase_all_sectors(uint32_t program_size);
void flash_erase_sector(uint8_t sector, uint32_t program_size);
void flash_program_double_word(uint32_t address, uint64_t data);
void flash_program_word(uint32_t address, uint32_t data);
void flash_program_half_word(uint32_t address, uint16_t data);
void flash_program_byte(uint32_t address, uint8_t data);
void flash_program(uint32_t address, uint8_t *data, uint32_t len);
void flash_program_option_bytes(uint32_t data);
END_DECLS
#endif
/** @cond */
#else
#warning "flash_common_f24.h should not be included direcitly,"
#warning "only via flash.h"
#endif
/** @endcond */

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/** @addtogroup gpio_defines
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H
The order of header inclusion is important. gpio.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined(LIBOPENCM3_GPIO_H) || defined(LIBOPENCM3_GPIO_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_GPIO_COMMON_ALL_H
#define LIBOPENCM3_GPIO_COMMON_ALL_H
/**@{*/
#include <libopencm3/cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */
/* --- GPIO_LCKR values ---------------------------------------------------- */
#define GPIO_LCKK (1 << 16)
/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
/* GPIO number definitions (for convenience) */
/** @defgroup gpio_pin_id GPIO Pin Identifiers
@ingroup gpio_defines
@{*/
#define GPIO0 (1 << 0)
#define GPIO1 (1 << 1)
#define GPIO2 (1 << 2)
#define GPIO3 (1 << 3)
#define GPIO4 (1 << 4)
#define GPIO5 (1 << 5)
#define GPIO6 (1 << 6)
#define GPIO7 (1 << 7)
#define GPIO8 (1 << 8)
#define GPIO9 (1 << 9)
#define GPIO10 (1 << 10)
#define GPIO11 (1 << 11)
#define GPIO12 (1 << 12)
#define GPIO13 (1 << 13)
#define GPIO14 (1 << 14)
#define GPIO15 (1 << 15)
#define GPIO_ALL 0xffff
/**@}*/
BEGIN_DECLS
void gpio_set(uint32_t gpioport, uint16_t gpios);
void gpio_clear(uint32_t gpioport, uint16_t gpios);
uint16_t gpio_get(uint32_t gpioport, uint16_t gpios);
void gpio_toggle(uint32_t gpioport, uint16_t gpios);
uint16_t gpio_port_read(uint32_t gpioport);
void gpio_port_write(uint32_t gpioport, uint16_t data);
void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios);
END_DECLS
/**@}*/
#endif
/** @cond */
#else
#warning "gpio_common_all.h should not be included explicitly, only via gpio.h"
#endif
/** @endcond */

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/** @addtogroup gpio_defines
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H
The order of header inclusion is important. gpio.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_GPIO_H
/** @endcond */
#ifndef LIBOPENCM3_GPIO_COMMON_F234_H
#define LIBOPENCM3_GPIO_COMMON_F234_H
/**@{*/
#include <libopencm3/stm32/common/gpio_common_all.h>
/* GPIO port base addresses (for convenience) */
/** @defgroup gpio_port_id GPIO Port IDs
@ingroup gpio_defines
@{*/
#define GPIOA GPIO_PORT_A_BASE
#define GPIOB GPIO_PORT_B_BASE
#define GPIOC GPIO_PORT_C_BASE
#define GPIOD GPIO_PORT_D_BASE
#define GPIOE GPIO_PORT_E_BASE
#define GPIOF GPIO_PORT_F_BASE
/**@}*/
/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */
/* Port mode register (GPIOx_MODER) */
#define GPIO_MODER(port) MMIO32(port + 0x00)
#define GPIOA_MODER GPIO_MODER(GPIOA)
#define GPIOB_MODER GPIO_MODER(GPIOB)
#define GPIOC_MODER GPIO_MODER(GPIOC)
#define GPIOD_MODER GPIO_MODER(GPIOD)
#define GPIOE_MODER GPIO_MODER(GPIOE)
#define GPIOF_MODER GPIO_MODER(GPIOF)
/* Port output type register (GPIOx_OTYPER) */
#define GPIO_OTYPER(port) MMIO32(port + 0x04)
#define GPIOA_OTYPER GPIO_OTYPER(GPIOA)
#define GPIOB_OTYPER GPIO_OTYPER(GPIOB)
#define GPIOC_OTYPER GPIO_OTYPER(GPIOC)
#define GPIOD_OTYPER GPIO_OTYPER(GPIOD)
#define GPIOE_OTYPER GPIO_OTYPER(GPIOE)
#define GPIOF_OTYPER GPIO_OTYPER(GPIOF)
/* Port output speed register (GPIOx_OSPEEDR) */
#define GPIO_OSPEEDR(port) MMIO32(port + 0x08)
#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA)
#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB)
#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC)
#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD)
#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE)
#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF)
/* Port pull-up/pull-down register (GPIOx_PUPDR) */
#define GPIO_PUPDR(port) MMIO32(port + 0x0c)
#define GPIOA_PUPDR GPIO_PUPDR(GPIOA)
#define GPIOB_PUPDR GPIO_PUPDR(GPIOB)
#define GPIOC_PUPDR GPIO_PUPDR(GPIOC)
#define GPIOD_PUPDR GPIO_PUPDR(GPIOD)
#define GPIOE_PUPDR GPIO_PUPDR(GPIOE)
#define GPIOF_PUPDR GPIO_PUPDR(GPIOF)
/* Port input data register (GPIOx_IDR) */
#define GPIO_IDR(port) MMIO32(port + 0x10)
#define GPIOA_IDR GPIO_IDR(GPIOA)
#define GPIOB_IDR GPIO_IDR(GPIOB)
#define GPIOC_IDR GPIO_IDR(GPIOC)
#define GPIOD_IDR GPIO_IDR(GPIOD)
#define GPIOE_IDR GPIO_IDR(GPIOE)
#define GPIOF_IDR GPIO_IDR(GPIOF)
/* Port output data register (GPIOx_ODR) */
#define GPIO_ODR(port) MMIO32(port + 0x14)
#define GPIOA_ODR GPIO_ODR(GPIOA)
#define GPIOB_ODR GPIO_ODR(GPIOB)
#define GPIOC_ODR GPIO_ODR(GPIOC)
#define GPIOD_ODR GPIO_ODR(GPIOD)
#define GPIOE_ODR GPIO_ODR(GPIOE)
#define GPIOF_ODR GPIO_ODR(GPIOF)
/* Port bit set/reset register (GPIOx_BSRR) */
#define GPIO_BSRR(port) MMIO32(port + 0x18)
#define GPIOA_BSRR GPIO_BSRR(GPIOA)
#define GPIOB_BSRR GPIO_BSRR(GPIOB)
#define GPIOC_BSRR GPIO_BSRR(GPIOC)
#define GPIOD_BSRR GPIO_BSRR(GPIOD)
#define GPIOE_BSRR GPIO_BSRR(GPIOE)
#define GPIOF_BSRR GPIO_BSRR(GPIOF)
/* Port configuration lock register (GPIOx_LCKR) */
#define GPIO_LCKR(port) MMIO32(port + 0x1c)
#define GPIOA_LCKR GPIO_LCKR(GPIOA)
#define GPIOB_LCKR GPIO_LCKR(GPIOB)
#define GPIOC_LCKR GPIO_LCKR(GPIOC)
#define GPIOD_LCKR GPIO_LCKR(GPIOD)
#define GPIOE_LCKR GPIO_LCKR(GPIOE)
#define GPIOF_LCKR GPIO_LCKR(GPIOF)
/* Alternate function low register (GPIOx_AFRL) */
#define GPIO_AFRL(port) MMIO32(port + 0x20)
#define GPIOA_AFRL GPIO_AFRL(GPIOA)
#define GPIOB_AFRL GPIO_AFRL(GPIOB)
#define GPIOC_AFRL GPIO_AFRL(GPIOC)
#define GPIOD_AFRL GPIO_AFRL(GPIOD)
#define GPIOE_AFRL GPIO_AFRL(GPIOE)
#define GPIOF_AFRL GPIO_AFRL(GPIOF)
/* Alternate function high register (GPIOx_AFRH) */
#define GPIO_AFRH(port) MMIO32(port + 0x24)
#define GPIOA_AFRH GPIO_AFRH(GPIOA)
#define GPIOB_AFRH GPIO_AFRH(GPIOB)
#define GPIOC_AFRH GPIO_AFRH(GPIOC)
#define GPIOD_AFRH GPIO_AFRH(GPIOD)
#define GPIOE_AFRH GPIO_AFRH(GPIOE)
#define GPIOF_AFRH GPIO_AFRH(GPIOF)
/* --- GPIOx_MODER values -------------------------------------------------- */
#define GPIO_MODE(n, mode) (mode << (2 * (n)))
#define GPIO_MODE_MASK(n) (0x3 << (2 * (n)))
/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode
@ingroup gpio_defines
@{*/
#define GPIO_MODE_INPUT 0x0
#define GPIO_MODE_OUTPUT 0x1
#define GPIO_MODE_AF 0x2
#define GPIO_MODE_ANALOG 0x3
/**@}*/
/* --- GPIOx_OTYPER values ------------------------------------------------- */
/** @defgroup gpio_output_type GPIO Output Pin Driver Type
@ingroup gpio_defines
@list Push Pull
@list Open Drain
@{*/
#define GPIO_OTYPE_PP 0x0
#define GPIO_OTYPE_OD 0x1
/**@}*/
/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
#define GPIO_OSPEED(n, speed) (speed << (2 * (n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n)))
/** @defgroup gpio_speed GPIO Output Pin Speed
@ingroup gpio_defines
@{*/
#define GPIO_OSPEED_2MHZ 0x0
#define GPIO_OSPEED_25MHZ 0x1
#define GPIO_OSPEED_50MHZ 0x2
#define GPIO_OSPEED_100MHZ 0x3
/**@}*/
/* --- GPIOx_PUPDR values -------------------------------------------------- */
#define GPIO_PUPD(n, pupd) (pupd << (2 * (n)))
#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n)))
/** @defgroup gpio_pup GPIO Output Pin Pullup
@ingroup gpio_defines
@{*/
#define GPIO_PUPD_NONE 0x0
#define GPIO_PUPD_PULLUP 0x1
#define GPIO_PUPD_PULLDOWN 0x2
/**@}*/
/* --- GPIOx_IDR values ---------------------------------------------------- */
/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
/* --- GPIOx_ODR values ---------------------------------------------------- */
/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
/* --- GPIOx_BSRR values --------------------------------------------------- */
/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
/* --- GPIOx_LCKR values --------------------------------------------------- */
#define GPIO_LCKK (1 << 16)
/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
/* --- GPIOx_AFRL/H values ------------------------------------------------- */
/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
/* See datasheet table 6 (pg. 48) for alternate function mappings. */
#define GPIO_AFR(n, af) (af << ((n) * 4))
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
/** @defgroup gpio_af_num Alternate Function Pin Selection
@ingroup gpio_defines
@{*/
#define GPIO_AF0 0x0
#define GPIO_AF1 0x1
#define GPIO_AF2 0x2
#define GPIO_AF3 0x3
#define GPIO_AF4 0x4
#define GPIO_AF5 0x5
#define GPIO_AF6 0x6
#define GPIO_AF7 0x7
#define GPIO_AF8 0x8
#define GPIO_AF9 0x9
#define GPIO_AF10 0xa
#define GPIO_AF11 0xb
#define GPIO_AF12 0xc
#define GPIO_AF13 0xd
#define GPIO_AF14 0xe
#define GPIO_AF15 0xf
/**@}*/
/* Note: EXTI source selection is now in the SYSCFG peripheral. */
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
/*
* Note: The F2 and F4 series have a completely new GPIO peripheral with
* different configuration options. Here we implement a different API partly to
* more closely match the peripheral capabilities and also to deliberately
* break compatibility with old F1 code so there is no confusion with similar
* sounding functions that have very different functionality.
*/
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down,
uint16_t gpios);
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed,
uint16_t gpios);
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios);
END_DECLS
/**@}*/
#endif
/** @cond */
#else
#warning "gpio_common_f234.h should not be included explicitly, only via gpio.h"
#endif
/** @endcond */

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/** @addtogroup gpio_defines
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H
The order of header inclusion is important. gpio.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_GPIO_H
/** @endcond */
#ifndef LIBOPENCM3_GPIO_COMMON_F24_H
#define LIBOPENCM3_GPIO_COMMON_F24_H
/**@{*/
#include <libopencm3/stm32/common/gpio_common_all.h>
#include <libopencm3/stm32/common/gpio_common_f234.h>
/* GPIO port base addresses (for convenience) */
/** @defgroup gpio_port_id GPIO Port IDs
@ingroup gpio_defines
@{*/
#define GPIOG GPIO_PORT_G_BASE
#define GPIOH GPIO_PORT_H_BASE
#define GPIOI GPIO_PORT_I_BASE
/**@}*/
/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */
/* Port mode register (GPIOx_MODER) */
#define GPIOG_MODER GPIO_MODER(GPIOG)
#define GPIOH_MODER GPIO_MODER(GPIOH)
#define GPIOI_MODER GPIO_MODER(GPIOI)
/* Port output type register (GPIOx_OTYPER) */
#define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
#define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
#define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
/* Port output speed register (GPIOx_OSPEEDR) */
#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
/* Port pull-up/pull-down register (GPIOx_PUPDR) */
#define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
#define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
#define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
/* Port input data register (GPIOx_IDR) */
#define GPIOG_IDR GPIO_IDR(GPIOG)
#define GPIOH_IDR GPIO_IDR(GPIOH)
#define GPIOI_IDR GPIO_IDR(GPIOI)
/* Port output data register (GPIOx_ODR) */
#define GPIOG_ODR GPIO_ODR(GPIOG)
#define GPIOH_ODR GPIO_ODR(GPIOH)
#define GPIOI_ODR GPIO_ODR(GPIOI)
/* Port bit set/reset register (GPIOx_BSRR) */
#define GPIOG_BSRR GPIO_BSRR(GPIOG)
#define GPIOH_BSRR GPIO_BSRR(GPIOH)
#define GPIOI_BSRR GPIO_BSRR(GPIOI)
/* Port configuration lock register (GPIOx_LCKR) */
#define GPIOG_LCKR GPIO_LCKR(GPIOG)
#define GPIOH_LCKR GPIO_LCKR(GPIOH)
#define GPIOI_LCKR GPIO_LCKR(GPIOI)
/* Alternate function low register (GPIOx_AFRL) */
#define GPIOG_AFRL GPIO_AFRL(GPIOG)
#define GPIOH_AFRL GPIO_AFRL(GPIOH)
#define GPIOI_AFRL GPIO_AFRL(GPIOI)
/* Alternate function high register (GPIOx_AFRH) */
#define GPIOG_AFRH GPIO_AFRH(GPIOG)
#define GPIOH_AFRH GPIO_AFRH(GPIOH)
#define GPIOI_AFRH GPIO_AFRH(GPIOI)
#endif
/** @cond */
#else
#warning "gpio_common_f24.h should not be included explicitly, only via gpio.h"
#endif
/** @endcond */

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/** @addtogroup hash_defines
@author @htmlonly &copy; @endhtmlonly 2013
Mikhail Avkhimenia <mikhail@avkhimenia.net>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Mikhail Avkhimenia <mikhail@avkhimenia.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifdef LIBOPENCM3_HASH_H
#ifndef LIBOPENCM3_HASH_COMMON_F24_H
#define LIBOPENCM3_HASH_COMMON_F24_H
#include <libopencm3/cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */
/****************************************************************************/
/** @defgroup hash_reg_base HASH register base addresses
@ingroup STM32F_hash_defines
@{*/
#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)
#define HASH HASH_BASE
/**@}*/
/* --- HASH registers ------------------------------------------------------ */
/* HASH control register (HASH_CR) */
#define HASH_CR MMIO32(HASH + 0x00)
/* HASH data input register (HASH_DIR) */
#define HASH_DIN MMIO32(HASH + 0x04)
/* HASH start register (HASH_STR) */
#define HASH_STR MMIO32(HASH + 0x08)
/* HASH digest registers (HASH_HR[5]) */
#define HASH_HR (&MMIO32(HASH + 0x0C)) /* x5 */
/* HASH interrupt enable register (HASH_IMR) */
#define HASH_IMR MMIO32(HASH + 0x20)
/* HASH status register (HASH_SR) */
#define HASH_SR MMIO32(HASH + 0x28)
/* HASH context swap registers (HASH_CSR[51]) */
#define HASH_CSR (&MMIO32(HASH + 0xF8)) /* x51 */
/* --- HASH_CR values ------------------------------------------------------ */
/* INIT: Initialize message digest calculation */
#define HASH_CR_INIT (1 << 2)
/* DMAE: DMA enable */
#define HASH_CR_DMAE (1 << 3)
/* DATATYPE: Data type selection */
/****************************************************************************/
/** @defgroup hash_data_type HASH Data Type
@ingroup hash_defines
@{*/
#define HASH_DATA_32BIT (0 << 4)
#define HASH_DATA_16BIT (1 << 4)
#define HASH_DATA_8BIT (2 << 4)
#define HASH_DATA_BITSTRING (3 << 4)
/**@}*/
#define HASH_CR_DATATYPE (3 << 4)
/* MODE: Mode selection */
/****************************************************************************/
/** @defgroup hash_mode HASH Mode
@ingroup hash_defines
@{*/
#define HASH_MODE_HASH (0 << 6)
#define HASH_MODE_HMAC (1 << 6)
/**@}*/
#define HASH_CR_MODE (1 << 6)
/* ALGO: Algorithm selection */
/****************************************************************************/
/** @defgroup hash_algorithm HASH Algorithm
@ingroup hash_defines
@{*/
#define HASH_ALGO_SHA1 (0 << 7)
#define HASH_ALGO_MD5 (1 << 7)
/**@}*/
#define HASH_CR_ALGO (1 << 7)
/* NBW: Number of words already pushed */
#define HASH_CR_NBW (15 << 8)
/* DINNE: DIN(Data input register) not empty */
#define HASH_CR_DINNE (1 << 12)
/* LKEY: Long key selection */
/****************************************************************************/
/** @defgroup hash_key_length HASH Key length
@ingroup hash_defines
@{*/
#define HASH_KEY_SHORT (0 << 16)
#define HASH_KEY_LONG (1 << 16)
/**@}*/
#define HASH_CR_LKEY (1 << 16)
/* --- HASH_STR values ----------------------------------------------------- */
/* NBLW: Number of valid bits in the last word of the message in the bit string
*/
#define HASH_STR_NBW (31 << 0)
/* DCAL: Digest calculation */
#define HASH_STR_DCAL (1 << 8)
/* --- HASH_IMR values ----------------------------------------------------- */
/* DINIE: Data input interrupt enable */
#define HASH_IMR_DINIE (1 << 0)
/* DCIE: Digest calculation completion interrupt enable */
#define HASH_IMR_DCIE (1 << 1)
/* --- HASH_SR values ------------------------------------------------------ */
/* DINIS: Data input interrupt status */
#define HASH_SR_DINIS (1 << 0)
/* DCIS: Digest calculation completion interrupt status */
#define HASH_SR_DCIS (1 << 1)
/* DMAS: DMA Status */
#define HASH_SR_DMAS (1 << 2)
/* BUSY: Busy bit */
#define HASH_SR_BUSY (1 << 3)
/* --- HASH function prototypes -------------------------------------------- */
BEGIN_DECLS
void hash_set_mode(uint8_t mode);
void hash_set_algorithm(uint8_t algorithm);
void hash_set_data_type(uint8_t datatype);
void hash_set_key_length(uint8_t keylength);
void hash_set_last_word_valid_bits(uint8_t validbits);
void hash_init(void);
void hash_add_data(uint32_t data);
void hash_digest(void);
void hash_get_result(uint32_t *data);
END_DECLS
/**@}*/
#endif
#else
#warning "hash_common_f24.h should not be included explicitly, only via hash.h"
#endif

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/** @addtogroup i2c_defines
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H
The order of header inclusion is important. i2c.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined(LIBOPENCM3_I2C_H) || defined(LIBOPENCM3_I2C_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_I2C_COMMON_ALL_H
#define LIBOPENCM3_I2C_COMMON_ALL_H
#include <libopencm3/cm3/common.h>
/**@{*/
/* --- Convenience macros -------------------------------------------------- */
/* I2C register base addresses (for convenience) */
/****************************************************************************/
/** @defgroup i2c_reg_base I2C register base address
@ingroup i2c_defines
@{*/
#define I2C1 I2C1_BASE
#define I2C2 I2C2_BASE
/**@}*/
/* --- I2C registers ------------------------------------------------------- */
/* Control register 1 (I2Cx_CR1) */
#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
#define I2C1_CR1 I2C_CR1(I2C1)
#define I2C2_CR1 I2C_CR1(I2C2)
/* Control register 2 (I2Cx_CR2) */
#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
#define I2C1_CR2 I2C_CR2(I2C1)
#define I2C2_CR2 I2C_CR2(I2C2)
/* Own address register 1 (I2Cx_OAR1) */
#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
#define I2C1_OAR1 I2C_OAR1(I2C1)
#define I2C2_OAR1 I2C_OAR1(I2C2)
/* Own address register 2 (I2Cx_OAR2) */
#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
#define I2C1_OAR2 I2C_OAR2(I2C1)
#define I2C2_OAR2 I2C_OAR2(I2C2)
/* Data register (I2Cx_DR) */
#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10)
#define I2C1_DR I2C_DR(I2C1)
#define I2C2_DR I2C_DR(I2C2)
/* Status register 1 (I2Cx_SR1) */
#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14)
#define I2C1_SR1 I2C_SR1(I2C1)
#define I2C2_SR1 I2C_SR1(I2C2)
/* Status register 2 (I2Cx_SR2) */
#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18)
#define I2C1_SR2 I2C_SR2(I2C1)
#define I2C2_SR2 I2C_SR2(I2C2)
/* Clock control register (I2Cx_CCR) */
#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c)
#define I2C1_CCR I2C_CCR(I2C1)
#define I2C2_CCR I2C_CCR(I2C2)
/* TRISE register (I2Cx_CCR) */
#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20)
#define I2C1_TRISE I2C_TRISE(I2C1)
#define I2C2_TRISE I2C_TRISE(I2C2)
/* --- I2Cx_CR1 values ----------------------------------------------------- */
/* SWRST: Software reset */
#define I2C_CR1_SWRST (1 << 15)
/* Note: Bit 14 is reserved, and forced to 0 by hardware. */
/* ALERT: SMBus alert */
#define I2C_CR1_ALERT (1 << 13)
/* PEC: Packet error checking */
#define I2C_CR1_PEC (1 << 12)
/* POS: Acknowledge / PEC position */
#define I2C_CR1_POS (1 << 11)
/* ACK: Acknowledge enable */
#define I2C_CR1_ACK (1 << 10)
/* STOP: STOP generation */
#define I2C_CR1_STOP (1 << 9)
/* START: START generation */
#define I2C_CR1_START (1 << 8)
/* NOSTRETCH: Clock stretching disable (slave mode) */
#define I2C_CR1_NOSTRETCH (1 << 7)
/* ENGC: General call enable */
#define I2C_CR1_ENGC (1 << 6)
/* ENPEC: Enable PEC */
#define I2C_CR1_ENPEC (1 << 5)
/* ENARP: ARP enable */
#define I2C_CR1_ENARP (1 << 4)
/* SMBTYPE: SMBus type */
#define I2C_CR1_SMBTYPE (1 << 3)
/* Note: Bit 2 is reserved, and forced to 0 by hardware. */
/* SMBUS: SMBus mode */
#define I2C_CR1_SMBUS (1 << 1)
/* PE: Peripheral enable */
#define I2C_CR1_PE (1 << 0)
/* --- I2Cx_CR2 values ----------------------------------------------------- */
/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */
/* LAST: DMA last transfer */
#define I2C_CR2_LAST (1 << 12)
/* DMAEN: DMA requests enable */
#define I2C_CR2_DMAEN (1 << 11)
/* ITBUFEN: Buffer interrupt enable */
#define I2C_CR2_ITBUFEN (1 << 10)
/* ITEVTEN: Event interrupt enable */
#define I2C_CR2_ITEVTEN (1 << 9)
/* ITERREN: Error interrupt enable */
#define I2C_CR2_ITERREN (1 << 8)
/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
/****************************************************************************/
/** @defgroup i2c_clock I2C clock frequency settings
@ingroup i2c_defines
@{*/
#define I2C_CR2_FREQ_2MHZ 0x02
#define I2C_CR2_FREQ_3MHZ 0x03
#define I2C_CR2_FREQ_4MHZ 0x04
#define I2C_CR2_FREQ_5MHZ 0x05
#define I2C_CR2_FREQ_6MHZ 0x06
#define I2C_CR2_FREQ_7MHZ 0x07
#define I2C_CR2_FREQ_8MHZ 0x08
#define I2C_CR2_FREQ_9MHZ 0x09
#define I2C_CR2_FREQ_10MHZ 0x0a
#define I2C_CR2_FREQ_11MHZ 0x0b
#define I2C_CR2_FREQ_12MHZ 0x0c
#define I2C_CR2_FREQ_13MHZ 0x0d
#define I2C_CR2_FREQ_14MHZ 0x0e
#define I2C_CR2_FREQ_15MHZ 0x0f
#define I2C_CR2_FREQ_16MHZ 0x10
#define I2C_CR2_FREQ_17MHZ 0x11
#define I2C_CR2_FREQ_18MHZ 0x12
#define I2C_CR2_FREQ_19MHZ 0x13
#define I2C_CR2_FREQ_20MHZ 0x14
#define I2C_CR2_FREQ_21MHZ 0x15
#define I2C_CR2_FREQ_22MHZ 0x16
#define I2C_CR2_FREQ_23MHZ 0x17
#define I2C_CR2_FREQ_24MHZ 0x18
#define I2C_CR2_FREQ_25MHZ 0x19
#define I2C_CR2_FREQ_26MHZ 0x1a
#define I2C_CR2_FREQ_27MHZ 0x1b
#define I2C_CR2_FREQ_28MHZ 0x1c
#define I2C_CR2_FREQ_29MHZ 0x1d
#define I2C_CR2_FREQ_30MHZ 0x1e
#define I2C_CR2_FREQ_31MHZ 0x1f
#define I2C_CR2_FREQ_32MHZ 0x20
#define I2C_CR2_FREQ_33MHZ 0x21
#define I2C_CR2_FREQ_34MHZ 0x22
#define I2C_CR2_FREQ_35MHZ 0x23
#define I2C_CR2_FREQ_36MHZ 0x24
/**@}*/
/* --- I2Cx_OAR1 values ---------------------------------------------------- */
/* ADDMODE: Addressing mode (slave mode) */
#define I2C_OAR1_ADDMODE (1 << 15)
#define I2C_OAR1_ADDMODE_7BIT 0
#define I2C_OAR1_ADDMODE_10BIT 1
/* Note: Bit 14 should always be kept at 1 by software! */
/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */
/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */
/* --- I2Cx_OAR2 values ---------------------------------------------------- */
/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */
/* ENDUAL: Dual addressing mode enable */
#define I2C_OAR2_ENDUAL (1 << 0)
/* --- I2Cx_DR values ------------------------------------------------------ */
/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
/* DR[7:0] 8-bit data register */
/* --- I2Cx_SR1 values ----------------------------------------------------- */
/* SMBALERT: SMBus alert */
#define I2C_SR1_SMBALERT (1 << 15)
/* TIMEOUT: Timeout or Tlow Error */
#define I2C_SR1_TIMEOUT (1 << 14)
/* Note: Bit 13 is reserved, and forced to 0 by hardware. */
/* PECERR: PEC Error in reception */
#define I2C_SR1_PECERR (1 << 12)
/* OVR: Overrun/Underrun */
#define I2C_SR1_OVR (1 << 11)
/* AF: Acknowledge failure */
#define I2C_SR1_AF (1 << 10)
/* ARLO: Arbitration lost (master mode) */
#define I2C_SR1_ARLO (1 << 9)
/* BERR: Bus error */
#define I2C_SR1_BERR (1 << 8)
/* TxE: Data register empty (transmitters) */
#define I2C_SR1_TxE (1 << 7)
/* RxNE: Data register not empty (receivers) */
#define I2C_SR1_RxNE (1 << 6)
/* Note: Bit 5 is reserved, and forced to 0 by hardware. */
/* STOPF: STOP detection (slave mode) */
#define I2C_SR1_STOPF (1 << 4)
/* ADD10: 10-bit header sent (master mode) */
#define I2C_SR1_ADD10 (1 << 3)
/* BTF: Byte transfer finished */
#define I2C_SR1_BTF (1 << 2)
/* ADDR: Address sent (master mode) / address matched (slave mode) */
#define I2C_SR1_ADDR (1 << 1)
/* SB: Start bit (master mode) */
#define I2C_SR1_SB (1 << 0)
/* --- I2Cx_SR2 values ----------------------------------------------------- */
/* Bits [15:8]: PEC[7:0]: Packet error checking register */
/* DUALF: Dual flag (slave mode) */
#define I2C_SR2_DUALF (1 << 7)
/* SMBHOST: SMBus host header (slave mode) */
#define I2C_SR2_SMBHOST (1 << 6)
/* SMBDEFAULT: SMBus device default address (slave mode) */
#define I2C_SR2_SMBDEFAULT (1 << 5)
/* GENCALL: General call address (slave mode) */
#define I2C_SR2_GENCALL (1 << 4)
/* Note: Bit 3 is reserved, and forced to 0 by hardware. */
/* TRA: Transmitter / receiver */
#define I2C_SR2_TRA (1 << 2)
/* BUSY: Bus busy */
#define I2C_SR2_BUSY (1 << 1)
/* MSL: Master / slave */
#define I2C_SR2_MSL (1 << 0)
/* --- I2Cx_CCR values ----------------------------------------------------- */
/* F/S: I2C Master mode selection (fast / standard) */
#define I2C_CCR_FS (1 << 15)
/* DUTY: Fast Mode Duty Cycle */
/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles
@ingroup i2c_defines
@{*/
#define I2C_CCR_DUTY (1 << 14)
#define I2C_CCR_DUTY_DIV2 0
#define I2C_CCR_DUTY_16_DIV_9 1
/**@}*/
/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
/*
* Bits [11:0]:
* CCR[11:0]: Clock control register in Fast/Standard mode (master mode)
*/
/* --- I2Cx_TRISE values --------------------------------------------------- */
/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
/*
* Bits [5:0]:
* TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
*/
/* --- I2C constant definitions -------------------------------------------- */
/****************************************************************************/
/** @defgroup i2c_rw I2C Read/Write bit
@ingroup i2c_defines
@{*/
#define I2C_WRITE 0
#define I2C_READ 1
/**@}*/
/* --- I2C function prototypes---------------------------------------------- */
BEGIN_DECLS
void i2c_reset(uint32_t i2c);
void i2c_peripheral_enable(uint32_t i2c);
void i2c_peripheral_disable(uint32_t i2c);
void i2c_send_start(uint32_t i2c);
void i2c_send_stop(uint32_t i2c);
void i2c_clear_stop(uint32_t i2c);
void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave);
void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave);
void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq);
void i2c_send_data(uint32_t i2c, uint8_t data);
void i2c_set_fast_mode(uint32_t i2c);
void i2c_set_standard_mode(uint32_t i2c);
void i2c_set_ccr(uint32_t i2c, uint16_t freq);
void i2c_set_trise(uint32_t i2c, uint16_t trise);
void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite);
uint8_t i2c_get_data(uint32_t i2c);
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt);
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt);
void i2c_enable_ack(uint32_t i2c);
void i2c_disable_ack(uint32_t i2c);
void i2c_nack_next(uint32_t i2c);
void i2c_nack_current(uint32_t i2c);
void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle);
void i2c_enable_dma(uint32_t i2c);
void i2c_disable_dma(uint32_t i2c);
void i2c_set_dma_last_transfer(uint32_t i2c);
void i2c_clear_dma_last_transfer(uint32_t i2c);
END_DECLS
#endif
/** @cond */
#else
#warning "i2c_common_all.h should not be included explicitly, only via i2c.h"
#endif
/** @endcond */
/**@}*/

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/** @addtogroup i2c_defines
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H
The order of header inclusion is important. i2c.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_I2C_H
/** @endcond */
#ifndef LIBOPENCM3_I2C_COMMON_F24_H
#define LIBOPENCM3_I2C_COMMON_F24_H
#include <libopencm3/stm32/common/i2c_common_all.h>
/**@{*/
#define I2C3 I2C3_BASE
/**@}*/
#endif
/** @cond */
#else
#warning "i2c_common_f24.h should not be included explicitly, only via i2c.h"
#endif
/** @endcond */

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/** @addtogroup iwdg_defines
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H
The order of header inclusion is important. iwdg.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_IWDG_H
/** @endcond */
#ifndef LIBOPENCM3_IWDG_COMMON_ALL_H
#define LIBOPENCM3_IWDG_COMMON_ALL_H
#include <libopencm3/cm3/common.h>
/**@{*/
/* --- IWDG registers ------------------------------------------------------ */
/* Key Register (IWDG_KR) */
#define IWDG_KR MMIO32(IWDG_BASE + 0x00)
/* Prescaler register (IWDG_PR) */
#define IWDG_PR MMIO32(IWDG_BASE + 0x04)
/* Reload register (IWDG_RLR) */
#define IWDG_RLR MMIO32(IWDG_BASE + 0x08)
/* Status register (IWDG_SR) */
#define IWDG_SR MMIO32(IWDG_BASE + 0x0c)
/* --- IWDG_KR values ------------------------------------------------------ */
/* Bits [31:16]: Reserved. */
/* KEY[15:0]: Key value (write-only, reads as 0x0000) */
/** @defgroup iwdg_key IWDG Key Values
@ingroup STM32F_iwdg_defines
@{*/
#define IWDG_KR_RESET 0xaaaa
#define IWDG_KR_UNLOCK 0x5555
#define IWDG_KR_START 0xcccc
/**@}*/
/* --- IWDG_PR values ------------------------------------------------------ */
/* Bits [31:3]: Reserved. */
/* PR[2:0]: Prescaler divider */
#define IWDG_PR_LSB 0
/** @defgroup iwdg_prediv IWDG prescaler divider
@ingroup STM32F_iwdg_defines
@{*/
#define IWDG_PR_DIV4 0x0
#define IWDG_PR_DIV8 0x1
#define IWDG_PR_DIV16 0x2
#define IWDG_PR_DIV32 0x3
#define IWDG_PR_DIV64 0x4
#define IWDG_PR_DIV128 0x5
#define IWDG_PR_DIV256 0x6
/**@}*/
/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
/* #define IWDG_PR_DIV256 0x7 */
/* --- IWDG_RLR values ----------------------------------------------------- */
/* Bits [31:12]: Reserved. */
/* RL[11:0]: Watchdog counter reload value */
/* --- IWDG_SR values ------------------------------------------------------ */
/* Bits [31:2]: Reserved. */
/* RVU: Watchdog counter reload value update */
#define IWDG_SR_RVU (1 << 1)
/* PVU: Watchdog prescaler value update */
#define IWDG_SR_PVU (1 << 0)
/* --- IWDG function prototypes---------------------------------------------- */
BEGIN_DECLS
void iwdg_start(void);
void iwdg_set_period_ms(uint32_t period);
bool iwdg_reload_busy(void);
bool iwdg_prescaler_busy(void);
void iwdg_reset(void);
END_DECLS
#endif
/** @cond */
#else
#warning "iwdg_common_all.h should not be included explicitly, only via iwdg.h"
#endif
/** @endcond */
/**@}*/

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/** @addtogroup pwr_defines
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H
The order of header inclusion is important. pwr.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_PWR_H
/** @endcond */
#ifndef LIBOPENCM3_PWR_COMMON_ALL_H
#define LIBOPENCM3_PWR_COMMON_ALL_H
/**@{*/
#include <libopencm3/cm3/common.h>
/* --- PWR registers ------------------------------------------------------- */
/* Power control register (PWR_CR) */
#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
/* Power control/status register (PWR_CSR) */
#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
/* --- PWR_CR values ------------------------------------------------------- */
/* Bits [31:9]: Reserved, must be kept at reset value. */
/* DBP: Disable backup domain write protection */
#define PWR_CR_DBP (1 << 8)
/* PLS[7:5]: PVD level selection */
#define PWR_CR_PLS_LSB 5
/** @defgroup pwr_pls PVD level selection
@ingroup STM32F_pwr_defines
@{*/
#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
/**@}*/
#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
/* PVDE: Power voltage detector enable */
#define PWR_CR_PVDE (1 << 4)
/* CSBF: Clear standby flag */
#define PWR_CR_CSBF (1 << 3)
/* CWUF: Clear wakeup flag */
#define PWR_CR_CWUF (1 << 2)
/* PDDS: Power down deepsleep */
#define PWR_CR_PDDS (1 << 1)
/* LPDS: Low-power deepsleep */
#define PWR_CR_LPDS (1 << 0)
/* --- PWR_CSR values ------------------------------------------------------ */
/* Bits [31:9]: Reserved, must be kept at reset value. */
/* EWUP: Enable WKUP pin */
#define PWR_CSR_EWUP (1 << 8)
/* Bits [7:3]: Reserved, must be kept at reset value. */
/* PVDO: PVD output */
#define PWR_CSR_PVDO (1 << 2)
/* SBF: Standby flag */
#define PWR_CSR_SBF (1 << 1)
/* WUF: Wakeup flag */
#define PWR_CSR_WUF (1 << 0)
/* --- PWR function prototypes ------------------------------------------- */
BEGIN_DECLS
void pwr_disable_backup_domain_write_protect(void);
void pwr_enable_backup_domain_write_protect(void);
void pwr_enable_power_voltage_detect(uint32_t pvd_level);
void pwr_disable_power_voltage_detect(void);
void pwr_clear_standby_flag(void);
void pwr_clear_wakeup_flag(void);
void pwr_set_standby_mode(void);
void pwr_set_stop_mode(void);
void pwr_voltage_regulator_on_in_stop(void);
void pwr_voltage_regulator_low_power_in_stop(void);
void pwr_enable_wakeup_pin(void);
void pwr_disable_wakeup_pin(void);
bool pwr_voltage_high(void);
bool pwr_get_standby_flag(void);
bool pwr_get_wakeup_flag(void);
END_DECLS
/**@}*/
#endif
/** @cond */
#else
#warning "pwr_common_all.h should not be included explicitly, only via pwr.h"
#endif
/** @endcond */

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/*
* This file is part of the libopencm3 project.
*
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RNG.H
The order of header inclusion is important. rng.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_RNG_H
/** @endcond */
#ifndef LIBOPENCM3_RNG_COMMON_F24_H
#define LIBOPENCM3_RNG_COMMON_F24_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- Random number generator registers ----------------------------------- */
/* Control register */
#define RNG_CR MMIO32(RNG_BASE + 0x00)
/* Status register */
#define RNG_SR MMIO32(RNG_BASE + 0x04)
/* Data register */
#define RNG_DR MMIO32(RNG_BASE + 0x08)
/* --- RNG_CR values ------------------------------------------------------- */
/* RNG ENABLE */
#define RNG_CR_RNGEN (1 << 2)
/* RNG interrupt enable */
#define RNG_CR_IE (1 << 3)
/* --- RNG_SR values ------------------------------------------------------- */
/* Data ready */
#define RNG_SR_DRDY (1 << 0)
/* Clock error current status */
#define RNG_SR_CECS (1 << 1)
/* Seed error current status */
#define RNG_SR_SECS (1 << 2)
/* Clock error interrupt status */
#define RNG_SR_CEIS (1 << 5)
/* Seed error interrupt status */
#define RNG_SR_SEIS (1 << 6)
#endif
/** @cond */
#else
#warning "rng_common_f24.h should not be included explicitly, only via rng.h"
#endif
/** @endcond */

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/** @addtogroup rtc_defines
@author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* This covers the "version 2" RTC peripheral. This is completely different
* to the v1 RTC periph on the F1 series devices. It has BCD counters, with
* automatic leapyear corrections and daylight savings support.
* This peripheral is used on the F0, F2, F3, F4 and L1 devices, though some
* only support a subset.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H
The order of header inclusion is important. rtc.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_RTC_H
/** @endcond */
#ifndef LIBOPENCM3_RTC2_H
#define LIBOPENCM3_RTC2_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/memorymap.h>
/* RTC time register (RTC_TR) */
#define RTC_TR MMIO32(RTC_BASE + 0x00)
/* RTC date register (RTC_DR) */
#define RTC_DR MMIO32(RTC_BASE + 0x04)
/* RTC control register (RTC_CR) */
#define RTC_CR MMIO32(RTC_BASE + 0x08)
/* RTC initialization and status register (RTC_ISR) */
#define RTC_ISR MMIO32(RTC_BASE + 0x0c)
/* RTC prescaler register (RTC_PRER) */
#define RTC_PRER MMIO32(RTC_BASE + 0x10)
/* RTC wakeup timer register (RTC_WUTR) */
#define RTC_WUTR MMIO32(RTC_BASE + 0x14)
/* RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */
#define RTC_CALIBR MMIO32(RTC_BASE + 0x18)
/* RTC alarm X register (RTC_ALRMxR) */
#define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c)
#define RTC_ALRMBR MMIO32(RTC_BASE + 0x20)
/* RTC write protection register (RTC_WPR)*/
#define RTC_WPR MMIO32(RTC_BASE + 0x24)
/* RTC sub second register (RTC_SSR) (high and med+ only) */
#define RTC_SSR MMIO32(RTC_BASE + 0x28)
/* RTC shift control register (RTC_SHIFTR) (high and med+ only) */
#define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c)
/* RTC time stamp time register (RTC_TSTR) */
#define RTC_TSTR MMIO32(RTC_BASE + 0x30)
/* RTC time stamp date register (RTC_TSDR) */
#define RTC_TSDR MMIO32(RTC_BASE + 0x34)
/* RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */
#define RTC_TSSSR MMIO32(RTC_BASE + 0x38)
/* RTC calibration register (RTC_CALR) (high and med+ only) */
#define RTC_CALR MMIO32(RTC_BASE + 0x3c)
/* RTC tamper and alternate function configuration register (RTC_TAFCR) */
#define RTC_TAFCR MMIO32(RTC_BASE + 0x40)
/* RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */
#define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44)
#define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48)
/* RTC backup registers (RTC_BKPxR) */
#define RTC_BKP_BASE (RTC_BASE + 0x50)
#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4*reg))
/* RTC time register (RTC_TR) ----------------------------------- */
/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value.
*/
#define RTC_TR_PM (1 << 22) /* AM/PM notation */
#define RTC_TR_HT_SHIFT (20) /* Hour tens in BCD format shift */
#define RTC_TR_HT_MASK (0x3) /* Hour tens in BCD format mask */
#define RTC_TR_HU_SHIFT (16) /* Hour units in BCD format shift */
#define RTC_TR_HU_MASK (0xf) /* Hour units in BCD format mask */
#define RTC_TR_MNT_SHIFT (12) /* Minute tens in BCD format shift */
#define RTC_TR_MNT_MASK (0x7) /* Minute tens in BCD format mask */
#define RTC_TR_MNU_SHIFT (8) /* Minute units in BCD format shift */
#define RTC_TR_MNU_MASK (0xf) /* Minute units in BCD format mask */
#define RTC_TR_ST_SHIFT (4) /* Second tens in BCD format shift */
#define RTC_TR_ST_MASK (0x7) /* Second tens in BCD format mask */
#define RTC_TR_SU_SHIFT (0) /* Second units in BCD format shift */
#define RTC_TR_SU_MASK (0xf) /* Second units in BCD format mask */
/* RTC date register (RTC_DR) ----------------------------------- */
/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value.
*/
#define RTC_DR_YT_SHIFT (20) /* Year tens in BCD format shift */
#define RTC_DR_YT_MASK (0xf) /* Year tens in BCD format mask */
#define RTC_DR_YU_SHIFT (16) /* Year units in BCD format shift */
#define RTC_DR_YU_MASK (0xf) /* Year units in BCD format mask */
#define RTC_DR_WDU_SHIFT (13) /* Weekday units shift */
#define RTC_DR_WDU_MASK (0x7) /* Weekday units mask */
#define RTC_DR_MT (1<<12) /* Month tens in BCD format shift */
#define RTC_DR_MT_SHIFT (12) /* Month tens in BCD format mask */
#define RTC_DR_MU_SHIFT (8) /* Month units in BCD format shift */
#define RTC_DR_MU_MASK (0xf) /* Month units in BCD format mask */
#define RTC_DR_DT_SHIFT (4) /* Date tens in BCD format shift */
#define RTC_DR_DT_MASK (0x3) /* Date tens in BCD format mask */
#define RTC_DR_DU_SHIFT (0) /* Date units in BCD format shift */
#define RTC_DR_DU_MASK (0xf) /* Date units in BCD format mask */
/* RTC control register (RTC_CR) -------------------------------- */
/* Note: Bits [31:24] are reserved, and must be kept at reset value. */
/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode
* only (RTC_ISR/INITF = 1).
*/
/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit
* = 0 and RTC_ISR WUTWF bit = 1.
*/
#define RTC_CR_COE (1<<23) /* RTC_CR_COE: Calibration output enable */
/* RTC_CR_OSEL: Output selection values */
/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC
* output
*/
#define RTC_CR_OSEL_SHIFT 21
#define RTC_CR_OSEL_MASK (0x3)
#define RTC_CR_OSEL_DISABLED (0x0)
#define RTC_CR_OSEL_ALARMA (0x1)
#define RTC_CR_OSEL_ALARMB (0x2)
#define RTC_CR_OSEL_WAKEUP (0x3)
#define RTC_CR_POL (1<<20) /* RTC_CR_POL: Output polarity */
#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output
selection */
#define RTC_CR_BKP (1<<18) /* RTC_CR_BKP: Backup */
#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour
(winter time change) */
#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer
time change) */
#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt
enable */
#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer
interrupt enable */
#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt
enable */
#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt
enable */
#define RTC_CR_TSE (1<<11) /* RTC_CR_TSE: Time stamp enable */
#define RTC_CR_WUTE (1<<10) /* RTC_CR_WUTE: Wakeup timer enable */
#define RTC_CR_ALRBE (1<<9) /* RTC_CR_ALRBIE: Alarm B enable */
#define RTC_CR_ALRAE (1<<8) /* RTC_CR_ALRAE: Alarm A enable */
#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital
calibration enable */
#define RTC_CR_FMT (1<<6) /* RTC_CR_FMT: Hour format */
#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow
registers */
#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock
detection enable */
#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event
active edge */
/* RTC_CR_WUCKSEL: Wakeup clock selection */
#define RTC_CR_WUCLKSEL_SHIFT (0)
#define RTC_CR_WUCLKSEL_MASK (0x7)
#define RTC_CR_WUCLKSEL_RTC_DIV16 (0x0)
#define RTC_CR_WUCLKSEL_RTC_DIV8 (0x1)
#define RTC_CR_WUCLKSEL_RTC_DIV4 (0x2)
#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3)
#define RTC_CR_WUCLKSEL_SPRE (0x4)
#define RTC_CR_WUCLKSEL_SPRE_216 (0x6)
/* RTC initialization and status register (RTC_ISR) ------------- */
/* Note: Bits [31:17] and [15] are reserved, and must be kept at reset value. */
/* Note: This register is write protected (except for RTC_ISR[13:8] bits). */
#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalib pending flag */
#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag
(not on F4)*/
#define RTC_ISR_TAMP2F (1<<14) /* TAMP2F: TAMPER2 detection flag */
#define RTC_ISR_TAMP1F (1<<13) /* TAMP1F: TAMPER detection flag */
#define RTC_ISR_TSOVF (1<<12) /* TSOVF: Timestamp overflow flag */
#define RTC_ISR_TSF (1<<11) /* TSF: Timestamp flag */
#define RTC_ISR_WUTF (1<<10) /* WUTF: Wakeup timer flag */
#define RTC_ISR_ALRBF (1<<9) /* ALRBF: Alarm B flag */
#define RTC_ISR_ALRAF (1<<8) /* ALRAF: Alarm A flag */
#define RTC_ISR_INIT (1<<7) /* INIT: Initialization mode */
#define RTC_ISR_INITF (1<<6) /* INITF: Initialization flag */
#define RTC_ISR_RSF (1<<5) /* RSF: Registers sync flag */
#define RTC_ISR_INITS (1<<4) /* INITS: Init status flag */
#define RTC_ISR_SHPF (1<<3) /* SHPF: Shift operation pending */
#define RTC_ISR_WUTWF (1<<2) /* WUTWF: Wakeup timer write flag */
#define RTC_ISR_ALRBWF (1<<1) /* ALRBWF: Alarm B write flag */
#define RTC_ISR_ALRAWF (1<<0) /* ALRAWF: Alarm A write flag */
/* RTC prescaler register (RTC_PRER) ---------------------------- */
#define RTC_PRER_PREDIV_A_SHIFT (16) /* Async prescaler factor shift */
#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Async prescaler factor mask */
#define RTC_PRER_PREDIV_S_SHIFT (0) /* Sync prescaler factor shift */
#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Sync prescaler factor mask */
/* RTC calibration register (RTC_CALIBR) ------------------------ */
/* FIXME - TODO */
/* RTC Alarm register ------------------------------------------- */
/* Note: Applies to RTC_ALRMAR and RTC_ALRMBR */
#define RTC_ALRMXR_MSK4 (1<<31)
#define RTC_ALRMXR_WDSEL (1<<30)
#define RTC_ALRMXR_DT_SHIFT (28)
#define RTC_ALRMXR_DT_MASK (0x3)
#define RTC_ALRMXR_DU_SHIFT (24)
#define RTC_ALRMXR_DU_MASK (0xf)
#define RTC_ALRMXR_MSK3 (1<<23)
#define RTC_ALRMXR_PM (1<<22)
#define RTC_ALRMXR_HT_SHIFT (20)
#define RTC_ALRMXR_HT_MASK (0x3)
#define RTC_ALRMXR_HU_SHIFT (16)
#define RTC_ALRMXR_HU_MASK (0xf)
#define RTC_ALRMXR_MSK2 (1<<15)
#define RTC_ALRMXR_MNT_SHIFT (12)
#define RTC_ALRMXR_MNT_MASK (0x7)
#define RTC_ALRMXR_MNU_SHIFT (8)
#define RTC_ALRMXR_MNU_MASK (0xf)
#define RTC_ALRMXR_MSK1 (1<<7)
#define RTC_ALRMXR_ST_SHIFT (4)
#define RTC_ALRMXR_ST_MASK (0x7)
#define RTC_ALRMXR_SU_SHIFT (0)
#define RTC_ALRMXR_SU_MASK (0xf)
/* RTC shift control register (RTC_SHIFTR) */
/* FIXME - TODO */
/* RTC time stamp time register (RTC_TSTR) ---------------------- */
#define RTC_TSTR_PM (1<<22)
#define RTC_TSTR_HT_SHIFT (20)
#define RTC_TSTR_HT_MASK (0x3)
#define RTC_TSTR_HU_SHIFT (16)
#define RTC_TSTR_HU_MASK (0xf)
#define RTC_TSTR_MNT_SHIFT (12)
#define RTC_TSTR_MNT_MASK (0x7)
#define RTC_TSTR_MNU_SHIFT (8)
#define RTC_TSTR_MNU_MASK (0xf)
#define RTC_TSTR_ST_SHIFT (4)
#define RTC_TSTR_ST_MASK (0x7)
#define RTC_TSTR_SU_SHIFT (0)
#define RTC_TSTR_SU_MASK (0xf)
/* RTC time stamp date register (RTC_TSDR) ---------------------- */
#define RTC_TSDR_WDU_SHIFT (13)
#define RTC_TSDR_WDU_MASK (0x7)
#define RTC_TSDR_MT (1<<12)
#define RTC_TSDR_MU_SHIFT (8)
#define RTC_TSDR_MU_MASK (0xf)
#define RTC_TSDR_DT_SHIFT (4)
#define RTC_TSDR_DT_MASK (0x3)
#define RTC_TSDR_DU_SHIFT (0)
#define RTC_TSDR_DU_MASK (0xf)
/* RTC calibration register (RTC_CALR) -------------------------- */
/* FIXME - TODO */
/* RTC tamper and alternate function configuration register (RTC_TAFCR) --- */
#define RTC_TAFCR_ALARMOUTTYPE (1<<18)
#define RTC_TAFCR_TAMPPUDIS (1<<15)
#define RTC_TAFCR_TAMPPRCH_SHIFT (13)
#define RTC_TAFCR_TAMPPRCH_MASK (0x3)
#define RTC_TAFCR_TAMPPRCH_1RTC (0x0)
#define RTC_TAFCR_TAMPPRCH_2RTC (0x1)
#define RTC_TAFCR_TAMPPRCH_4RTC (0x2)
#define RTC_TAFCR_TAMPPRCH_8RTC (0x3)
#define RTC_TAFCR_TAMPFLT_SHIFT (11)
#define RTC_TAFCR_TAMPFLT_MASK (0x3)
#define RTC_TAFCR_TAMPFLT_EDGE1 (0x0)
#define RTC_TAFCR_TAMPFLT_EDGE2 (0x1)
#define RTC_TAFCR_TAMPFLT_EDGE4 (0x2)
#define RTC_TAFCR_TAMPFLT_EDGE8 (0x3)
#define RTC_TAFCR_TAMPFREQ_SHIFT (8)
#define RTC_TAFCR_TAMPFREQ_MASK (0x7)
#define RTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0)
#define RTC_TAFCR_TAMPFREQ_RTCDIV16K (0x1)
#define RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2)
#define RTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3)
#define RTC_TAFCR_TAMPFREQ_RTCDIV2K (0x4)
#define RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5)
#define RTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6)
#define RTC_TAFCR_TAMPFREQ_RTCDIV256 (0x7)
#define RTC_TAFCR_TAMPTS (1<<7)
#define RTC_TAFCR_TAMP3TRG (1<<6)
#define RTC_TAFCR_TAMP3E (1<<5)
#define RTC_TAFCR_TAMP2TRG (1<<4)
#define RTC_TAFCR_TAMP2E (1<<3)
#define RTC_TAFCR_TAMPIE (1<<2)
#define RTC_TAFCR_TAMP1TRG (1<<1)
#define RTC_TAFCR_TAMP1E (1<<0)
/* RTC alarm X sub second register */
/* FIXME - TODO */
BEGIN_DECLS
void rtc_set_prescaler(uint32_t sync, uint32_t async);
void rtc_wait_for_synchro(void);
void rtc_lock(void);
void rtc_unlock(void);
void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel);
void rtc_clear_wakeup_flag(void);
END_DECLS
/**@}*/
#endif /* RTC2_H */
/** @cond */
#else
#warning "rtc_common_bcd.h should not be included explicitly, only via rtc.h"
#endif
/** @endcond */

405
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/common/spi_common_all.h Normal file
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/** @addtogroup spi_defines
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
The order of header inclusion is important. spi.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined(LIBOPENCM3_SPI_H) || defined(LIBOPENCM3_SPI_COMMON_F24_H)
/** @endcond */
#ifndef LIBOPENCM3_SPI_COMMON_ALL_H
#define LIBOPENCM3_SPI_COMMON_ALL_H
#include <libopencm3/cm3/common.h>
/**@{*/
/* Registers can be accessed as 16bit or 32bit values. */
/* --- Convenience macros -------------------------------------------------- */
/****************************************************************************/
/** @defgroup spi_reg_base SPI Register base address
@ingroup spi_defines
@{*/
#define SPI1 SPI1_BASE
#define SPI2 SPI2_I2S_BASE
#define SPI3 SPI3_I2S_BASE
/**@}*/
/* --- SPI registers ------------------------------------------------------- */
/* Control register 1 (SPIx_CR1) */
/* Note: Not used in I2S mode. */
#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00)
#define SPI1_CR1 SPI_CR1(SPI1_BASE)
#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE)
#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE)
/* Control register 2 (SPIx_CR2) */
#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04)
#define SPI1_CR2 SPI_CR2(SPI1_BASE)
#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE)
#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE)
/* Status register (SPIx_SR) */
#define SPI_SR(spi_base) MMIO32(spi_base + 0x08)
#define SPI1_SR SPI_SR(SPI1_BASE)
#define SPI2_SR SPI_SR(SPI2_I2S_BASE)
#define SPI3_SR SPI_SR(SPI3_I2S_BASE)
/* Data register (SPIx_DR) */
#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c)
#define SPI1_DR SPI_DR(SPI1_BASE)
#define SPI2_DR SPI_DR(SPI2_I2S_BASE)
#define SPI3_DR SPI_DR(SPI3_I2S_BASE)
/* CRC polynomial register (SPIx_CRCPR) */
/* Note: Not used in I2S mode. */
#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10)
#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE)
#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE)
#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE)
/* RX CRC register (SPIx_RXCRCR) */
/* Note: Not used in I2S mode. */
#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14)
#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)
#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE)
#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE)
/* TX CRC register (SPIx_RXCRCR) */
/* Note: Not used in I2S mode. */
#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18)
#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)
#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE)
#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE)
/* I2S configuration register (SPIx_I2SCFGR) */
#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c)
#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)
#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE)
#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE)
/* I2S prescaler register (SPIx_I2SPR) */
#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20)
#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE)
#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE)
#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE)
/* --- SPI_CR1 values ------------------------------------------------------ */
/* Note: None of the CR1 bits are used in I2S mode. */
/* BIDIMODE: Bidirectional data mode enable */
#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)
#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)
#define SPI_CR1_BIDIMODE (1 << 15)
/* BIDIOE: Output enable in bidirectional mode */
#define SPI_CR1_BIDIOE (1 << 14)
/* CRCEN: Hardware CRC calculation enable */
#define SPI_CR1_CRCEN (1 << 13)
/* CRCNEXT: Transmit CRC next */
#define SPI_CR1_CRCNEXT (1 << 12)
/* RXONLY: Receive only */
#define SPI_CR1_RXONLY (1 << 10)
/* SSM: Software slave management */
#define SPI_CR1_SSM (1 << 9)
/* SSI: Internal slave select */
#define SPI_CR1_SSI (1 << 8)
/* LSBFIRST: Frame format */
/****************************************************************************/
/** @defgroup spi_lsbfirst SPI lsb/msb first
@ingroup spi_defines
@{*/
#define SPI_CR1_MSBFIRST (0 << 7)
#define SPI_CR1_LSBFIRST (1 << 7)
/**@}*/
/* SPE: SPI enable */
#define SPI_CR1_SPE (1 << 6)
/* BR[2:0]: Baud rate control */
/****************************************************************************/
/** @defgroup spi_baudrate SPI peripheral baud rates
@ingroup spi_defines
@{*/
#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
/**@}*/
/****************************************************************************/
/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
@ingroup spi_defines
@{*/
#define SPI_CR1_BR_FPCLK_DIV_2 0x0
#define SPI_CR1_BR_FPCLK_DIV_4 0x1
#define SPI_CR1_BR_FPCLK_DIV_8 0x2
#define SPI_CR1_BR_FPCLK_DIV_16 0x3
#define SPI_CR1_BR_FPCLK_DIV_32 0x4
#define SPI_CR1_BR_FPCLK_DIV_64 0x5
#define SPI_CR1_BR_FPCLK_DIV_128 0x6
#define SPI_CR1_BR_FPCLK_DIV_256 0x7
/**@}*/
/* MSTR: Master selection */
#define SPI_CR1_MSTR (1 << 2)
/* CPOL: Clock polarity */
/****************************************************************************/
/** @defgroup spi_cpol SPI clock polarity
@ingroup spi_defines
@{*/
#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
/**@}*/
#define SPI_CR1_CPOL (1 << 1)
/* CPHA: Clock phase */
/****************************************************************************/
/** @defgroup spi_cpha SPI clock phase
@ingroup spi_defines
@{*/
#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
/**@}*/
#define SPI_CR1_CPHA (1 << 0)
/* --- SPI_CR2 values ------------------------------------------------------ */
/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */
/* TXEIE: Tx buffer empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7)
/* RXNEIE: Rx buffer not empty interrupt enable */
#define SPI_CR2_RXNEIE (1 << 6)
/* ERRIE: Error interrupt enable */
#define SPI_CR2_ERRIE (1 << 5)
/* Bits [4:3]: Reserved. Forced to 0 by hardware. */
/* SSOE: SS output enable */
/* Note: Not used in I2S mode. */
#define SPI_CR2_SSOE (1 << 2)
/* TXDMAEN: Tx buffer DMA enable */
#define SPI_CR2_TXDMAEN (1 << 1)
/* RXDMAEN: Rx buffer DMA enable */
#define SPI_CR2_RXDMAEN (1 << 0)
/* --- SPI_SR values ------------------------------------------------------- */
/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */
/* BSY: Busy flag */
#define SPI_SR_BSY (1 << 7)
/* OVR: Overrun flag */
#define SPI_SR_OVR (1 << 6)
/* MODF: Mode fault */
/* Note: Not used in I2S mode. */
#define SPI_SR_MODF (1 << 5)
/* CRCERR: CRC error flag */
/* Note: Not used in I2S mode. */
#define SPI_SR_CRCERR (1 << 4)
/* UDR: Underrun flag */
/* Note: Not used in SPI mode. */
#define SPI_SR_UDR (1 << 3)
/* CHSIDE: Channel side */
/* Note: Not used in SPI mode. No meaning in PCM mode. */
#define SPI_SR_CHSIDE (1 << 2)
/* TXE: Transmit buffer empty */
#define SPI_SR_TXE (1 << 1)
/* RXNE: Receive buffer not empty */
#define SPI_SR_RXNE (1 << 0)
/* --- SPI_DR values ------------------------------------------------------- */
/* SPI_DR[15:0]: Data Register. */
/* --- SPI_CRCPR values ---------------------------------------------------- */
/* Note: Not used in I2S mode. */
/* SPI_CRCPR [15:0]: CRC Polynomial Register. */
/* --- SPI_RXCRCR values --------------------------------------------------- */
/* Note: Not used in I2S mode. */
/* SPI_RXCRCR [15:0]: RX CRC Register. */
/* --- SPI_TXCRCR values --------------------------------------------------- */
/* Note: Not used in I2S mode. */
/* SPI_TXCRCR [15:0]: TX CRC Register. */
/* --- SPI_I2SCFGR values -------------------------------------------------- */
/* Note: None of these bits are used in SPI mode. */
/* Bits [15:12]: Reserved. Forced to 0 by hardware. */
/* I2SMOD: I2S mode selection */
#define SPI_I2SCFGR_I2SMOD (1 << 11)
/* I2SE: I2S enable */
#define SPI_I2SCFGR_I2SE (1 << 10)
/* I2SCFG[9:8]: I2S configuration mode */
#define SPI_I2SCFGR_I2SCFG_LSB 8
#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0
#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1
#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2
#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3
/* PCMSYNC: PCM frame synchronization */
#define SPI_I2SCFGR_PCMSYNC (1 << 7)
/* Bit 6: Reserved. Forced to 0 by hardware. */
/* I2SSTD[5:4]: I2S standard selection */
#define SPI_I2SCFGR_I2SSTD_LSB 4
#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0
#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1
#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2
#define SPI_I2SCFGR_I2SSTD_PCM 0x3
/* CKPOL: Steady state clock polarity */
#define SPI_I2SCFGR_CKPOL (1 << 3)
/* DATLEN[2:1]: Data length to be transferred */
#define SPI_I2SCFGR_DATLEN_LSB 1
#define SPI_I2SCFGR_DATLEN_16BIT 0x0
#define SPI_I2SCFGR_DATLEN_24BIT 0x1
#define SPI_I2SCFGR_DATLEN_32BIT 0x2
/* CHLEN: Channel length */
#define SPI_I2SCFGR_CHLEN (1 << 0)
/* --- SPI_I2SPR values ---------------------------------------------------- */
/* Note: None of these bits are used in SPI mode. */
/* Bits [15:10]: Reserved. Forced to 0 by hardware. */
/* MCKOE: Master clock output enable */
#define SPI_I2SPR_MCKOE (1 << 9)
/* ODD: Odd factor for the prescaler */
#define SPI_I2SPR_ODD (1 << 8)
/* I2SDIV[7:0]: I2S linear prescaler */
/* 0 and 1 are forbidden values */
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void spi_reset(uint32_t spi_peripheral);
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
uint32_t dff, uint32_t lsbfirst);
void spi_enable(uint32_t spi);
void spi_disable(uint32_t spi);
uint16_t spi_clean_disable(uint32_t spi);
void spi_write(uint32_t spi, uint16_t data);
void spi_send(uint32_t spi, uint16_t data);
uint16_t spi_read(uint32_t spi);
uint16_t spi_xfer(uint32_t spi, uint16_t data);
void spi_set_bidirectional_mode(uint32_t spi);
void spi_set_unidirectional_mode(uint32_t spi);
void spi_set_bidirectional_receive_only_mode(uint32_t spi);
void spi_set_bidirectional_transmit_only_mode(uint32_t spi);
void spi_enable_crc(uint32_t spi);
void spi_disable_crc(uint32_t spi);
void spi_set_next_tx_from_buffer(uint32_t spi);
void spi_set_next_tx_from_crc(uint32_t spi);
void spi_set_dff_8bit(uint32_t spi);
void spi_set_dff_16bit(uint32_t spi);
void spi_set_full_duplex_mode(uint32_t spi);
void spi_set_receive_only_mode(uint32_t spi);
void spi_disable_software_slave_management(uint32_t spi);
void spi_enable_software_slave_management(uint32_t spi);
void spi_set_nss_high(uint32_t spi);
void spi_set_nss_low(uint32_t spi);
void spi_send_lsb_first(uint32_t spi);
void spi_send_msb_first(uint32_t spi);
void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate);
void spi_set_master_mode(uint32_t spi);
void spi_set_slave_mode(uint32_t spi);
void spi_set_clock_polarity_1(uint32_t spi);
void spi_set_clock_polarity_0(uint32_t spi);
void spi_set_clock_phase_1(uint32_t spi);
void spi_set_clock_phase_0(uint32_t spi);
void spi_enable_tx_buffer_empty_interrupt(uint32_t spi);
void spi_disable_tx_buffer_empty_interrupt(uint32_t spi);
void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi);
void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi);
void spi_enable_error_interrupt(uint32_t spi);
void spi_disable_error_interrupt(uint32_t spi);
void spi_enable_ss_output(uint32_t spi);
void spi_disable_ss_output(uint32_t spi);
void spi_enable_tx_dma(uint32_t spi);
void spi_disable_tx_dma(uint32_t spi);
void spi_enable_rx_dma(uint32_t spi);
void spi_disable_rx_dma(uint32_t spi);
END_DECLS
/**@}*/
#endif
/** @cond */
#else
#warning "spi_common_all.h should not be included explicitly, only via spi.h"
#endif
/** @endcond */

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/** @addtogroup spi_defines
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
The order of header inclusion is important. spi.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_SPI_H
/** @endcond */
#ifndef LIBOPENCM3_SPI_COMMON_F0124_H
#define LIBOPENCM3_SPI_COMMON_F0124_H
/**@{*/
#include <libopencm3/stm32/common/spi_common_all.h>
/*
* This file extends the common STM32 version with definitions only
* applicable to the STM32F0/1/2/4 series of devices.
*/
/* DFF: Data frame format */
/****************************************************************************/
/** @defgroup spi_dff SPI data frame format
@ingroup spi_defines
@{*/
#define SPI_CR1_DFF_8BIT (0 << 11)
#define SPI_CR1_DFF_16BIT (1 << 11)
/**@}*/
#define SPI_CR1_DFF (1 << 11)
#endif
/** @cond */
#else
#warning "spi_common_f24.h should not be included explicitly, only via spi.h"
#endif
/** @endcond */
/**@}*/

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/** @addtogroup spi_defines
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
The order of header inclusion is important. spi.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_SPI_H
/** @endcond */
#ifndef LIBOPENCM3_SPI_COMMON_F24_H
#define LIBOPENCM3_SPI_COMMON_F24_H
/**@{*/
#include <libopencm3/stm32/common/spi_common_f124.h>
/*
* This file extends the common STM32 version with definitions only
* applicable to the STM32F2/4 series of devices.
*/
/* --- SPI_CR2 values ------------------------------------------------------ */
/* FRF: Frame format */
/* Note: Not used in I2S mode. */
#define SPI_CR2_FRF (1 << 4)
#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
#define SPI_CR2_FRF_TI_MODE (1 << 4)
/* --- SPI_SR values ------------------------------------------------------- */
/* TIFRFE: TI frame format error */
#define SPI_SR_TIFRFE (1 << 8)
#endif
/** @cond */
#else
#warning "spi_common_f24.h should not be included explicitly, only via spi.h"
#endif
/** @endcond */
/**@}*/

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
The order of header inclusion is important. spi.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined(LIBOPENCM3_SYSCFG_H)
/** @endcond */
#ifndef LIBOPENCM3_SYSCFG_COMMON_L1F234_H
#define LIBOPENCM3_SYSCFG_COMMON_L1F234_H
#include <libopencm3/stm32/memorymap.h>
/* --- SYSCFG registers ---------------------------------------------------- */
#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00)
#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04)
/* External interrupt configuration registers [0..3] (SYSCFG_EXTICR[1..4]) */
#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4)
#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0)
#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1)
#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2)
#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3)
#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20)
#endif
/** @cond */
#else
#warning "syscfg_common_l1f234.h should not be included explicitly,"
#warning "only via syscfg.h"
#endif
/** @endcond */

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/** @addtogroup timer_defines
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H
The order of header inclusion is important. timer.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_TIMER_H
/** @endcond */
#ifndef LIBOPENCM3_TIMER_COMMON_F24_H
#define LIBOPENCM3_TIMER_COMMON_F24_H
#include <libopencm3/stm32/common/timer_common_all.h>
/*
* TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide:
* CNT, ARR, CCR1, CCR2, CCR3, CCR4
*/
/* Timer 2/5 option register (TIMx_OR) */
#define TIM_OR(tim_base) MMIO32(tim_base + 0x50)
#define TIM2_OR TIM_OR(TIM2)
#define TIM5_OR TIM_OR(TIM5)
/* --- TIM2_OR values ---------------------------------------------------- */
/* ITR1_RMP */
/****************************************************************************/
/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal
Trigger 1 Remap
Only available in F2 and F4 series.
@ingroup timer_defines
@{*/
/** Internal Trigger 1 remapped to timer 8 trigger out */
#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10)
/** Internal Trigger 1 remapped to PTP trigger out */
#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10)
/** Internal Trigger 1 remapped to USB OTG FS SOF */
#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10)
/** Internal Trigger 1 remapped to USB OTG HS SOF */
#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10)
/**@}*/
#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10)
/* --- TIM5_OR values ---------------------------------------------------- */
/* ITR4_RMP */
/****************************************************************************/
/** @defgroup tim5_opt_trigger_remap TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap
Only available in F2 and F4 series.
@ingroup timer_defines
@{*/
/** Internal Trigger 4 remapped to GPIO (see reference manual) */
#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6)
/** Internal Trigger 4 remapped to LSI internal clock */
#define TIM5_OR_TI4_RMP_LSI (0x1 << 6)
/** Internal Trigger 4 remapped to LSE internal clock */
#define TIM5_OR_TI4_RMP_LSE (0x2 << 6)
/** Internal Trigger 4 remapped to RTC output event */
#define TIM5_OR_TI4_RMP_RTC (0x3 << 6)
/**@}*/
#define TIM5_OR_TI4_RMP_MASK (0x3 << 6)
/** Input Capture input polarity */
enum tim_ic_pol {
TIM_IC_RISING,
TIM_IC_FALLING,
TIM_IC_BOTH,
};
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void timer_set_option(uint32_t timer_peripheral, uint32_t option);
void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic,
enum tim_ic_pol pol);
END_DECLS
#endif
/** @cond */
#else
#warning "timer_common_f24.h should not be included directly, only via timer.h"
#endif
/** @endcond */

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/** @addtogroup usart_defines
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H
The order of header inclusion is important. usart.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined(LIBOPENCM3_USART_H)
/** @endcond */
#ifndef LIBOPENCM3_USART_COMMON_ALL_H
#define LIBOPENCM3_USART_COMMON_ALL_H
#include <libopencm3/cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */
/****************************************************************************/
/** @defgroup usart_reg_base USART register base addresses
@ingroup STM32F_usart_defines
@{*/
#define USART1 USART1_BASE
#define USART2 USART2_BASE
#define USART3 USART3_BASE
/**@}*/
#define UART4 UART4_BASE
#define UART5 UART5_BASE
/* --- Convenience defines ------------------------------------------------- */
/* CR1_PCE / CR1_PS combined values */
/****************************************************************************/
/** @defgroup usart_cr1_parity USART Parity Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_PARITY_NONE 0x00
#define USART_PARITY_EVEN USART_CR1_PCE
#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)
/**@}*/
#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
/* CR1_TE/CR1_RE combined values */
/****************************************************************************/
/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_MODE_RX USART_CR1_RE
#define USART_MODE_TX USART_CR1_TE
#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)
/**@}*/
#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)
/****************************************************************************/
/** @defgroup usart_cr2_stopbits USART Stop Bit Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* .5 stop bit */
#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bit*/
/**@}*/
/* CR3_CTSE/CR3_RTSE combined values */
/****************************************************************************/
/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
@ingroup STM32F_usart_defines
@{*/
#define USART_FLOWCONTROL_NONE 0x00
#define USART_FLOWCONTROL_RTS USART_CR3_RTSE
#define USART_FLOWCONTROL_CTS USART_CR3_CTSE
#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
/**@}*/
#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void usart_set_baudrate(uint32_t usart, uint32_t baud);
void usart_set_databits(uint32_t usart, uint32_t bits);
void usart_set_stopbits(uint32_t usart, uint32_t stopbits);
void usart_set_parity(uint32_t usart, uint32_t parity);
void usart_set_mode(uint32_t usart, uint32_t mode);
void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol);
void usart_enable(uint32_t usart);
void usart_disable(uint32_t usart);
void usart_send(uint32_t usart, uint16_t data);
uint16_t usart_recv(uint32_t usart);
void usart_wait_send_ready(uint32_t usart);
void usart_wait_recv_ready(uint32_t usart);
void usart_send_blocking(uint32_t usart, uint16_t data);
uint16_t usart_recv_blocking(uint32_t usart);
void usart_enable_rx_dma(uint32_t usart);
void usart_disable_rx_dma(uint32_t usart);
void usart_enable_tx_dma(uint32_t usart);
void usart_disable_tx_dma(uint32_t usart);
void usart_enable_rx_interrupt(uint32_t usart);
void usart_disable_rx_interrupt(uint32_t usart);
void usart_enable_tx_interrupt(uint32_t usart);
void usart_disable_tx_interrupt(uint32_t usart);
void usart_enable_error_interrupt(uint32_t usart);
void usart_disable_error_interrupt(uint32_t usart);
bool usart_get_flag(uint32_t usart, uint32_t flag);
bool usart_get_interrupt_source(uint32_t usart, uint32_t flag);
END_DECLS
#endif
/** @cond */
#else
#warning "usart_common_all.h should not be included directly, only via usart.h"
#endif
/** @endcond */
/**@}*/

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/** @addtogroup usart_defines
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H
The order of header inclusion is important. usart.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#if defined(LIBOPENCM3_USART_H)
/** @endcond */
#ifndef LIBOPENCM3_USART_COMMON_F124_H
#define LIBOPENCM3_USART_COMMON_F124_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/common/usart_common_all.h>
/* --- USART registers ----------------------------------------------------- */
/* Status register (USARTx_SR) */
#define USART_SR(usart_base) MMIO32(usart_base + 0x00)
#define USART1_SR USART_SR(USART1_BASE)
#define USART2_SR USART_SR(USART2_BASE)
#define USART3_SR USART_SR(USART3_BASE)
#define UART4_SR USART_SR(UART4_BASE)
#define UART5_SR USART_SR(UART5_BASE)
/* Data register (USARTx_DR) */
#define USART_DR(usart_base) MMIO32(usart_base + 0x04)
#define USART1_DR USART_DR(USART1_BASE)
#define USART2_DR USART_DR(USART2_BASE)
#define USART3_DR USART_DR(USART3_BASE)
#define UART4_DR USART_DR(UART4_BASE)
#define UART5_DR USART_DR(UART5_BASE)
/* Baud rate register (USARTx_BRR) */
#define USART_BRR(usart_base) MMIO32(usart_base + 0x08)
#define USART1_BRR USART_BRR(USART1_BASE)
#define USART2_BRR USART_BRR(USART2_BASE)
#define USART3_BRR USART_BRR(USART3_BASE)
#define UART4_BRR USART_BRR(UART4_BASE)
#define UART5_BRR USART_BRR(UART5_BASE)
/* Control register 1 (USARTx_CR1) */
#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c)
#define USART1_CR1 USART_CR1(USART1_BASE)
#define USART2_CR1 USART_CR1(USART2_BASE)
#define USART3_CR1 USART_CR1(USART3_BASE)
#define UART4_CR1 USART_CR1(UART4_BASE)
#define UART5_CR1 USART_CR1(UART5_BASE)
/* Control register 2 (USARTx_CR2) */
#define USART_CR2(usart_base) MMIO32(usart_base + 0x10)
#define USART1_CR2 USART_CR2(USART1_BASE)
#define USART2_CR2 USART_CR2(USART2_BASE)
#define USART3_CR2 USART_CR2(USART3_BASE)
#define UART4_CR2 USART_CR2(UART4_BASE)
#define UART5_CR2 USART_CR2(UART5_BASE)
/* Control register 3 (USARTx_CR3) */
#define USART_CR3(usart_base) MMIO32(usart_base + 0x14)
#define USART1_CR3 USART_CR3(USART1_BASE)
#define USART2_CR3 USART_CR3(USART2_BASE)
#define USART3_CR3 USART_CR3(USART3_BASE)
#define UART4_CR3 USART_CR3(UART4_BASE)
#define UART5_CR3 USART_CR3(UART5_BASE)
/* Guard time and prescaler register (USARTx_GTPR) */
#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18)
#define USART1_GTPR USART_GTPR(USART1_BASE)
#define USART2_GTPR USART_GTPR(USART2_BASE)
#define USART3_GTPR USART_GTPR(USART3_BASE)
#define UART4_GTPR USART_GTPR(UART4_BASE)
#define UART5_GTPR USART_GTPR(UART5_BASE)
/* --- USART_SR values ----------------------------------------------------- */
/****************************************************************************/
/** @defgroup usart_sr_flags USART Status register Flags
@ingroup STM32F_usart_defines
@{*/
/** CTS: CTS flag */
/** @note: undefined on UART4 and UART5 */
#define USART_SR_CTS (1 << 9)
/** LBD: LIN break detection flag */
#define USART_SR_LBD (1 << 8)
/** TXE: Transmit data buffer empty */
#define USART_SR_TXE (1 << 7)
/** TC: Transmission complete */
#define USART_SR_TC (1 << 6)
/** RXNE: Read data register not empty */
#define USART_SR_RXNE (1 << 5)
/** IDLE: Idle line detected */
#define USART_SR_IDLE (1 << 4)
/** ORE: Overrun error */
#define USART_SR_ORE (1 << 3)
/** NE: Noise error flag */
#define USART_SR_NE (1 << 2)
/** FE: Framing error */
#define USART_SR_FE (1 << 1)
/** PE: Parity error */
#define USART_SR_PE (1 << 0)
/**@}*/
/* --- USART_DR values ----------------------------------------------------- */
/* USART_DR[8:0]: DR[8:0]: Data value */
#define USART_DR_MASK 0x1FF
/* --- USART_BRR values ---------------------------------------------------- */
/* DIV_Mantissa[11:0]: mantissa of USARTDIV */
#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4)
/* DIV_Fraction[3:0]: fraction of USARTDIV */
#define USART_BRR_DIV_FRACTION_MASK 0xF
/* --- USART_CR1 values ---------------------------------------------------- */
/* UE: USART enable */
#define USART_CR1_UE (1 << 13)
/* M: Word length */
#define USART_CR1_M (1 << 12)
/* WAKE: Wakeup method */
#define USART_CR1_WAKE (1 << 11)
/* PCE: Parity control enable */
#define USART_CR1_PCE (1 << 10)
/* PS: Parity selection */
#define USART_CR1_PS (1 << 9)
/* PEIE: PE interrupt enable */
#define USART_CR1_PEIE (1 << 8)
/* TXEIE: TXE interrupt enable */
#define USART_CR1_TXEIE (1 << 7)
/* TCIE: Transmission complete interrupt enable */
#define USART_CR1_TCIE (1 << 6)
/* RXNEIE: RXNE interrupt enable */
#define USART_CR1_RXNEIE (1 << 5)
/* IDLEIE: IDLE interrupt enable */
#define USART_CR1_IDLEIE (1 << 4)
/* TE: Transmitter enable */
#define USART_CR1_TE (1 << 3)
/* RE: Receiver enable */
#define USART_CR1_RE (1 << 2)
/* RWU: Receiver wakeup */
#define USART_CR1_RWU (1 << 1)
/* SBK: Send break */
#define USART_CR1_SBK (1 << 0)
/* --- USART_CR2 values ---------------------------------------------------- */
/* LINEN: LIN mode enable */
#define USART_CR2_LINEN (1 << 14)
/* STOP[13:12]: STOP bits */
#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */
#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */
#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */
#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */
#define USART_CR2_STOPBITS_MASK (0x03 << 12)
#define USART_CR2_STOPBITS_SHIFT 12
/* CLKEN: Clock enable */
#define USART_CR2_CLKEN (1 << 11)
/* CPOL: Clock polarity */
#define USART_CR2_CPOL (1 << 10)
/* CPHA: Clock phase */
#define USART_CR2_CPHA (1 << 9)
/* LBCL: Last bit clock pulse */
#define USART_CR2_LBCL (1 << 8)
/* LBDIE: LIN break detection interrupt enable */
#define USART_CR2_LBDIE (1 << 6)
/* LBDL: LIN break detection length */
#define USART_CR2_LBDL (1 << 5)
/* ADD[3:0]: Address of the usart node */
#define USART_CR2_ADD_MASK 0xF
/* --- USART_CR3 values ---------------------------------------------------- */
/* CTSIE: CTS interrupt enable */
/* Note: N/A on UART4 & UART5 */
#define USART_CR3_CTSIE (1 << 10)
/* CTSE: CTS enable */
/* Note: N/A on UART4 & UART5 */
#define USART_CR3_CTSE (1 << 9)
/* RTSE: RTS enable */
/* Note: N/A on UART4 & UART5 */
#define USART_CR3_RTSE (1 << 8)
/* DMAT: DMA enable transmitter */
/* Note: N/A on UART5 */
#define USART_CR3_DMAT (1 << 7)
/* DMAR: DMA enable receiver */
/* Note: N/A on UART5 */
#define USART_CR3_DMAR (1 << 6)
/* SCEN: Smartcard mode enable */
/* Note: N/A on UART4 & UART5 */
#define USART_CR3_SCEN (1 << 5)
/* NACK: Smartcard NACK enable */
/* Note: N/A on UART4 & UART5 */
#define USART_CR3_NACK (1 << 4)
/* HDSEL: Half-duplex selection */
#define USART_CR3_HDSEL (1 << 3)
/* IRLP: IrDA low-power */
#define USART_CR3_IRLP (1 << 2)
/* IREN: IrDA mode enable */
#define USART_CR3_IREN (1 << 1)
/* EIE: Error interrupt enable */
#define USART_CR3_EIE (1 << 0)
/* --- USART_GTPR values --------------------------------------------------- */
/* GT[7:0]: Guard time value */
/* Note: N/A on UART4 & UART5 */
#define USART_GTPR_GT_MASK (0xFF << 8)
/* PSC[7:0]: Prescaler value */
/* Note: N/A on UART4/5 */
#define USART_GTPR_PSC_MASK 0xFF
/* TODO */ /* Note to Uwe: what needs to be done here? */
#endif
/** @cond */
#else
#warning "usart_common_all.h should not be included directly, only via usart.h"
#endif
/** @endcond */
/**@}*/

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/** @addtogroup usart_defines
@author @htmlonly &copy; @endhtmlonly 2011 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
* Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H
The order of header inclusion is important. usart.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_USART_H
/** @endcond */
#ifndef LIBOPENCM3_USART_COMMON_F24_H
#define LIBOPENCM3_USART_COMMON_F24_H
#include <libopencm3/stm32/common/usart_common_f124.h>
/* --- Convenience macros -------------------------------------------------- */
#define USART6 USART6_BASE
/* --- USART registers ----------------------------------------------------- */
/* Status register (USARTx_SR) */
#define USART6_SR USART_SR(USART6_BASE)
/* Data register (USARTx_DR) */
#define USART6_DR USART_DR(USART6_BASE)
/* Baud rate register (USARTx_BRR) */
#define USART6_BRR USART_BRR(USART6_BASE)
/* Control register 1 (USARTx_CR1) */
#define USART6_CR1 USART_CR1(USART6_BASE)
/* Control register 2 (USARTx_CR2) */
#define USART6_CR2 USART_CR2(USART6_BASE)
/* Control register 3 (USARTx_CR3) */
#define USART6_CR3 USART_CR3(USART6_BASE)
/* Guard time and prescaler register (USARTx_GTPR) */
#define USART6_GTPR USART_GTPR(USART6_BASE)
/* --- USART_CR1 values ---------------------------------------------------- */
/* OVER8: Oversampling mode */
#define USART_CR1_OVER8 (1 << 15)
/* --- USART_CR3 values ---------------------------------------------------- */
/* ONEBIT: One sample bit method enable */
#define USART_CR3_ONEBIT (1 << 11)
#endif
/** @cond */
#else
#warning "usart_common_f24.h should not be included directly, only via usart.h"
#endif
/** @endcond */

25
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/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(STM32F0)
# include <libopencm3/stm32/f0/comparator.h>
#else
# error "stm32 family not defined."
#endif

35
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/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(STM32F0)
# include <libopencm3/stm32/f0/crc.h>
#elif defined(STM32F1)
# include <libopencm3/stm32/f1/crc.h>
#elif defined(STM32F2)
# include <libopencm3/stm32/f2/crc.h>
#elif defined(STM32F3)
# include <libopencm3/stm32/f3/crc.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/crc.h>
#elif defined(STM32L1)
# include <libopencm3/stm32/l1/crc.h>
#else
# error "stm32 family not defined."
#endif

27
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/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(STM32F2)
# include <libopencm3/stm32/f2/crypto.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/crypto.h>
#else
# error "CRYPTO processor is supported only" \
"in stm32f2xx, stm32f41xx, stm32f42xx and stm32f43xx family."
#endif

34
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/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(STM32F0)
# include <libopencm3/stm32/f0/dac.h>
#elif defined(STM32F1)
# include <libopencm3/stm32/f1/dac.h>
#elif defined(STM32F2)
# include <libopencm3/stm32/f2/dac.h>
#elif defined(STM32F3)
# include <libopencm3/stm32/f3/dac.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/dac.h>
#elif defined(STM32L1)
# include <libopencm3/stm32/l1/dac.h>
#else
# error "stm32 family not defined."
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_STM32_DBGMCU_H
#define LIBOPENCM3_STM32_DBGMCU_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- DBGMCU registers ---------------------------------------------------- */
/* Debug MCU IDCODE register (DBGMCU_IDCODE) */
#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00)
/* Debug MCU configuration register (DBGMCU_CR) */
/* Note: Only 32bit access supported. */
#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04)
/* --- DBGMCU_IDCODE values ------------------------------------------------ */
#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff
#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000
/* --- DBGMCU_CR values ---------------------------------------------------- */
/* Bit 31: Reserved. */
/* Bits [24:22]: Reserved, must be kept cleared. */
/* Bits [4:3]: Reserved. */
#define DBGMCU_CR_SLEEP 0x00000001
#define DBGMCU_CR_STOP 0x00000002
#define DBGMCU_CR_STANDBY 0x00000004
#define DBGMCU_CR_TRACE_IOEN 0x00000020
#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0
#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000
#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040
#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080
#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0
#define DBGMCU_CR_IWDG_STOP 0x00000100
#define DBGMCU_CR_WWDG_STOP 0x00000200
#define DBGMCU_CR_TIM1_STOP 0x00000400
#define DBGMCU_CR_TIM2_STOP 0x00000800
#define DBGMCU_CR_TIM3_STOP 0x00001000
#define DBGMCU_CR_TIM4_STOP 0x00002000
#define DBGMCU_CR_CAN1_STOP 0x00004000
#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000
#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000
#define DBGMCU_CR_TIM8_STOP 0x00020000
#define DBGMCU_CR_TIM5_STOP 0x00040000
#define DBGMCU_CR_TIM6_STOP 0x00080000
#define DBGMCU_CR_TIM7_STOP 0x00100000
#define DBGMCU_CR_CAN2_STOP 0x00200000
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_DESIG_H
#define LIBOPENCM3_DESIG_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- Device Electronic Signature -------------------------------- */
/* Flash size register */
#define DESIG_FLASH_SIZE MMIO16(DESIG_FLASH_SIZE_BASE + 0x00)
/* Unique ID register (96 bits) */
/* Note: ST says these may be accessed in any width if you choose */
#define DESIG_UID_15_0 MMIO16(DESIG_UNIQUE_ID_BASE + 0x00)
/* Listed as "This field value is also reserved for a future feature" WTH?! */
#define DESIG_UID_31_16 MMIO16(DESIG_UNIQUE_ID_BASE + 0x02)
#define DESIG_UID_63_32 MMIO32(DESIG_UNIQUE_ID_BASE + 0x04)
#define DESIG_UID_95_64 MMIO32(DESIG_UNIQUE_ID_BASE + 0x08)
BEGIN_DECLS
/**
* Read the on board flash size
* @return flash size in KB
*/
uint16_t desig_get_flash_size(void);
/**
* Read the full 96 bit unique identifier
* Note: ST specifies that bits 31..16 are _also_ reserved for future use
* @param result pointer to at least 3xuint32_ts (96 bits)
*/
void desig_get_unique_id(uint32_t result[]);
/**
* Read the full 96 bit unique identifier and return it as a
* zero-terminated string
* @param string memory region to write the result to
8 @param string_len the size of string in bytes
*/
void desig_get_unique_id_as_string(char *string,
unsigned int string_len);
END_DECLS
#endif

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/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(STM32F0)
# include <libopencm3/stm32/f0/dma.h>
#elif defined(STM32F1)
# include <libopencm3/stm32/f1/dma.h>
#elif defined(STM32F2)
# include <libopencm3/stm32/f2/dma.h>
#elif defined(STM32F3)
# include <libopencm3/stm32/f3/dma.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/dma.h>
#elif defined(STM32L1)
# include <libopencm3/stm32/l1/dma.h>
#else
# error "stm32 family not defined."
#endif

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/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Piotr Esden-Tempski <piotr@esden.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(STM32F0)
# include <libopencm3/stm32/f0/exti.h>
#elif defined(STM32F1)
# include <libopencm3/stm32/f1/exti.h>
#elif defined(STM32F2)
# include <libopencm3/stm32/f2/exti.h>
#elif defined(STM32F3)
# include <libopencm3/stm32/f3/exti.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/exti.h>
#elif defined(STM32L1)
# include <libopencm3/stm32/l1/exti.h>
#else
# error "stm32 family not defined."
#endif

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/** @defgroup adc_defines ADC Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx Analog to Digital
* Converter</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_ADC_H
#define LIBOPENCM3_ADC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/memorymap.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
/** @defgroup adc_reg_base ADC register base addresses
* @ingroup adc_defines
*
*@{*/
#define ADC ADC_BASE
#define ADC1 ADC_BASE/* for API compatibility */
/**@}*/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
/* ADC interrupt and status register */
#define ADC_ISR(base) MMIO32(base + 0x00)
#define ADC1_ISR ADC_ISR(ADC)
/* Interrupt Enable Register */
#define ADC_IER(base) MMIO32(base + 0x04)
#define ADC1_IER ADC_IER(ADC)
/* Control Register */
#define ADC_CR(base) MMIO32(base + 0x08)
#define ADC1_CR ADC_CR(ADC)
/* Configuration Register 1 */
#define ADC_CFGR1(base) MMIO32(base + 0x0C)
#define ADC1_CFGR1 ADC_CFGR1(ADC)
/* Configuration Register 2 */
#define ADC_CFGR2(base) MMIO32(base + 0x10)
#define ADC1_CFGR2 ADC_CFGR2(ADC)
/* Sample Time Register 1 */
#define ADC_SMPR(base) MMIO32(base + 0x14)
#define ADC1_SMPR ADC_SMPR(ADC)
/* Watchdog Threshold Register */
#define ADC_TR(base) MMIO32(base + 0x20)
#define ADC1_TR ADC_TR(ADC)
/* Channel Select Register */
#define ADC_CHSELR(base) MMIO32(base + 0x28)
#define ADC1_CHSELR ADC_CHSELR(ADC)
/* Regular Data Register */
#define ADC_DR(base) MMIO32(base + 0x40)
#define ADC1_DR ADC_DR(ADC)
/* Regular Data Register */
#define ADC_CCR MMIO32(ADC_BASE + 0x308)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* ADC_ISR Values -----------------------------------------------------------*/
#define ADC_ISR_AWD (1 << 7)
#define ADC_ISR_OVR (1 << 4)
#define ADC_ISR_EOSEQ (1 << 3)
#define ADC_ISR_EOC (1 << 2)
#define ADC_ISR_EOSMP (1 << 1)
#define ADC_ISR_ADRDY (1 << 0)
/* ADC_IER Values -----------------------------------------------------------*/
#define ADC_IER_AWDIE (1 << 7)
#define ADC_IER_OVRIE (1 << 4)
#define ADC_IER_EOSEQIE (1 << 3)
#define ADC_IER_EOCIE (1 << 2)
#define ADC_IER_EOSMPIE (1 << 1)
#define ADC_IER_ADRDYIE (1 << 0)
/* ADC_CR Values ------------------------------------------------------------*/
#define ADC_CR_ADCAL (1 << 31)
#define ADC_CR_ADSTP (1 << 4)
#define ADC_CR_ADSTART (1 << 2)
#define ADC_CR_ADDIS (1 << 1)
#define ADC_CR_ADEN (1 << 0)
/* ADC_CFGR1 Values ---------------------------------------------------------*/
#define ADC_CFGR1_AWDCH_SHIFT 26
#define ADC_CFGR1_AWDCH (0x1F << ADC_CFGR1_AWDCH_SHIFT)
#define ADC_CFGR1_AWDCH_VAL(x) ((x) << ADC_CFGR1_AWDCH_SHIFT)
#define ADC_CFGR1_AWDEN (1 << 23)
#define ADC_CFGR1_AWDSGL (1 << 22)
#define ADC_CFGR1_DISCEN (1 << 16)
#define ADC_CFGR1_AUTOFF (1 << 15)
#define ADC_CFGR1_WAIT (1 << 14)
#define ADC_CFGR1_CONT (1 << 13)
#define ADC_CFGR1_OVRMOD (1 << 12)
#define ADC_CFGR1_EXTEN_SHIFT 10
#define ADC_CFGR1_EXTEN (3 << ADC_CFGR1_EXTEN_SHIFT)
#define ADC_CFGR1_EXTEN_DISABLE (0 << ADC_CFGR1_EXTEN_SHIFT)
#define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT)
#define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT)
#define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT)
#define ADC_CFGR1_EXTSEL_SHIFT 6
#define ADC_CFGR1_EXTSEL (7 << ADC_CFGR1_EXTSEL_SHIFT)
#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
#define ADC_CFGR1_ALIGN (1 << 5)
#define ADC_CFGR1_RES_SHIFT 3
#define ADC_CFGR1_RES (3 << ADC_CFGR1_RES_SHIFT)
#define ADC_CFGR1_RES_12_BIT (0 << ADC_CFGR1_RES_SHIFT)
#define ADC_CFGR1_RES_10_BIT (1 << ADC_CFGR1_RES_SHIFT)
#define ADC_CFGR1_RES_8_BIT (2 << ADC_CFGR1_RES_SHIFT)
#define ADC_CFGR1_RES_6_BIT (3 << ADC_CFGR1_RES_SHIFT)
#define ADC_CFGR1_SCANDIR (1 << 2)
#define ADC_CFGR1_DMACFG (1 << 1)
#define ADC_CFGR1_DMAEN (1 << 0)
/* ADC_CFGR2 Values ---------------------------------------------------------*/
#define ADC_CFGR2_CKMODE_SHIFT 30
#define ADC_CFGR2_CKMODE (3 << ADC_CFGR2_CKMODE_SHIFT)
#define ADC_CFGR2_CKMODE_CK_ADC (0 << ADC_CFGR2_CKMODE_SHIFT)
#define ADC_CFGR2_CKMODE_PCLK_DIV2 (1 << ADC_CFGR2_CKMODE_SHIFT)
#define ADC_CFGR2_CKMODE_PCLK_DIV4 (2 << ADC_CFGR2_CKMODE_SHIFT)
/* ADC_SMPR Values ----------------------------------------------------------*/
#define ADC_SMPR_SMP_SHIFT 0
#define ADC_SMPR_SMP (7 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMP_001DOT5 (0 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMP_007DOT5 (1 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMP_013DOT5 (2 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMP_028DOT5 (3 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMP_041DOT5 (4 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMP_055DOT5 (5 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMP_071DOT5 (6 << ADC_SMPR_SMP_SHIFT)
#define ADC_SMPR_SMP_239DOT5 (7 << ADC_SMPR_SMP_SHIFT)
/* ADC_TR Values ------------------------------------------------------------*/
#define ADC_TR_LT_SHIFT 0
#define ADC_TR_LT (0xFFF << ADC_TR_LT_SHIFT)
#define ADC_TR_LT_VAL(x) ((x) << ADC_TR_LT_SHIFT)
#define ADC_TR_HT_SHIFT 16
#define ADC_TR_HT (0xFFF << ADC_TR_HT_SHIFT)
#define ADC_TR_HT_VAL(x) ((x) << ADC_TR_HT_SHIFT)
/* ADC_CHSELR Values --------------------------------------------------------*/
#define ADC_CHSELR_CHSEL(x) (1 << (x))
/* ADC_DR Values ------------------------------------------------------------*/
#define ADC_DR_DATA 0xFFFF
/* ADC_CCR Values -----------------------------------------------------------*/
#define ADC_CCR_VBATEN (1 << 24)
#define ADC_CCR_TSEN (1 << 23)
#define ADC_CCR_VREFEN (1 << 22)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/** @defgroup adc_api_res ADC resolutions
* @ingroup adc_defines
*
*@{*/
#define ADC_RESOLUTION_12BIT ADC_CFGR1_RES_12_BIT
#define ADC_RESOLUTION_10BIT ADC_CFGR1_RES_10_BIT
#define ADC_RESOLUTION_8BIT ADC_CFGR1_RES_8_BIT
#define ADC_RESOLUTION_6BIT ADC_CFGR1_RES_6_BIT
/**@}*/
/** @defgroup adc_api_smptime ADC sampling time
* @ingroup adc_defines
*
*@{*/
#define ADC_SMPTIME_001DOT5 ADC_SMPR_SMP_001DOT5
#define ADC_SMPTIME_007DOT5 ADC_SMPR_SMP_007DOT5
#define ADC_SMPTIME_013DOT5 ADC_SMPR_SMP_013DOT5
#define ADC_SMPTIME_028DOT5 ADC_SMPR_SMP_028DOT5
#define ADC_SMPTIME_041DOT5 ADC_SMPR_SMP_041DOT5
#define ADC_SMPTIME_055DOT5 ADC_SMPR_SMP_055DOT5
#define ADC_SMPTIME_071DOT5 ADC_SMPR_SMP_071DOT5
#define ADC_SMPTIME_239DOT5 ADC_SMPR_SMP_239DOT5
/**@}*/
/** @defgroup adc_api_clksource ADC clock source
* @ingroup adc_defines
*
*@{*/
#define ADC_CLKSOURCE_ADC ADC_CFGR2_CKMODE_CK_ADC
#define ADC_CLKSOURCE_PCLK_DIV2 ADC_CFGR2_CKMODE_PCLK_DIV2
#define ADC_CLKSOURCE_PCLK_DIV4 ADC_CFGR2_CKMODE_PCLK_DIV4
/**@}*/
/** @defgroup adc_channel ADC Channel Numbers
* @ingroup adc_defines
*
*@{*/
#define ADC_CHANNEL0 0x00
#define ADC_CHANNEL1 0x01
#define ADC_CHANNEL2 0x02
#define ADC_CHANNEL3 0x03
#define ADC_CHANNEL4 0x04
#define ADC_CHANNEL5 0x05
#define ADC_CHANNEL6 0x06
#define ADC_CHANNEL7 0x07
#define ADC_CHANNEL8 0x08
#define ADC_CHANNEL9 0x09
#define ADC_CHANNEL10 0x0A
#define ADC_CHANNEL11 0x0B
#define ADC_CHANNEL12 0x0C
#define ADC_CHANNEL13 0x0D
#define ADC_CHANNEL14 0x0E
#define ADC_CHANNEL15 0x0F
#define ADC_CHANNEL_TEMP 0x10
#define ADC_CHANNEL_VREF 0x11
#define ADC_CHANNEL_VBAT 0x12
/**@}*/
/** @defgroup adc_api_opmode ADC Operation Modes
* @ingroup adc_defines
*
*@{*/
enum adc_opmode {
ADC_MODE_SEQUENTIAL,
ADC_MODE_SCAN,
ADC_MODE_SCAN_INFINITE,
};
/**@}*/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
/* Operation mode API */
void adc_set_continuous_conversion_mode(uint32_t adc);
void adc_set_single_conversion_mode(uint32_t adc);
void adc_enable_discontinuous_mode(uint32_t adc);
void adc_disable_discontinuous_mode(uint32_t adc);
void adc_set_operation_mode(uint32_t adc, enum adc_opmode opmode);
/* Trigger API */
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
uint32_t polarity);
void adc_disable_external_trigger_regular(uint32_t adc);
/* Conversion API */
void adc_start_conversion_regular(uint32_t adc);
bool adc_eoc(uint32_t adc);
uint32_t adc_read_regular(uint32_t adc);
/* Interrupt configuration */
void adc_enable_watchdog_interrupt(uint32_t adc);
void adc_disable_watchdog_interrupt(uint32_t adc);
bool adc_get_watchdog_flag(uint32_t adc);
void adc_clear_watchdog_flag(uint32_t adc);
void adc_enable_overrun_interrupt(uint32_t adc);
void adc_disable_overrun_interrupt(uint32_t adc);
bool adc_get_overrun_flag(uint32_t adc);
void adc_clear_overrun_flag(uint32_t adc);
void adc_enable_eoc_sequence_interrupt(uint32_t adc);
void adc_disable_eoc_sequence_interrupt(uint32_t adc);
bool adc_get_eoc_sequence_flag(uint32_t adc);
void adc_enable_eoc_interrupt(uint32_t adc);
void adc_disable_eoc_interrupt(uint32_t adc);
/* Basic configuration */
void adc_power_off(uint32_t adc);
void adc_power_on(uint32_t adc);
void adc_set_clk_source(uint32_t adc, uint32_t source);
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
void adc_set_resolution(uint32_t adc, uint16_t resolution);
void adc_set_left_aligned(uint32_t adc);
void adc_set_right_aligned(uint32_t adc);
void adc_enable_dma(uint32_t adc);
void adc_disable_dma(uint32_t adc);
void adc_enable_temperature_sensor(void);
void adc_disable_temperature_sensor(void);
void adc_enable_vref_sensor(void);
void adc_disable_vref_sensor(void);
void adc_enable_vbat_sensor(void);
void adc_disable_vbat_sensor(void);
void adc_calibrate_start(uint32_t adc);
void adc_calibrate_wait_finish(uint32_t adc);
/* Analog Watchdog */
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan);
void adc_disable_analog_watchdog(uint32_t adc);
void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold);
void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold);
END_DECLS
#endif

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/** @defgroup CEC_defines CEC Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx HDMI-CEC</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CEC_H
#define LIBOPENCM3_CEC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/memorymap.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
#define CEC CEC_BASE
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define CEC_CR MMIO32(CEC_BASE + 0x00)
#define CEC_CFGR MMIO32(CEC_BASE + 0x04)
#define CEC_TXDR MMIO32(CEC_BASE + 0x08)
#define CEC_RXDR MMIO32(CEC_BASE + 0x0c)
#define CEC_ISR MMIO32(CEC_BASE + 0x10)
#define CEC_IER MMIO32(CEC_BASE + 0x14)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* CEC_CR Values ------------------------------------------------------------*/
#define CEC_CR_TXEOM (1 << 2)
#define CEC_CR_TXSOM (1 << 1)
#define CEC_CR_CECEN (1 << 0)
/* CEC_CFGR Values ----------------------------------------------------------*/
#define CEC_CFGR_LSTN (1 << 31)
#define CEC_CFGR_OAR_SHIFT 16
#define CEC_CFGR_OAR (0x3FFF << CEC_CFGR_OAR_SHIFT)
#define CEC_CFGR_SFTOPT (1 << 8)
#define CEC_CFGR_BRDNOGEN (1 << 7)
#define CEC_CFGR_LBPEGEN (1 << 6)
#define CEC_CFGR_BREGEN (1 << 5)
#define CEC_CFGR_BRESTP (1 << 4)
#define CEC_CFGR_RXTOL (1 << 3)
#define CEC_CFGR_SFT_SHIFT 0
#define CEC_CFGR_SFT (7 >> CEC_CFGR_SFT_SHIFT)
/* CEC_ISR Values -----------------------------------------------------------*/
#define CEC_ISR_TXACKE (1 << 12)
#define CEC_ISR_TXERR (1 << 11)
#define CEC_ISR_TXUDR (1 << 10)
#define CEC_ISR_TXEND (1 << 9)
#define CEC_ISR_TXBR (1 << 8)
#define CEC_ISR_ARBLST (1 << 7)
#define CEC_ISR_RXACKE (1 << 6)
#define CEC_ISR_LBPE (1 << 5)
#define CEC_ISR_SBPE (1 << 4)
#define CEC_ISR_BRE (1 << 3)
#define CEC_ISR_RXOVR (1 << 2)
#define CEC_ISR_RXEND (1 << 1)
#define CEC_ISR_RXBR (1 << 0)
/* CEC_IER Values -----------------------------------------------------------*/
#define CEC_IER_TXACKIE (1 << 12)
#define CEC_IER_TXERRIE (1 << 11)
#define CEC_IER_TXUDRIE (1 << 10)
#define CEC_IER_TXENDIE (1 << 9)
#define CEC_IER_TXBRIE (1 << 8)
#define CEC_IER_ARBLSTIE (1 << 7)
#define CEC_IER_RXACKIE (1 << 6)
#define CEC_IER_LBPEIE (1 << 5)
#define CEC_IER_SBPEIE (1 << 4)
#define CEC_IER_BREIE (1 << 3)
#define CEC_IER_RXOVRIE (1 << 2)
#define CEC_IER_RXENDIE (1 << 1)
#define CEC_IER_RXBRIE (1 << 0)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
END_DECLS
#endif

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/** @defgroup comp_defines COMP Defines
*
* @brief <b>libopencm3 Defined Constants and Types for the STM32F0xx
* Comparator module</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 29 Jun 2013
*
*LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_COMP_H
#define LIBOPENCM3_COMP_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/memorymap.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
#define COMP1 0
#define COMP2 1
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define COMP_CSR(i) MMIO16(SYSCFG_COMP_BASE + 0x1c + (i)*2)
#define COMP_CSR1 COMP_CSR(COMP1)
#define COMP_CSR2 COMP_CSR(COMP2)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* COMP_CSR Values ----------------------------------------------------------*/
#define COMP_CSR_LOCK (1 << 15)
#define COMP_CSR_OUT (1 << 14)
#define COMP_CSR_HYST_SHIFT 12
#define COMP_CSR_HYST (3 << COMP_CSR_HYST_SHIFT)
#define COMP_CSR_HYST_NO (0 << COMP_CSR_HYST_SHIFT)
#define COMP_CSR_HYST_LOW (1 << COMP_CSR_HYST_SHIFT)
#define COMP_CSR_HYST_MED (2 << COMP_CSR_HYST_SHIFT)
#define COMP_CSR_HYST_HIGH (3 << COMP_CSR_HYST_SHIFT)
#define COMP_CSR_POL (1 << 11)
#define COMP_CSR_OUTSEL_SHIFT 8
#define COMP_CSR_OUTSEL (7 << COMP_CSR_OUTSEL_SHIFT)
#define COMP_CSR_OUTSEL_NONE (0 << COMP_CSR_OUTSEL_SHIFT)
#define COMP_CSR_OUTSEL_TIM1_BRK (1 << COMP_CSR_OUTSEL_SHIFT)
#define COMP_CSR_OUTSEL_TIM1_IC1 (2 << COMP_CSR_OUTSEL_SHIFT)
#define COMP_CSR_OUTSEL_TIM1_OCRCLR (3 << COMP_CSR_OUTSEL_SHIFT)
#define COMP_CSR_OUTSEL_TIM2_IC4 (4 << COMP_CSR_OUTSEL_SHIFT)
#define COMP_CSR_OUTSEL_TIM2_OCRCLR (5 << COMP_CSR_OUTSEL_SHIFT)
#define COMP_CSR_OUTSEL_TIM3_IC1 (6 << COMP_CSR_OUTSEL_SHIFT)
#define COMP_CSR_OUTSEL_TIM3_OCRCLR (7 << COMP_CSR_OUTSEL_SHIFT)
#define COMP_CSR_WINDWEN (1 << 23)
#define COMP_CSR_INSEL_SHIFT 4
#define COMP_CSR_INSEL (7 << COMP_CSR_INSEL_SHIFT)
#define COMP_CSR_INSEL_1_4_VREFINT (0 << COMP_CSR_INSEL_SHIFT)
#define COMP_CSR_INSEL_2_4_VREFINT (1 << COMP_CSR_INSEL_SHIFT)
#define COMP_CSR_INSEL_3_4_VREFINT (2 << COMP_CSR_INSEL_SHIFT)
#define COMP_CSR_INSEL_4_4_VREFINT (3 << COMP_CSR_INSEL_SHIFT)
#define COMP_CSR_INSEL_VREFINT (3 << COMP_CSR_INSEL_SHIFT)
#define COMP_CSR_INSEL_INM4 (4 << COMP_CSR_INSEL_SHIFT)
#define COMP_CSR_INSEL_INM5 (5 << COMP_CSR_INSEL_SHIFT)
#define COMP_CSR_INSEL_INM6 (6 << COMP_CSR_INSEL_SHIFT)
#define COMP_CSR_SPEED_SHIFT 2
#define COMP_CSR_SPEED (3 << COMP_CSR_SPEED_SHIFT)
#define COMP_CSR_SPEED_HIGH (0 << COMP_CSR_SPEED_SHIFT)
#define COMP_CSR_SPEED_MED (1 << COMP_CSR_SPEED_SHIFT)
#define COMP_CSR_SPEED_LOW (2 << COMP_CSR_SPEED_SHIFT)
#define COMP_CSR_SPEED_VERYLOW (3 << COMP_CSR_SPEED_SHIFT)
#define COMP_CSR_SW1 (1 << 1)
#define COMP_CSR_EN (1 << 0)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
void comp_enable(uint8_t id);
void comp_disable(uint8_t id);
void comp_select_input(uint8_t id, uint32_t input);
void comp_select_output(uint8_t id, uint32_t output);
void comp_select_hyst(uint8_t id, uint32_t hyst);
void comp_select_speed(uint8_t id, uint32_t speed);
END_DECLS
#endif

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/** @defgroup crc_defines CRC Defines
*
* @brief <b>libopencm3 Defined Constants and Types for the STM32F1xx CRC
* Generator </b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 29 Jun 2013
*
*LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CRC_H
#define LIBOPENCM3_CRC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/crc_common_all.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
#define CRC_CR_REV_OUT (1 << 7)
#define CRC_CR_REV_IN_SHIFT 5
#define CRC_CR_REV_IN (3 << CRC_CR_REV_IN_SHIFT)
#define CRC_CR_REV_IN_NONE (0 << CRC_CR_REV_IN_SHIFT)
#define CRC_CR_REV_IN_BYTE (1 << CRC_CR_REV_IN_SHIFT)
#define CRC_CR_REV_IN_HALF (2 << CRC_CR_REV_IN_SHIFT)
#define CRC_CR_REV_IN_WORD (3 << CRC_CR_REV_IN_SHIFT)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
END_DECLS
#endif

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/** @defgroup dac_defines DAC Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx Digital to Analog
* Converter</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_DAC_H
#define LIBOPENCM3_DAC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/memorymap.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
#define DAC DAC_BASE
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define DAC_CR MMIO32(DAC_BASE + 0x00)
#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04)
#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08)
#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C)
#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10)
#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C)
#define DAC_SR MMIO32(DAC_BASE + 0x34)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* DAC_CR Values ------------------------------------------------------------*/
#define DAC_CR_DMAUDRIE1 (1 << 13)
#define DAC_CR_DMAEN1 (1 << 12)
#define DAC_CR_TSEL1_SHIFT 3
#define DAC_CR_TSEL1 (7 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_TIM6_TRGO (0 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_TIM8_TRGO (1 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_TIM7_TRGO (2 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_TIM5_TRGO (3 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_TIM2_TRGO (4 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_TIM4_TRGO (5 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_EXT_9 (6 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_SWTRG (7 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TEN1 (1 << 2)
#define DAC_CR_BOFF1 (1 << 1)
#define DAC_CR_EN1 (1 << 0)
/* DAC_SWTRIGR Values -------------------------------------------------------*/
#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
/* DAC_DHR12R1 Values -------------------------------------------------------*/
#define DAC_DHR12R1_DACC1DHR 0xFFF
/* DAC_DHR12L1 Values -------------------------------------------------------*/
#define DAC_DHR12L1_DACC1DHR (0xFFF << 4)
/* DAC_DHR8R1 Values --------------------------------------------------------*/
#define DAC_DHR8R1_DACC1DHR 0xFF
/* DAC_DOR1 Values ----------------------------------------------------------*/
#define DAC_DOR1_DACC1DOR 0xFFF
/* DAC_SR Values ------------------------------------------------------------*/
#define DAC_SR_DMAUDR1 (1 << 13)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
END_DECLS
#endif

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/** @defgroup dma_defines DMA Defines
*
* @ingroup STM32F0xx_defines
*
* @brief Defined Constants and Types for the STM32F0xx DMA Controller
*
* @version 1.0.0
*
* @date 10 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/dma_common_l1f013.h>
#endif

32
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/** @mainpage libopencm3 STM32F0
*
* @version 1.0.0
*
* @date 11 July 2013
*
* API documentation for ST Microelectronics STM32F0 Cortex M0 series.
*
* LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F0xx STM32F0xx
* Libraries for ST Microelectronics STM32F0xx series.
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F0xx_defines STM32F0xx Defines
*
* @brief Defined Constants and Types for the STM32F0xx series
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/

39
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/** @defgroup exti_defines EXTI Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx External Interrupts
* </b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_EXTI_H
#define LIBOPENCM3_EXTI_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/exti_common_all.h>
#endif

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/** @defgroup flash_defines FLASH Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx Flash memory</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_FLASH_H
#define LIBOPENCM3_FLASH_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C)
#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_ACR_PRFTBS (1 << 5)
#define FLASH_ACR_PRFTBE (1 << 4)
#define FLASH_ACR_LATENCY_SHIFT 0
#define FLASH_ACR_LATENCY 7
#define FLASH_ACR_LATENCY_000_024MHZ 0
#define FLASH_ACR_LATENCY_024_048MHZ 1
#define FLASH_ACR_LATENCY_0WS 0
#define FLASH_ACR_LATENCY_1WS 1
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_SR_EOP (1 << 5)
#define FLASH_SR_WRPRTERR (1 << 4)
#define FLASH_SR_PGERR (1 << 2)
#define FLASH_SR_BSY (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_CR_OBL_LAUNCH (1 << 13)
#define FLASH_CR_EOPIE (1 << 12)
#define FLASH_CR_ERRIE (1 << 10)
#define FLASH_CR_OPTWRE (1 << 9)
#define FLASH_CR_LOCK (1 << 7)
#define FLASH_CR_STRT (1 << 6)
#define FLASH_CR_OPTER (1 << 5)
#define FLASH_CR_OPTPG (1 << 4)
#define FLASH_CR_MER (1 << 2)
#define FLASH_CR_PER (1 << 1)
#define FLASH_CR_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
#define FLASH_OBR_DATA1_SHIFT 24
#define FLASH_OBR_DATA1 (0xFF << FLASH_OBR_DATA1_SHIFT)
#define FLASH_OBR_DATA0_SHIFT 16
#define FLASH_OBR_DATA0 (0xFF << FLASH_OBR_DATA0_SHIFT)
#define FLASH_OBR_RAM_PARITY_CHECK (1 << 14)
#define FLASH_OBR_VDDA_MONITOR (1 << 13)
#define FLASH_OBR_NBOOT1 (1 << 12)
#define FLASH_OBR_NRST_STDBY (1 << 10)
#define FLASH_OBR_NRST_STOP (1 << 9)
#define FLASH_OBR_WDG_SW (1 << 8)
#define FLASH_OBR_RDPRT_SHIFT 1
#define FLASH_OBR_RDPRT (3 << FLASH_OBR_RDPRT_SHIFT)
#define FLASH_OBR_RDPRT_L0 (0 << FLASH_OBR_RDPRT_SHIFT)
#define FLASH_OBR_RDPRT_L1 (1 << FLASH_OBR_RDPRT_SHIFT)
#define FLASH_OBR_RDPRT_L2 (2 << FLASH_OBR_RDPRT_SHIFT)
#define FLASH_OBR_OPTERR (1 << 0)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
#define FLASH_RDP_L0 ((uint8_t)0xaa)
#define FLASH_RDP_L1 ((uint8_t)0xf0) /* any value */
#define FLASH_RDP_L2 ((uint8_t)0xcc)
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
void flash_prefetch_buffer_enable(void);
void flash_prefetch_buffer_disable(void);
void flash_set_ws(uint32_t ws);
void flash_wait_busy(void);
void flash_program_u32(uint32_t address, uint32_t data);
void flash_program_u16(uint32_t address, uint16_t data);
void flash_erase_page(uint32_t page_address);
void flash_erase_all_pages(void);
END_DECLS
#endif

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/** @defgroup gpio_defines GPIO Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx General Purpose I/O</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 1 July 2012
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/gpio_common_f24.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define GPIO_BRR(port) MMIO32(port + 0x24)
#define GPIOA_BRR GPIO_BRR(GPIOA)
#define GPIOB_BRR GPIO_BRR(GPIOB)
#define GPIOC_BRR GPIO_BRR(GPIOC)
#define GPIOD_BRR GPIO_BRR(GPIOD)
#define GPIOF_BRR GPIO_BRR(GPIOF)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/** @defgroup gpio_speed GPIO Output Pin Speed
@ingroup gpio_defines
@{*/
#define GPIO_OSPEED_LOW 0x0
#define GPIO_OSPEED_MED 0x1
#define GPIO_OSPEED_HIGH 0x3
/**@}*/
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
END_DECLS
#endif

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/** @defgroup i2c_defines I2C Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx I2C</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_I2C_H
#define LIBOPENCM3_I2C_H
#include <libopencm3/cm3/common.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
#define I2C1 I2C1_BASE
#define I2C2 I2C2_BASE
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
#define I2C1_CR1 I2C_CR1(I2C1)
#define I2C2_CR1 I2C_CR1(I2C2)
#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
#define I2C1_CR2 I2C_CR2(I2C1)
#define I2C2_CR2 I2C_CR2(I2C2)
#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
#define I2C1_OAR1 I2C_OAR1(I2C1)
#define I2C2_OAR1 I2C_OAR1(I2C2)
#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
#define I2C1_OAR2 I2C_OAR2(I2C1)
#define I2C2_OAR2 I2C_OAR2(I2C2)
#define I2C_TIMINGR(i2c_base) MMIO32(i2c_base + 0x10)
#define I2C1_TIMINGR I2C_TIMINGR(I2C1)
#define I2C2_TIMINGR I2C_TIMINGR(I2C2)
#define I2C_TIMEOUTR(i2c_base) MMIO32(i2c_base + 0x14)
#define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1)
#define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2)
#define I2C_ISR(i2c_base) MMIO32(i2c_base + 0x18)
#define I2C1_ISR I2C_ISR(I2C1)
#define I2C2_ISR I2C_ISR(I2C2)
#define I2C_ICR(i2c_base) MMIO32(i2c_base + 0x1C)
#define I2C1_ICR I2C_ICR(I2C1)
#define I2C2_ICR I2C_ICR(I2C2)
#define I2C_PECR(i2c_base) MMIO8(i2c_base + 0x20)
#define I2C1_PECR I2C_PECR(I2C1)
#define I2C2_PECR I2C_PECR(I2C2)
#define I2C_RXDR(i2c_base) MMIO8(i2c_base + 0x24)
#define I2C1_RXDR I2C_RXDR(I2C1)
#define I2C2_RXDR I2C_RXDR(I2C2)
#define I2C_TXDR(i2c_base) MMIO8(i2c_base + 0x28)
#define I2C1_TXDR I2C_TXDR(I2C1)
#define I2C2_TXDR I2C_TXDR(I2C2)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* I2C_CR1 values ---------------------------------------------------------- */
#define I2C_CR1_PECEN (1 << 23)
#define I2C_CR1_ALERTEN (1 << 22)
#define I2C_CR1_SMBDEN (1 << 21)
#define I2C_CR1_SMBHEN (1 << 20)
#define I2C_CR1_GCEN (1 << 19)
#define I2C_CR1_WUPEN (1 << 18)
#define I2C_CR1_NOSTRETCH (1 << 17)
#define I2C_CR1_SBC (1 << 16)
#define I2C_CR1_RXDMAEN (1 << 15)
#define I2C_CR1_TXDMAEN (1 << 14)
#define I2C_CR1_ANFOFF (1 << 12)
#define I2C_CR1_DNF_SHIFT 8
#define I2C_CR1_DNF (0x0F << I2C_CR1_DNF_SHIFT)
#define I2C_CR1_DNF_VAL(x) ((x) << I2C_CR1_DNF_SHIFT)
#define I2C_CR1_ERRIE (1 << 7)
#define I2C_CR1_TCIE (1 << 6)
#define I2C_CR1_STOPIE (1 << 5)
#define I2C_CR1_NACKIE (1 << 4)
#define I2C_CR1_ADDRIE (1 << 3)
#define I2C_CR1_RXIE (1 << 2)
#define I2C_CR1_TXIE (1 << 1)
#define I2C_CR1_PE (1 << 0)
/* I2C_CR2 values ---------------------------------------------------------- */
#define I2C_CR2_PECBYTE (1 << 26)
#define I2C_CR2_AUTOEND (1 << 25)
#define I2C_CR2_RELOAD (1 << 24)
#define I2C_CR2_NBYTES_SHIFT 16
#define I2C_CR2_NBYTES (0xFF << I2C_CR2_NBYTES_SHIFT)
#define I2C_CR2_NBYTES_VAL(x) ((x) << I2C_CR2_NBYTES_SHIFT)
#define I2C_CR2_NACK (1 << 15)
#define I2C_CR2_STOP (1 << 14)
#define I2C_CR2_START (1 << 13)
#define I2C_CR2_HEAD10R (1 << 12)
#define I2C_CR2_ADD10 (1 << 11)
#define I2C_CR2_RD_WRN (1 << 10)
#define I2C_CR2_SADD_SHIFT 0
#define I2C_CR2_SADD (0x3FF << I2C_CR2_SADD_SHIFT)
#define I2C_CR2_SADD_VAL(x) ((x) << I2C_CR2_SADD_SHIFT)
/* I2C_OAR1 values --------------------------------------------------------- */
#define I2C_OAR1_OA1EN (1 << 15)
#define I2C_OAR1_OA1MODE (1 << 10)
#define I2C_OAR1_OA1_SHIFT 0
#define I2C_OAR1_OA1 (0x3FF << I2C_OAR1_OA1_SHIFT)
#define I2C_OAR1_OA1_VAL(x) ((x) << I2C_OAR1_OA1_SHIFT)
/* I2C_OAR2 values --------------------------------------------------------- */
#define I2C_OAR2_OA1EN (1 << 15)
#define I2C_OAR2_OA2MSK_SHIFT 8
#define I2C_OAR2_OA2MSK (7 << I2C_OAR2_OA2MSK_SHIFT)
#define I2C_OAR2_OA2MSK_NOMASK (0 << I2C_OAR2_OA2MSK_SHIFT)
#define I2C_OAR2_OA2MSK_1_BIT (1 << I2C_OAR2_OA2MSK_SHIFT)
#define I2C_OAR2_OA2MSK_2_BIT (2 << I2C_OAR2_OA2MSK_SHIFT)
#define I2C_OAR2_OA2MSK_3_BIT (3 << I2C_OAR2_OA2MSK_SHIFT)
#define I2C_OAR2_OA2MSK_4_BIT (4 << I2C_OAR2_OA2MSK_SHIFT)
#define I2C_OAR2_OA2MSK_5_BIT (5 << I2C_OAR2_OA2MSK_SHIFT)
#define I2C_OAR2_OA2MSK_6_BIT (6 << I2C_OAR2_OA2MSK_SHIFT)
#define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT)
#define I2C_OAR2_OA2_SHIFT 1
#define I2C_OAR2_OA2 (0x7F << I2C_OAR2_OA2_SHIFT)
#define I2C_OAR2_OA2_VAL(x) ((x) << I2C_OAR2_OA2_SHIFT)
/* I2C_TIMINGR values ------------------------------------------------------ */
#define I2C_TIMINGR_PRESC_SHIFT 28
#define I2C_TIMINGR_PRESC (0x0F << I2C_TIMINGR_PRESC_SHIFT)
#define I2C_TIMINGR_PRESC_VAL(x) ((x) << I2C_TIMINGR_PRESC_SHIFT)
#define I2C_TIMINGR_SCLDEL_SHIFT 20
#define I2C_TIMINGR_SCLDEL (0x0F << I2C_TIMINGR_SCLDEL_SHIFT)
#define I2C_TIMINGR_SCLDEL_VAL(x) ((x) << I2C_TIMINGR_SCLDEL_SHIFT)
#define I2C_TIMINGR_SDADEL_SHIFT 16
#define I2C_TIMINGR_SDADEL (0x0F << I2C_TIMINGR_SDADEL_SHIFT)
#define I2C_TIMINGR_SDADEL_VAL(x) ((x) << I2C_TIMINGR_SDADEL_SHIFT)
#define I2C_TIMINGR_SCLH_SHIFT 8
#define I2C_TIMINGR_SCLH (0xFF << I2C_TIMINGR_SCLH_SHIFT)
#define I2C_TIMINGR_SCLH_VAL(x) ((x) << I2C_TIMINGR_SCLH_SHIFT)
#define I2C_TIMINGR_SCLL_SHIFT 0
#define I2C_TIMINGR_SCLL (0xFF << I2C_TIMINGR_SCLL_SHIFT)
#define I2C_TIMINGR_SCLL_VAL(x) ((x) << I2C_TIMINGR_SCLL_SHIFT)
/* I2C_TIMEOUTR values ----------------------------------------------------- */
#define I2C_TIMEOUTR_TETXEN (1 << 31)
#define I2C_TIMEOUTR_TIMEOUTB_SHIFT 16
#define I2C_TIMEOUTR_TIMEOUTB (0xFFF << I2C_TIMEOUTR_TIMEOUTB_SHIFT)
#define I2C_TIMEOUTR_TIMEOUTB_VAL(x) ((x) << I2C_TIMEOUTR_TIMEOUTB_SHIFT)
#define I2C_TIMEOUTR_TIMOUTEN (1 << 15)
#define I2C_TIMEOUTR_TIDLE (1 << 12)
#define I2C_TIMEOUTR_TIMEOUTA_SHIFT 0
#define I2C_TIMEOUTR_TIMEOUTA (0xFFF << I2C_TIMEOUTR_TIMEOUTA_SHIFT)
#define I2C_TIMEOUTR_TIMEOUTA_VAL(x) ((x) << I2C_TIMEOUTR_TIMEOUTA_SHIFT)
/* I2C_ISR values ---------------------------------------------------------- */
#define I2C_ISR_ADDCODE_SHIFT 17
#define I2C_ISR_ADDCODE (0x7F << I2C_ISR_ADDCODE_SHIFT)
#define I2C_ISR_ADDCODE_VAL(x) ((x) << I2C_ISR_ADDCODE_SHIFT)
#define I2C_ISR_ADDCODE_VALG(reg) (((reg) & I2C_ISR_ADDCODE) >> \
I2C_ISR_ADDCODE_SHIFT)
#define I2C_ISR_DIR (1 << 16)
#define I2C_ISR_BUSY (1 << 15)
#define I2C_ISR_ALERT (1 << 13)
#define I2C_ISR_TIMEOUT (1 << 12)
#define I2C_ISR_PECERR (1 << 11)
#define I2C_ISR_OVR (1 << 10)
#define I2C_ISR_ARLO (1 << 9)
#define I2C_ISR_BERR (1 << 8)
#define I2C_ISR_TCR (1 << 7)
#define I2C_ISR_TC (1 << 6)
#define I2C_ISR_STOPF (1 << 5)
#define I2C_ISR_NACKF (1 << 4)
#define I2C_ISR_ADDR (1 << 3)
#define I2C_ISR_RXNE (1 << 2)
#define I2C_ISR_TXIS (1 << 1)
#define I2C_ISR_TXE (1 << 0)
/* I2C_ICR values ---------------------------------------------------------- */
#define I2C_ICR_ALERTCF (1 << 13)
#define I2C_ICR_TIMEOUTCF (1 << 12)
#define I2C_ICR_PECCF (1 << 11)
#define I2C_ICR_OVRCF (1 << 10)
#define I2C_ICR_ARLOCF (1 << 9)
#define I2C_ICR_BERRCF (1 << 8)
#define I2C_ICR_STOPCF (1 << 5)
#define I2C_ICR_NACKCF (1 << 4)
#define I2C_ICR_ADDRCF (1 << 3)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
END_DECLS
#endif

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includeguard: LIBOPENCM3_STM32_F0_NVIC_H
partname_humanreadable: STM32 F0 series
partname_doxygen: STM32F0
irqs:
- wwdg
- pvd
- rtc
- flash
- rcc
- exti0_1
- exti2_3
- exti4_15
- tsc
- dma1_channel1
- dma1_channel2_3
- dma1_channel4_5
- adc_comp
- tim1_brk_up_trg_com
- tim1_cc
- tim2
- tim3
- tim6_dac
- reserved0
- tim14
- tim15
- tim16
- tim17
- i2c1
- i2c2
- spi1
- spi2
- usart1
- usart2
- reserved1
- cec
- reserved2

71
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/** @defgroup iwdg_defines IWDG Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx Independent Watchdog
* Timer</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 18 August 2012
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_IWDG_H
#define LIBOPENCM3_IWDG_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/iwdg_common_all.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
/* Key Register (IWDG_WINR) */
#define IWDG_WINR MMIO32(IWDG_BASE + 0x10)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* --- IWDG_SR values ------------------------------------------------------ */
/* WVU: Watchdog counter window value update */
#define IWDG_SR_WVU (1 << 2)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
END_DECLS
#endif

101
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* .. based on file from F4.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_MEMORYMAP_H
#define LIBOPENCM3_MEMORYMAP_H
#include <libopencm3/cm3/memorymap.h>
/* --- STM32 specific peripheral definitions ------------------------------- */
/* Memory map for all buses */
#define FLASH_BASE ((uint32_t)0x08000000)
#define PERIPH_BASE ((uint32_t)0x40000000)
#define INFO_BASE ((uint32_t)0x1ffff000)
#define PERIPH_BASE_APB (PERIPH_BASE + 0x00000000)
#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x00020000)
#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x08000000)
/* Register boundary addresses */
/* APB1 */
#define TIM2_BASE (PERIPH_BASE_APB + 0x0000)
#define TIM3_BASE (PERIPH_BASE_APB + 0x0400)
#define TIM6_BASE (PERIPH_BASE_APB + 0x1000)
#define TIM14_BASE (PERIPH_BASE_APB + 0x2000)
/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
#define RTC_BASE (PERIPH_BASE_APB + 0x2800)
#define WWDG_BASE (PERIPH_BASE_APB + 0x2c00)
#define IWDG_BASE (PERIPH_BASE_APB + 0x3000)
/* PERIPH_BASE_APB + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_BASE (PERIPH_BASE_APB + 0x3800)
/* PERIPH_BASE_APB + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB + 0x4400)
#define I2C1_BASE (PERIPH_BASE_APB + 0x5400)
#define I2C2_BASE (PERIPH_BASE_APB + 0x5800)
#define POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000)
#define DAC_BASE (PERIPH_BASE_APB + 0x7400)
#define CEC_BASE (PERIPH_BASE_APB + 0x7800)
#define SYSCFG_COMP_BASE (PERIPH_BASE_APB + 0x10000)
#define EXTI_BASE (PERIPH_BASE_APB + 0x10400)
#define ADC_BASE (PERIPH_BASE_APB + 0x12400)
#define TIM1_BASE (PERIPH_BASE_APB + 0x12C00)
#define SPI1_I2S1_BASE (PERIPH_BASE_APB + 0x13000)
#define USART1_BASE (PERIPH_BASE_APB + 0x13800)
#define TIM15_BASE (PERIPH_BASE_APB + 0x14000)
#define TIM16_BASE (PERIPH_BASE_APB + 0x14400)
#define TIM17_BASE (PERIPH_BASE_APB + 0x14800)
#define DBGMCU_BASE (PERIPH_BASE_APB + 0x15800)
/* AHB1 */
#define DMA_BASE (PERIPH_BASE_AHB1 + 0x0000)
#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000)
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000)
#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000)
/* AHB2 */
#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000)
#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400)
#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800)
#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00)
#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400)
/* Device Electronic Signature */
/* ???
#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0)
#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8)
*/
#endif

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/** @defgroup pwr_defines PWR Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx PWR Control</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 5 December 2012
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_PWR_H
#define LIBOPENCM3_PWR_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/pwr_common_all.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* EWUP: Enable WKUP2 pin */
#define PWR_CSR_EWUP2 (1 << 9)
/* EWUP: Enable WKUP1 pin */
#define PWR_CSR_EWUP1 (1 << 8)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
END_DECLS
#endif

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/** @defgroup rcc_defines RCC Defines
*
* @brief <b>libopencm3 STM32F0xx Reset and Clock Control</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 29 Jun 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_RCC_H
#define LIBOPENCM3_RCC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define RCC_CR MMIO32(RCC_BASE + 0x00)
#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
#define RCC_CIR MMIO32(RCC_BASE + 0x08)
#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)
#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
#define RCC_CSR MMIO32(RCC_BASE + 0x24)
#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28)
#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c)
#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30)
#define RCC_CR2 MMIO32(RCC_BASE + 0x32)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* --- RCC_CR values ------------------------------------------------------- */
#define RCC_CR_PLLRDY (1 << 25)
#define RCC_CR_PLLON (1 << 24)
#define RCC_CR_CSSON (1 << 19)
#define RCC_CR_HSEBYP (1 << 18)
#define RCC_CR_HSERDY (1 << 17)
#define RCC_CR_HSEON (1 << 16)
#define RCC_CR_HSICAL_SHIFT 8
#define RCC_CR_HSICAL (0xFF << RCC_CR_HSICAL_SHIFT)
#define RCC_CR_HSITRIM_SHIFT 3
#define RCC_CR_HSITRIM (0x1F << RCC_CR_HSITRIM_SHIFT)
#define RCC_CR_HSIRDY (1 << 1)
#define RCC_CR_HSION (1 << 0)
/* --- RCC_CFGR values ----------------------------------------------------- */
#define RCC_CFGR_PLLNODIV (1 << 31)
#define RCC_CFGR_MCOPRE_SHIFT 28
#define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT)
#define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT)
#define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT)
#define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT)
#define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT)
#define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT)
#define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT)
#define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT)
#define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT)
#define RCC_CFGR_MCO_SHIFT 24
#define RCC_CFGR_MCO (7 << RCC_CFGR_MCO_SHIFT)
#define RCC_CFGR_MCO_NOCLK (0 << RCC_CFGR_MCO_SHIFT)
#define RCC_CFGR_MCO_HSI14 (1 << RCC_CFGR_MCO_SHIFT)
#define RCC_CFGR_MCO_LSI (2 << RCC_CFGR_MCO_SHIFT)
#define RCC_CFGR_MCO_LSE (3 << RCC_CFGR_MCO_SHIFT)
#define RCC_CFGR_MCO_SYSCLK (4 << RCC_CFGR_MCO_SHIFT)
#define RCC_CFGR_MCO_HSI (5 << RCC_CFGR_MCO_SHIFT)
#define RCC_CFGR_MCO_HSE (6 << RCC_CFGR_MCO_SHIFT)
#define RCC_CFGR_MCO_PLL (7 << RCC_CFGR_MCO_SHIFT)
#define RCC_CFGR_PLLMUL_SHIFT 18
#define RCC_CFGR_PLLMUL (0x0F << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL2 (0x00 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL3 (0x01 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL4 (0x02 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL5 (0x03 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL6 (0x04 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL7 (0x05 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL8 (0x06 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL9 (0x06 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL10 (0x07 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL11 (0x08 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL12 (0x09 << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL13 (0x0A << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL14 (0x0B << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL15 (0x0C << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLMUL_MUL16 (0x0D << RCC_CFGR_PLLMUL_SHIFT)
#define RCC_CFGR_PLLXTPRE (1<<17)
#define RCC_CFGR_PLLSRC (1<<16)
#define RCC_CFGR_ADCPRE (1<<14)
#define RCC_CFGR_PPRE_SHIFT 8
#define RCC_CFGR_PPRE (7 << RCC_CFGR_PPRE_SHIFT)
#define RCC_CFGR_PPRE_NODIV (0 << RCC_CFGR_PPRE_SHIFT)
#define RCC_CFGR_PPRE_DIV2 (4 << RCC_CFGR_PPRE_SHIFT)
#define RCC_CFGR_PPRE_DIV4 (5 << RCC_CFGR_PPRE_SHIFT)
#define RCC_CFGR_PPRE_DIV8 (6 << RCC_CFGR_PPRE_SHIFT)
#define RCC_CFGR_PPRE_DIV16 (7 << RCC_CFGR_PPRE_SHIFT)
#define RCC_CFGR_HPRE_SHIFT 4
#define RCC_CFGR_HPRE (0xf << RCC_CFGR_HPRE_SHIFT)
#define RCC_CFGR_HPRE_NODIV (0x0 << RCC_CFGR_HPRE_SHIFT)
#define RCC_CFGR_HPRE_DIV2 (0x8 << RCC_CFGR_HPRE_SHIFT)
#define RCC_CFGR_HPRE_DIV4 (0x9 << RCC_CFGR_HPRE_SHIFT)
#define RCC_CFGR_HPRE_DIV8 (0xa << RCC_CFGR_HPRE_SHIFT)
#define RCC_CFGR_HPRE_DIV16 (0xb << RCC_CFGR_HPRE_SHIFT)
#define RCC_CFGR_HPRE_DIV64 (0xc << RCC_CFGR_HPRE_SHIFT)
#define RCC_CFGR_HPRE_DIV128 (0xd << RCC_CFGR_HPRE_SHIFT)
#define RCC_CFGR_HPRE_DIV256 (0xe << RCC_CFGR_HPRE_SHIFT)
#define RCC_CFGR_HPRE_DIV512 (0xf << RCC_CFGR_HPRE_SHIFT)
#define RCC_CFGR_SWS_SHIFT 2
#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT)
#define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT)
#define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT)
#define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT)
#define RCC_CFGR_SW_SHIFT 0
#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT)
#define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT)
#define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT)
#define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT)
/* --- RCC_CIR values ------------------------------------------------------ */
#define RCC_CIR_CSSC (1 << 23)
#define RCC_CIR_HSI14RDYC (1 << 21)
#define RCC_CIR_PLLRDYC (1 << 20)
#define RCC_CIR_HSERDYC (1 << 19)
#define RCC_CIR_HSIRDYC (1 << 18)
#define RCC_CIR_LSERDYC (1 << 17)
#define RCC_CIR_LSIRDYC (1 << 16)
#define RCC_CIR_HSI14RDYIE (1 << 13)
#define RCC_CIR_PLLRDYIE (1 << 12)
#define RCC_CIR_HSERDYIE (1 << 11)
#define RCC_CIR_HSIRDYIE (1 << 10)
#define RCC_CIR_LSERDYIE (1 << 9)
#define RCC_CIR_LSIRDYIE (1 << 8)
#define RCC_CIR_CSSF (1 << 7)
#define RCC_CIR_HSI14RDYF (1 << 5)
#define RCC_CIR_PLLRDYF (1 << 4)
#define RCC_CIR_HSERDYF (1 << 3)
#define RCC_CIR_HSIRDYF (1 << 2)
#define RCC_CIR_LSERDYF (1 << 1)
#define RCC_CIR_LSIRDYF (1 << 0)
/* --- RCC_APB2RSTR values ------------------------------------------------- */
#define RCC_APB2RSTR_DBGMCURST (1 << 22)
#define RCC_APB2RSTR_TIM17RST (1 << 18)
#define RCC_APB2RSTR_TIM16RST (1 << 17)
#define RCC_APB2RSTR_TIM15RST (1 << 16)
#define RCC_APB2RSTR_USART1RST (1 << 14)
#define RCC_APB2RSTR_SPI1RST (1 << 12)
#define RCC_APB2RSTR_TIM1RST (1 << 11)
#define RCC_APB2RSTR_ADCRST (1 << 9)
#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
/* --- RCC_APB1RSTR values ------------------------------------------------- */
#define RCC_APB1RSTR_CECRST (1 << 30)
#define RCC_APB1RSTR_DACRST (1 << 29)
#define RCC_APB1RSTR_PWRRST (1 << 28)
#define RCC_APB1RSTR_I2C2RST (1 << 22)
#define RCC_APB1RSTR_I2C1RST (1 << 21)
#define RCC_APB1RSTR_USART2RST (1 << 17)
#define RCC_APB1RSTR_SPI2RST (1 << 14)
#define RCC_APB1RSTR_WWDGRST (1 << 11)
#define RCC_APB1RSTR_TIM14RST (1 << 8)
#define RCC_APB1RSTR_TIM6RST (1 << 4)
#define RCC_APB1RSTR_TIM3RST (1 << 1)
#define RCC_APB1RSTR_TIM2RST (1 << 0)
/* --- RCC_AHBENR values --------------------------------------------------- */
#define RCC_AHBENR_TSCEN (1 << 24)
#define RCC_AHBENR_GPIOFEN (1 << 22)
#define RCC_AHBENR_GPIODEN (1 << 20)
#define RCC_AHBENR_GPIOCEN (1 << 19)
#define RCC_AHBENR_GPIOBEN (1 << 18)
#define RCC_AHBENR_GPIOAEN (1 << 17)
#define RCC_AHBENR_CRCEN (1 << 6)
#define RCC_AHBENR_FLTFEN (1 << 4)
#define RCC_AHBENR_SRAMEN (1 << 2)
#define RCC_AHBENR_DMAEN (1 << 0)
/* --- RCC_APB2ENR values -------------------------------------------------- */
#define RCC_APB2ENR_DBGMCUEN (1 << 22)
#define RCC_APB2ENR_TIM17EN (1 << 18)
#define RCC_APB2ENR_TIM16EN (1 << 17)
#define RCC_APB2ENR_TIM15EN (1 << 16)
#define RCC_APB2ENR_USART1EN (1 << 14)
#define RCC_APB2ENR_SPI1EN (1 << 12)
#define RCC_APB2ENR_TIM1EN (1 << 11)
#define RCC_APB2ENR_ADCEN (1 << 9)
#define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0)
/* --- RCC_APB1ENR values -------------------------------------------------- */
#define RCC_APB1ENR_CECEN (1 << 30)
#define RCC_APB1ENR_DACEN (1 << 29)
#define RCC_APB1ENR_PWREN (1 << 28)
#define RCC_APB1ENR_I2C2EN (1 << 22)
#define RCC_APB1ENR_I2C1EN (1 << 21)
#define RCC_APB1ENR_USART2EN (1 << 17)
#define RCC_APB1ENR_SPI2EN (1 << 14)
#define RCC_APB1ENR_WWDGEN (1 << 11)
#define RCC_APB1ENR_TIM14EN (1 << 8)
#define RCC_APB1ENR_TIM6EN (1 << 4)
#define RCC_APB1ENR_TIM3EN (1 << 1)
#define RCC_APB1ENR_TIM2EN (1 << 0)
/* --- RCC_BDCR values ----------------------------------------------------- */
#define RCC_BDCR_BDRST (1 << 16)
#define RCC_BDCR_RTCEN (1 << 15)
#define RCC_BDCR_RTCSEL_SHIFT 8
#define RCC_BDCR_RTCSEL (3 << RCC_BDCR_RTCSEL_SHIFT)
#define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT)
#define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT)
#define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT)
#define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT)
#define RCC_BDCR_LSEDRV_SHIFT 3
#define RCC_BDCR_LSEDRV (3 << RCC_BDCR_LSEDRV_SHIFT)
#define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT)
#define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT)
#define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT)
#define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT)
#define RCC_BDCR_LSEBYP (1 << 2)
#define RCC_BDCR_LSERDY (1 << 1)
#define RCC_BDCR_LSEON (1 << 0)
/* --- RCC_CSR values ------------------------------------------------------ */
#define RCC_CSR_LPWRRSTF (1 << 31)
#define RCC_CSR_WWDGRSTF (1 << 30)
#define RCC_CSR_IWDGRSTF (1 << 29)
#define RCC_CSR_SFTRSTF (1 << 28)
#define RCC_CSR_PORRSTF (1 << 27)
#define RCC_CSR_PINRSTF (1 << 26)
#define RCC_CSR_OBLRSTF (1 << 25)
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_V18PWRRSTF (1 << 23)
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
/* --- RCC_AHBRSTR values -------------------------------------------------- */
#define RCC_AHBRSTR_TSCRST (1 << 24)
#define RCC_AHBRSTR_IOPFRST (1 << 22)
#define RCC_AHBRSTR_IOPDRST (1 << 20)
#define RCC_AHBRSTR_IOPCRST (1 << 19)
#define RCC_AHBRSTR_IOPBRST (1 << 18)
#define RCC_AHBRSTR_IOPARST (1 << 17)
/* --- RCC_CFGR2 values ---------------------------------------------------- */
#define RCC_CFGR2_PREDIV 0xf
#define RCC_CFGR2_PREDIV_NODIV 0x0
#define RCC_CFGR2_PREDIV_DIV2 0x1
#define RCC_CFGR2_PREDIV_DIV3 0x2
#define RCC_CFGR2_PREDIV_DIV4 0x3
#define RCC_CFGR2_PREDIV_DIV5 0x4
#define RCC_CFGR2_PREDIV_DIV6 0x5
#define RCC_CFGR2_PREDIV_DIV7 0x6
#define RCC_CFGR2_PREDIV_DIV8 0x7
#define RCC_CFGR2_PREDIV_DIV9 0x8
#define RCC_CFGR2_PREDIV_DIV10 0x9
#define RCC_CFGR2_PREDIV_DIV11 0xa
#define RCC_CFGR2_PREDIV_DIV12 0xb
#define RCC_CFGR2_PREDIV_DIV13 0xc
#define RCC_CFGR2_PREDIV_DIV14 0xd
#define RCC_CFGR2_PREDIV_DIV15 0xe
#define RCC_CFGR2_PREDIV_DIV16 0xf
/* --- RCC_CFGR3 values ---------------------------------------------------- */
#define RCC_CFGR3_ADCSW (1 << 8)
#define RCC_CFGR3_CECSW (1 << 6)
#define RCC_CFGR3_I2C1SW (1 << 4)
#define RCC_CFGR3_USART1SW_SHIFT 0
#define RCC_CFGR3_USART1SW (3 << RCC_CFGR3_USART1SW_SHIFT)
#define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT)
#define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT)
#define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT)
#define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT)
/* --- RCC_CFGR3 values ---------------------------------------------------- */
#define RCC_CR2_HSI14CAL_SHIFT 8
#define RCC_CR2_HSI14CAL (0xFF << RCC_CR2_HSI14CAL_SHIFT)
#define RCC_CR2_HSI14TRIM_SHIFT 3
#define RCC_CR2_HSI14TRIM (31 << RCC_CR2_HSI14TRIM_SHIFT)
#define RCC_CR2_HSI14DIS (1 << 2)
#define RCC_CR2_HSI14RDY (1 << 1)
#define RCC_CR2_HSI14ON (1 << 0)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/* --- Variable definitions ------------------------------------------------ */
extern uint32_t rcc_core_frequency;
extern uint32_t rcc_ppre_frequency;
enum rcc_osc {
HSI14, HSI, HSE, PLL, LSI, LSE
};
#define _REG_BIT(base, bit) (((base) << 5) + (bit))
enum rcc_periph_clken {
/* AHB peripherals */
RCC_DMA = _REG_BIT(0x14, 0),
RCC_SRAM = _REG_BIT(0x14, 2),
RCC_FLTIF = _REG_BIT(0x14, 4),
RCC_CRC = _REG_BIT(0x14, 6),
RCC_GPIOA = _REG_BIT(0x14, 17),
RCC_GPIOB = _REG_BIT(0x14, 18),
RCC_GPIOC = _REG_BIT(0x14, 19),
RCC_GPIOD = _REG_BIT(0x14, 20),
RCC_GPIOF = _REG_BIT(0x14, 22),
RCC_TSC = _REG_BIT(0x14, 24),
/* APB2 peripherals */
RCC_SYSCFG_COMP = _REG_BIT(0x18, 0),
RCC_ADC = _REG_BIT(0x18, 9),
RCC_TIM1 = _REG_BIT(0x18, 11),
RCC_SPI1 = _REG_BIT(0x18, 12),
RCC_USART1 = _REG_BIT(0x18, 14),
RCC_TIM15 = _REG_BIT(0x18, 16),
RCC_TIM16 = _REG_BIT(0x18, 17),
RCC_TIM17 = _REG_BIT(0x18, 18),
RCC_DBGMCU = _REG_BIT(0x18, 22),
/* APB1 peripherals */
RCC_TIM2 = _REG_BIT(0x1C, 0),
RCC_TIM3 = _REG_BIT(0x1C, 1),
RCC_TIM6 = _REG_BIT(0x1C, 4),
RCC_TIM14 = _REG_BIT(0x1C, 8),
RCC_WWDG = _REG_BIT(0x1C, 11),
RCC_SPI2 = _REG_BIT(0x1C, 14),
RCC_USART2 = _REG_BIT(0x1C, 17),
RCC_I2C1 = _REG_BIT(0x1C, 21),
RCC_I2C2 = _REG_BIT(0x1C, 22),
RCC_PWR = _REG_BIT(0x1C, 28),
RCC_DAC = _REG_BIT(0x1C, 29),
RCC_CEC = _REG_BIT(0x1C, 30),
/* Advanced peripherals */
RCC_RTC = _REG_BIT(0x20, 15),/* BDCR[15] */
};
enum rcc_periph_rst {
/* APB2 peripherals */
RST_SYSCFG = _REG_BIT(0x0C, 0),
RST_ADC = _REG_BIT(0x0C, 9),
RST_TIM1 = _REG_BIT(0x0C, 11),
RST_SPI1 = _REG_BIT(0x0C, 12),
RST_USART1 = _REG_BIT(0x0C, 14),
RST_TIM15 = _REG_BIT(0x0C, 16),
RST_TIM16 = _REG_BIT(0x0C, 17),
RST_TIM17 = _REG_BIT(0x0C, 18),
RST_DBGMCU = _REG_BIT(0x0C, 22),
/* APB1 peripherals */
RST_TIM2 = _REG_BIT(0x10, 0),
RST_TIM3 = _REG_BIT(0x10, 1),
RST_TIM6 = _REG_BIT(0x10, 4),
RST_TIM14 = _REG_BIT(0x10, 8),
RST_WWDG = _REG_BIT(0x10, 11),
RST_SPI2 = _REG_BIT(0x10, 14),
RST_USART2 = _REG_BIT(0x10, 17),
RST_I2C1 = _REG_BIT(0x10, 21),
RST_I2C2 = _REG_BIT(0x10, 22),
RST_PWR = _REG_BIT(0x10, 28),
RST_DAC = _REG_BIT(0x10, 29),
RST_CEC = _REG_BIT(0x10, 30),
/* Advanced peripherals */
RST_BACKUPDOMAIN = _REG_BIT(0x20, 16),/* BDCR[16] */
/* AHB peripherals */
RST_GPIOA = _REG_BIT(0x28, 17),
RST_GPIOB = _REG_BIT(0x28, 18),
RST_GPIOC = _REG_BIT(0x28, 19),
RST_GPIOD = _REG_BIT(0x28, 20),
RST_GPIOF = _REG_BIT(0x28, 22),
RST_TSC = _REG_BIT(0x28, 24),
};
#undef _REG_BIT
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
void rcc_osc_ready_int_clear(enum rcc_osc osc);
void rcc_osc_ready_int_enable(enum rcc_osc osc);
void rcc_osc_ready_int_disable(enum rcc_osc osc);
int rcc_osc_ready_int_flag(enum rcc_osc osc);
void rcc_wait_for_osc_ready(enum rcc_osc osc);
void rcc_osc_on(enum rcc_osc osc);
void rcc_osc_off(enum rcc_osc osc);
void rcc_osc_bypass_enable(enum rcc_osc osc);
void rcc_osc_bypass_disable(enum rcc_osc osc);
void rcc_css_enable(void);
void rcc_css_disable(void);
void rcc_css_int_clear(void);
int rcc_css_int_flag(void);
void rcc_set_sysclk_source(enum rcc_osc clk);
void rcc_set_pll_multiplication_factor(uint32_t mul);
void rcc_set_ppre(uint32_t ppre);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_prediv(uint32_t prediv);
void rcc_set_mco(uint32_t mcosrc);
enum rcc_osc rcc_system_clock_source(void);
void rcc_clock_setup_in_hsi_out_8mhz(void);
void rcc_clock_setup_in_hsi_out_16mhz(void);
void rcc_clock_setup_in_hsi_out_24mhz(void);
void rcc_clock_setup_in_hsi_out_32mhz(void);
void rcc_clock_setup_in_hsi_out_40mhz(void);
void rcc_clock_setup_in_hsi_out_48mhz(void);
void rcc_periph_clock_enable(enum rcc_periph_clken periph);
void rcc_periph_clock_disable(enum rcc_periph_clken periph);
void rcc_periph_reset_pulse(enum rcc_periph_rst periph);
void rcc_periph_reset_hold(enum rcc_periph_rst periph);
void rcc_periph_reset_release(enum rcc_periph_rst periph);
END_DECLS
#endif
/**@}*/

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/** @defgroup rtc_defines RTC Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx RTC</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 5 December 2012
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_RTC_H
#define LIBOPENCM3_RTC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/rtc_common_l1f024.h>
#endif

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/** @defgroup spi_defines SPI Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx SPI</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_SPI_H
#define LIBOPENCM3_SPI_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/spi_common_all.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
#define SPI1_BASE SPI1_I2S1_BASE
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* DFF: Data frame format */
/** @defgroup spi_dff SPI data frame format
* @ingroup spi_defines
*
* @{*/
#define SPI_CR1_CRCL_8BIT (0 << 11)
#define SPI_CR1_CRCL_16BIT (1 << 11)
/**@}*/
#define SPI_CR1_CRCL (1 << 11)
/* --- SPI_CR2 values ------------------------------------------------------ */
/* LDMA_TX: Last DMA transfer for transmission */
#define SPI_CR2_LDMA_TX (1 << 14)
/* LDMA_RX: Last DMA transfer for reception */
#define SPI_CR2_LDMA_RX (1 << 13)
/* FRXTH: FIFO reception threshold */
#define SPI_CR2_FRXTH (1 << 12)
/* DS [3:0]: Data size */
/* 0x0 - 0x2 NOT USED */
#define SPI_CR2_DS_4BIT (0x3 << 8)
#define SPI_CR2_DS_5BIT (0x4 << 8)
#define SPI_CR2_DS_6BIT (0x5 << 8)
#define SPI_CR2_DS_7BIT (0x6 << 8)
#define SPI_CR2_DS_8BIT (0x7 << 8)
#define SPI_CR2_DS_9BIT (0x8 << 8)
#define SPI_CR2_DS_10BIT (0x9 << 8)
#define SPI_CR2_DS_11BIT (0xA << 8)
#define SPI_CR2_DS_12BIT (0xB << 8)
#define SPI_CR2_DS_13BIT (0xC << 8)
#define SPI_CR2_DS_14BIT (0xD << 8)
#define SPI_CR2_DS_15BIT (0xE << 8)
#define SPI_CR2_DS_16BIT (0xF << 8)
#define SPI_CR2_DS_MASK (0xF << 8)
/* NSSP: NSS pulse management */
#define SPI_CR2_NSSP (1 << 3)
/* --- SPI_SR values ------------------------------------------------------- */
/* FTLVL[1:0]: FIFO Transmission Level */
#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)
#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)
#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)
#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)
/* FRLVL[1:0]: FIFO Reception Level */
#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)
#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)
#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)
#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
void spi_set_data_size(uint32_t spi, uint16_t data_s);
void spi_fifo_reception_threshold_8bit(uint32_t spi);
void spi_fifo_reception_threshold_16bit(uint32_t spi);
void spi_i2s_mode_spi_mode(uint32_t spi);
void spi_send8(uint32_t spi, uint8_t data);
uint8_t spi_read8(uint32_t spi);
END_DECLS
#endif

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/** @defgroup syscfg_defines SYSCFG Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx System Config</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_SYSCFG_H
#define LIBOPENCM3_SYSCFG_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/memorymap.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define SYSCFG_CFGR1 MMIO32(SYSCFG_COMP_BASE + 0x00)
#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_COMP_BASE + 0x08 + (i)*4)
#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0)
#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1)
#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2)
#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3)
#define SYSCFG_CFGR2 MMIO32(SYSCFG_COMP_BASE + 0x18)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* SYSCFG_CFGR1 Values -- ---------------------------------------------------*/
#define SYSCFG_CFGR1_MEM_MODE_SHIFT 0
#define SYSCFG_CFGR1_MEM_MODE (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
#define SYSCFG_CFGR1_MEM_MODE_FLASH (0 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
#define SYSCFG_CFGR1_MEM_MODE_SYSTEM (1 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
#define SYSCFG_CFGR1_MEM_MODE_SRAM (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT)
#define SYSCFG_CFGR1_ADC_DMA_RMP (1 << 8)
#define SYSCFG_CFGR1_USART1_TX_DMA_RMP (1 << 9)
#define SYSCFG_CFGR1_USART1_RX_DMA_RMP (1 << 10)
#define SYSCFG_CFGR1_TIM16_DMA_RMP (1 << 11)
#define SYSCFG_CFGR1_TIM17_DMA_RMP (1 << 12)
#define SYSCFG_CFGR1_I2C_PB6_FMPLUS (1 << 16)
#define SYSCFG_CFGR1_I2C_PB7_FMPLUS (1 << 17)
#define SYSCFG_CFGR1_I2C_PB8_FMPLUS (1 << 18)
#define SYSCFG_CFGR1_I2C_PB9_FMPLUS (1 << 19)
#define SYSCFG_CFGR1_I2C1_FMPLUS (1 << 20)
#define SYSCFG_CFGR1_I2C_PA9_FMPLUS (1 << 22)
#define SYSCFG_CFGR1_I2C_PA10_FMPLUS (1 << 23)
/* SYSCFG_EXTICR Values -- --------------------------------------------------*/
#define SYSCFG_EXTICR_SKIP 4
#define SYSCFG_EXTICR_GPIOA 0
#define SYSCFG_EXTICR_GPIOB 1
#define SYSCFG_EXTICR_GPIOC 2
#define SYSCFG_EXTICR_GPIOD 3
#define SYSCFG_EXTICR_GPIOF 5
/* SYSCFG_CFGR2 Values -- ---------------------------------------------------*/
#define SYSCFG_CFGR2_LOCKUP_LOCK (1 << 0)
#define SYSCFG_CFGR2_SRAM_PARITY_LOCK (1 << 1)
#define SYSCFG_CFGR2_PVD_LOCK (1 << 2)
#define SYSCFG_CFGR2_SRAM_PEF (1 << 8)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
END_DECLS
#endif

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/** @defgroup timer_defines Timers Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx Timers</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/

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/** @defgroup tsc_defines TSC Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx Touch Sensor</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_TSC_H
#define LIBOPENCM3_TSC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/memorymap.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
#define TSC TSC_BASE
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define TSC_CR MMIO32(TSC_BASE + 0x00)
#define TSC_IER MMIO32(TSC_BASE + 0x04)
#define TSC_ICR MMIO32(TSC_BASE + 0x08)
#define TSC_ISR MMIO32(TSC_BASE + 0x0c)
#define TSC_IOHCR MMIO32(TSC_BASE + 0x10)
#define TSC_IOASCR MMIO32(TSC_BASE + 0x18)
#define TSC_IOSCR MMIO32(TSC_BASE + 0x20)
#define TSC_IOCCR MMIO32(TSC_BASE + 0x28)
#define TSC_IOGCSR MMIO32(TSC_BASE + 0x30)
#define TSC_IOGxCR(x) MMIO8(TSC_BASE + 0x34 + (x)*4)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* TSC_CR Values ------------------------------------------------------------*/
#define TSC_CR_CTPH_SHIFT 28
#define TSC_CR_CTPH (0xF << TSC_CR_CTPH_SHIFT)
#define TSC_CR_CTPL_SHIFT 24
#define TSC_CR_CTPL (0x0F << TSC_CR_CTPL_SHIFT)
#define TSC_CR_SSD_SHIFT 17
#define TSC_CR_SSD (0x7F << TSC_CR_SSD_SHIFT)
#define TSC_CR_SSE (1 << 16)
#define TSC_CR_SSPSC (1 << 15)
#define TSC_CR_PGPSC_SHIFT 12
#define TSC_CR_PGPSC (7 << TSC_CR_PGPSC_SHIFT)
#define TSC_CR_MCV_SHIFT 5
#define TSC_CR_MCV (7 << TSC_CR_MCV_SHIFT)
#define TSC_CR_IODEF (1 << 4)
#define TSC_CR_SYNCPOL (1 << 3)
#define TSC_CR_AM (1 << 2)
#define TSC_CR_START (1 << 1)
#define TSC_CR_TSCE (1 << 0)
/* TSC_IER Values -----------------------------------------------------------*/
#define TSC_IER_MCEIE (1 << 1)
#define TSC_IER_EOAIE (1 << 0)
/* TSC_ICR Values -----------------------------------------------------------*/
#define TSC_ICR_MCEIC (1 << 1)
#define TSC_ICR_EOAIC (1 << 0)
/* TSC_ISR Values -----------------------------------------------------------*/
#define TSC_ISR_MCEF (1 << 1)
#define TSC_ISR_EOAF (1 << 0)
/* TSC_IOHCR Values ---------------------------------------------------------*/
/* Bit helper g = [1..6] io = [1..4] */
#define TSC_IOBIT_VAL(g, io) ((1 << ((io)-1)) << (((g)-1)*4))
#define TSC_IOHCR_G1(io) TSC_IOBIT_VAL(1, io)
#define TSC_IOHCR_G2(io) TSC_IOBIT_VAL(2, io)
#define TSC_IOHCR_G3(io) TSC_IOBIT_VAL(3, io)
#define TSC_IOHCR_G4(io) TSC_IOBIT_VAL(4, io)
#define TSC_IOHCR_G5(io) TSC_IOBIT_VAL(5, io)
#define TSC_IOHCR_G6(io) TSC_IOBIT_VAL(6, io)
/* TSC_IOASCR Values --------------------------------------------------------*/
#define TSC_IOASCR_G1(io) TSC_IOBIT_VAL(1, io)
#define TSC_IOASCR_G2(io) TSC_IOBIT_VAL(2, io)
#define TSC_IOASCR_G3(io) TSC_IOBIT_VAL(3, io)
#define TSC_IOASCR_G4(io) TSC_IOBIT_VAL(4, io)
#define TSC_IOASCR_G5(io) TSC_IOBIT_VAL(5, io)
#define TSC_IOASCR_G6(io) TSC_IOBIT_VAL(6, io)
/* TSC_IOSCR Values ---------------------------------------------------------*/
#define TSC_IOSCR_G1(io) TSC_IOBIT_VAL(1, io)
#define TSC_IOSCR_G2(io) TSC_IOBIT_VAL(2, io)
#define TSC_IOSCR_G3(io) TSC_IOBIT_VAL(3, io)
#define TSC_IOSCR_G4(io) TSC_IOBIT_VAL(4, io)
#define TSC_IOSCR_G5(io) TSC_IOBIT_VAL(5, io)
#define TSC_IOSCR_G6(io) TSC_IOBIT_VAL(6, io)
/* TSC_IOCCR Values ---------------------------------------------------------*/
#define TSC_IOCCR_G1(io) TSC_IOBIT_VAL(1, io)
#define TSC_IOCCR_G2(io) TSC_IOBIT_VAL(2, io)
#define TSC_IOCCR_G3(io) TSC_IOBIT_VAL(3, io)
#define TSC_IOCCR_G4(io) TSC_IOBIT_VAL(4, io)
#define TSC_IOCCR_G5(io) TSC_IOBIT_VAL(5, io)
#define TSC_IOCCR_G6(io) TSC_IOBIT_VAL(6, io)
/* TSC_IOGCSR Values --------------------------------------------------------*/
#define TSC_IOGCSR_GxE(x) (1 << ((x)-1))
#define TSC_IOGCSR_GxS(x) (1 << ((x)+15))
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
END_DECLS
#endif

319
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/** @defgroup usart_defines USART Defines
*
* @brief <b>Defined Constants and Types for the STM32F0xx USART</b>
*
* @ingroup STM32F0xx_defines
*
* @version 1.0.0
*
* @date 2 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_USART_H
#define LIBOPENCM3_USART_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/*****************************************************************************/
/* Module definitions */
/*****************************************************************************/
#define USART1 USART1_BASE
#define USART2 USART2_BASE
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
#define USART_CR1(usart_base) MMIO32(usart_base + 0x00)
#define USART1_CR1 USART_CR1(USART1_BASE)
#define USART2_CR1 USART_CR1(USART2_BASE)
#define USART_CR2(usart_base) MMIO32(usart_base + 0x04)
#define USART1_CR2 USART_CR2(USART1_BASE)
#define USART2_CR2 USART_CR2(USART2_BASE)
#define USART_CR3(usart_base) MMIO32(usart_base + 0x08)
#define USART1_CR3 USART_CR3(USART1_BASE)
#define USART2_CR3 USART_CR3(USART2_BASE)
#define USART_BRR(usart_base) MMIO32(usart_base + 0x0c)
#define USART1_BRR USART_BRR(USART1_BASE)
#define USART2_BRR USART_BRR(USART2_BASE)
#define USART_GTPR(usart_base) MMIO32(usart_base + 0x10)
#define USART1_GTPR USART_GTPR(USART1_BASE)
#define USART2_GTPR USART_GTPR(USART2_BASE)
#define USART_RTOR(usart_base) MMIO32(usart_base + 0x14)
#define USART1_RTOR USART_RTOR(USART1_BASE)
#define USART2_RTOR USART_RTOR(USART2_BASE)
#define USART_RQR(usart_base) MMIO32(usart_base + 0x18)
#define USART1_RQR USART_RQR(USART1_BASE)
#define USART2_RQR USART_RQR(USART2_BASE)
#define USART_ISR(usart_base) MMIO32(usart_base + 0x1c)
#define USART1_ISR USART_ISR(USART1_BASE)
#define USART2_ISR USART_ISR(USART2_BASE)
#define USART_ICR(usart_base) MMIO32(usart_base + 0x20)
#define USART1_ICR USART_ICR(USART1_BASE)
#define USART2_ICR USART_ICR(USART2_BASE)
#define USART_RDR(usart_base) MMIO8(usart_base + 0x24)
#define USART1_RDR USART_RDR(USART1_BASE)
#define USART2_RDR USART_RDR(USART2_BASE)
#define USART_TDR(usart_base) MMIO8(usart_base + 0x28)
#define USART1_TDR USART_TDR(USART1_BASE)
#define USART2_TDR USART_TDR(USART2_BASE)
/*****************************************************************************/
/* Register values */
/*****************************************************************************/
/* USART_CR1 Values ---------------------------------------------------------*/
#define USART_CR1_EOBIE (1 << 27)
#define USART_CR1_RTOIE (1 << 26)
#define USART_CR1_DEAT_SHIFT 21
#define USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT)
#define USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT)
#define USART_CR1_DEDT_SHIFT 16
#define USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT)
#define USART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT)
#define USART_CR1_OVER8 (1 << 15)
#define USART_CR1_CMIE (1 << 14)
#define USART_CR1_MME (1 << 13)
#define USART_CR1_M (1 << 12)
#define USART_CR1_WAKE (1 << 11)
#define USART_CR1_PCE (1 << 10)
#define USART_CR1_PS (1 << 9)
#define USART_CR1_PEIE (1 << 8)
#define USART_CR1_TXEIE (1 << 7)
#define USART_CR1_TCIE (1 << 6)
#define USART_CR1_RXNEIE (1 << 5)
#define USART_CR1_IDLEIE (1 << 4)
#define USART_CR1_TE (1 << 3)
#define USART_CR1_RE (1 << 2)
#define USART_CR1_UESM (1 << 1)
#define USART_CR1_UE (1 << 0)
/* USART_CR2 Values ---------------------------------------------------------*/
#define USART_CR2_ADD_SHIFT 24
#define USART_CR2_ADD (0xFF << USART_CR2_ADD_SHIFT)
#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)
#define USART_CR2_RTOEN (1 << 23)
#define USART_CR2_ABRMOD_SHIFT 21
#define USART_CR2_ABRMOD (3 << USART_CR2_ABRMOD_SHIFT)
#define USART_CR2_ABRMOD_STARTBIT (0 << USART_CR2_ABRMOD_SHIFT)
#define USART_CR2_ABRMOD_FALLTOFALL (1 << USART_CR2_ABRMOD_SHIFT)
#define USART_CR2_ABREN (1 << 20)
#define USART_CR2_MSBFIRST (1 << 19)
#define USART_CR2_DATAINV (1 << 18)
#define USART_CR2_TXINV (1 << 17)
#define USART_CR2_RXINV (1 << 16)
#define USART_CR2_SWAP (1 << 15)
#define USART_CR2_LINEN (1 << 14)
#define USART_CR2_STOP_SHIFT 12
#define USART_CR2_STOP (3 << USART_CR2_STOP_SHIFT)
#define USART_CR2_STOP_1_0BIT (0 << USART_CR2_STOP_SHIFT)
#define USART_CR2_STOP_2_0BIT (2 << USART_CR2_STOP_SHIFT)
#define USART_CR2_STOP_1_5BIT (3 << USART_CR2_STOP_SHIFT)
#define USART_CR2_CLKEN (1 << 11)
#define USART_CR2_CPOL (1 << 10)
#define USART_CR2_CPHA (1 << 9)
#define USART_CR2_LBCL (1 << 8)
#define USART_CR2_LBIDE (1 << 6)
#define USART_CR2_LBDL (1 << 5)
#define USART_CR2_ADDM (1 << 4)
/* USART_CR3 Values ---------------------------------------------------------*/
#define USART_CR3_WUFIE (1 << 22)
#define USART_CR3_WUS_SHIFT 20
#define USART_CR3_WUS (3 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUS_ADDRMATCH (0 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT)
#define USART_CR3_SCARCNT_SHIFT 17
#define USART_CR3_SCARCNT (7 << USART_CR3_SCARCNT_SHIFT)
#define USART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT)
#define USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT)
#define USART_CR3_DEP (1 << 15)
#define USART_CR3_DEM (1 << 14)
#define USART_CR3_DDRE (1 << 13)
#define USART_CR3_OVRDIS (1 << 12)
#define USART_CR3_ONEBIT (1 << 11)
#define USART_CR3_CTSIE (1 << 10)
#define USART_CR3_CTSE (1 << 9)
#define USART_CR3_RTSE (1 << 8)
#define USART_CR3_DMAT (1 << 7)
#define USART_CR3_DMAR (1 << 6)
#define USART_CR3_SCEN (1 << 5)
#define USART_CR3_NACK (1 << 4)
#define USART_CR3_HDSEL (1 << 3)
#define USART_CR3_IRLP (1 << 2)
#define USART_CR3_IREN (1 << 1)
#define USART_CR3_EIE (1 << 0)
/* USART_GTPR Values --------------------------------------------------------*/
#define USART_GTPR_GT_SHIFT 8
#define USART_GTPR_GT (0xFF << USART_GTPR_GT_SHIFT)
#define USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT)
#define USART_GTPR_PSC_SHIFT 0
#define USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT)
/* USART_RTOR Values --------------------------------------------------------*/
#define USART_RTOR_BLEN_SHIFT 24
#define USART_RTOR_BLEN (0xFF << USART_RTOR_BLEN_SHIFT)
#define USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT)
#define USART_RTOR_RTO_SHIFT 0
#define USART_RTOR_RTO (0xFF << USART_RTOR_RTO_SHIFT)
#define USART_RTOR_RTO_VAL(x) ((x) << USART_RTOR_RTO_SHIFT)
/* USART_RQR Values ---------------------------------------------------------*/
#define USART_RQR_TXFRQ (1 << 4)
#define USART_RQR_RXFRQ (1 << 3)
#define USART_RQR_MMRQ (1 << 2)
#define USART_RQR_SBKRQ (1 << 1)
#define USART_RQR_ABRRQ (1 << 0)
/* USART_ISR Values ---------------------------------------------------------*/
#define USART_ISR_REACK (1 << 22)
#define USART_ISR_TEACK (1 << 21)
#define USART_ISR_WUF (1 << 20)
#define USART_ISR_RWU (1 << 19)
#define USART_ISR_SBKF (1 << 18)
#define USART_ISR_CMF (1 << 17)
#define USART_ISR_BUSY (1 << 16)
#define USART_ISR_ABRF (1 << 15)
#define USART_ISR_ABRE (1 << 14)
#define USART_ISR_EOBF (1 << 12)
#define USART_ISR_RTOF (1 << 11)
#define USART_ISR_CTS (1 << 10)
#define USART_ISR_CTSIF (1 << 9)
#define USART_ISR_LBDF (1 << 8)
#define USART_ISR_TXE (1 << 7)
#define USART_ISR_TC (1 << 6)
#define USART_ISR_RXNE (1 << 5)
#define USART_ISR_IDLE (1 << 4)
#define USART_ISR_ORE (1 << 3)
#define USART_ISR_NF (1 << 2)
#define USART_ISR_FE (1 << 1)
#define USART_ISR_PE (1 << 0)
/* USART_ICR Values ---------------------------------------------------------*/
#define USART_ICR_WUCF (1 << 20)
#define USART_ICR_CMCF (1 << 17)
#define USART_ICR_EOBCF (1 << 12)
#define USART_ICR_RTOCF (1 << 11)
#define USART_ICR_CTSCF (1 << 9)
#define USART_ICR_LBDCF (1 << 8)
#define USART_ICR_TCCF (1 << 6)
#define USART_ICR_IDLECF (1 << 4)
#define USART_ICR_ORECF (1 << 3)
#define USART_ICR_NCF (1 << 2)
#define USART_ICR_FECF (1 << 1)
#define USART_ICR_PECF (1 << 0)
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
#define USART_PARITY (USART_CR1_PCE | USART_CR1_PS)
#define USART_PARITY_NONE (0)
#define USART_PARITY_EVEN (USART_CR1_PCE)
#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
#define USART_MODE (USART_CR1_TE | USART_CR1_RE)
#define USART_MODE_NONE (0)
#define USART_MODE_RX (USART_CR1_RE)
#define USART_MODE_TX (USART_CR1_TE)
#define USART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE)
#define USART_FLOWCONTROL (USART_CR3_RTSE | USART_CR3_CTSE)
#define USART_FLOWCONTROL_NONE (0)
#define USART_FLOWCONTROL_RTS (USART_CR3_RTSE)
#define USART_FLOWCONTROL_CTS (USART_CR3_CTSE)
#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
void usart_set_baudrate(uint32_t usart, uint32_t baud);
void usart_set_databits(uint32_t usart, uint32_t bits);
void usart_set_stopbits(uint32_t usart, uint32_t stopbits);
void usart_set_parity(uint32_t usart, uint32_t parity);
void usart_set_mode(uint32_t usart, uint32_t mode);
void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol);
void usart_enable(uint32_t usart);
void usart_disable(uint32_t usart);
void usart_send(uint32_t usart, uint8_t data);
uint8_t usart_recv(uint32_t usart);
void usart_wait_send_ready(uint32_t usart);
void usart_wait_recv_ready(uint32_t usart);
void usart_send_blocking(uint32_t usart, uint8_t data);
uint8_t usart_recv_blocking(uint32_t usart);
void usart_enable_rx_dma(uint32_t usart);
void usart_disable_rx_dma(uint32_t usart);
void usart_enable_tx_dma(uint32_t usart);
void usart_disable_tx_dma(uint32_t usart);
void usart_enable_rx_interrupt(uint32_t usart);
void usart_disable_rx_interrupt(uint32_t usart);
void usart_enable_tx_interrupt(uint32_t usart);
void usart_disable_tx_interrupt(uint32_t usart);
void usart_enable_error_interrupt(uint32_t usart);
void usart_disable_error_interrupt(uint32_t usart);
bool usart_get_flag(uint32_t usart, uint32_t flag);
bool usart_get_interrupt_source(uint32_t usart, uint32_t flag);
END_DECLS
#endif

709
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/f1/adc.h Normal file
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/** @defgroup adc_defines ADC Defines
@brief <b>Defined Constants and Types for the STM32F1xx Analog to Digital
Converters</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009
Edward Cheeseman <evbuilder@users.sourceforge.net>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_ADC_H
#define LIBOPENCM3_ADC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */
/* ADC port base addresses (for convenience) */
/****************************************************************************/
/** @defgroup adc_reg_base ADC register base addresses
@ingroup adc_defines
@{*/
#define ADC1 ADC1_BASE
#define ADC2 ADC2_BASE
#define ADC3 ADC3_BASE
/**@}*/
/* --- ADC registers ------------------------------------------------------- */
/* ADC status register (ADC_SR) */
#define ADC_SR(block) MMIO32(block + 0x00)
#define ADC1_SR ADC_SR(ADC1)
#define ADC2_SR ADC_SR(ADC2)
#define ADC3_SR ADC_SR(ADC3)
/* ADC control register 1 (ADC_CR1) */
#define ADC_CR1(block) MMIO32(block + 0x04)
#define ADC1_CR1 ADC_CR1(ADC1)
#define ADC2_CR1 ADC_CR1(ADC2)
#define ADC3_CR1 ADC_CR1(ADC3)
/* ADC control register 2 (ADC_CR2) */
#define ADC_CR2(block) MMIO32(block + 0x08)
#define ADC1_CR2 ADC_CR2(ADC1)
#define ADC2_CR2 ADC_CR2(ADC2)
#define ADC3_CR2 ADC_CR2(ADC3)
/* ADC sample time register 1 (ADC_SMPR1) */
#define ADC_SMPR1(block) MMIO32(block + 0x0c)
#define ADC1_SMPR1 ADC_SMPR1(ADC1)
#define ADC2_SMPR1 ADC_SMPR1(ADC2)
#define ADC3_SMPR1 ADC_SMPR1(ADC3)
/* ADC sample time register 2 (ADC_SMPR2) */
#define ADC_SMPR2(block) MMIO32(block + 0x10)
#define ADC1_SMPR2 ADC_SMPR2(ADC1)
#define ADC2_SMPR2 ADC_SMPR2(ADC2)
#define ADC3_SMPR2 ADC_SMPR2(ADC3)
/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
#define ADC_JOFR1(block) MMIO32(block + 0x14)
#define ADC_JOFR2(block) MMIO32(block + 0x18)
#define ADC_JOFR3(block) MMIO32(block + 0x1c)
#define ADC_JOFR4(block) MMIO32(block + 0x20)
#define ADC1_JOFR1 ADC_JOFR1(ADC1)
#define ADC2_JOFR1 ADC_JOFR1(ADC2)
#define ADC3_JOFR1 ADC_JOFR1(ADC3)
#define ADC1_JOFR2 ADC_JOFR2(ADC1)
#define ADC2_JOFR2 ADC_JOFR2(ADC2)
#define ADC3_JOFR2 ADC_JOFR2(ADC3)
#define ADC1_JOFR3 ADC_JOFR3(ADC1)
#define ADC2_JOFR3 ADC_JOFR3(ADC2)
#define ADC3_JOFR3 ADC_JOFR3(ADC3)
#define ADC1_JOFR4 ADC_JOFR4(ADC1)
#define ADC2_JOFR4 ADC_JOFR4(ADC2)
#define ADC3_JOFR4 ADC_JOFR4(ADC3)
/* ADC watchdog high threshold register (ADC_HTR) */
#define ADC_HTR(block) MMIO32(block + 0x24)
#define ADC1_HTR ADC_HTR(ADC1)
#define ADC2_HTR ADC_HTR(ADC2)
#define ADC3_HTR ADC_HTR(ADC3)
/* ADC watchdog low threshold register (ADC_LTR) */
#define ADC_LTR(block) MMIO32(block + 0x28)
#define ADC1_LTR ADC_LTR(ADC1_BASE)
#define ADC2_LTR ADC_LTR(ADC2_BASE)
#define ADC3_LTR ADC_LTR(ADC3_BASE)
/* ADC regular sequence register 1 (ADC_SQR1) */
#define ADC_SQR1(block) MMIO32(block + 0x2c)
#define ADC1_SQR1 ADC_SQR1(ADC1)
#define ADC2_SQR1 ADC_SQR1(ADC2)
#define ADC3_SQR1 ADC_SQR1(ADC3)
/* ADC regular sequence register 2 (ADC_SQR2) */
#define ADC_SQR2(block) MMIO32(block + 0x30)
#define ADC1_SQR2 ADC_SQR2(ADC1)
#define ADC2_SQR2 ADC_SQR2(ADC2)
#define ADC3_SQR2 ADC_SQR2(ADC3)
/* ADC regular sequence register 3 (ADC_SQR3) */
#define ADC_SQR3(block) MMIO32(block + 0x34)
#define ADC1_SQR3 ADC_SQR3(ADC1)
#define ADC2_SQR3 ADC_SQR3(ADC2)
#define ADC3_SQR3 ADC_SQR3(ADC3)
/* ADC injected sequence register (ADC_JSQR) */
#define ADC_JSQR(block) MMIO32(block + 0x38)
#define ADC1_JSQR ADC_JSQR(ADC1_BASE)
#define ADC2_JSQR ADC_JSQR(ADC2_BASE)
#define ADC3_JSQR ADC_JSQR(ADC3_BASE)
/* ADC injected data register x (ADC_JDRx) (x=1..4) */
#define ADC_JDR1(block) MMIO32(block + 0x3c)
#define ADC_JDR2(block) MMIO32(block + 0x40)
#define ADC_JDR3(block) MMIO32(block + 0x44)
#define ADC_JDR4(block) MMIO32(block + 0x48)
#define ADC1_JDR1 ADC_JDR1(ADC1)
#define ADC2_JDR1 ADC_JDR1(ADC2)
#define ADC3_JDR1 ADC_JDR1(ADC3)
#define ADC1_JDR2 ADC_JDR2(ADC1)
#define ADC2_JDR2 ADC_JDR2(ADC2)
#define ADC3_JDR2 ADC_JDR2(ADC3)
#define ADC1_JDR3 ADC_JDR3(ADC1)
#define ADC2_JDR3 ADC_JDR3(ADC2)
#define ADC3_JDR3 ADC_JDR3(ADC3)
#define ADC1_JDR4 ADC_JDR4(ADC1)
#define ADC2_JDR4 ADC_JDR4(ADC2)
#define ADC3_JDR4 ADC_JDR4(ADC3)
/* ADC regular data register (ADC_DR) */
#define ADC_DR(block) MMIO32(block + 0x4c)
#define ADC1_DR ADC_DR(ADC1)
#define ADC2_DR ADC_DR(ADC2)
#define ADC3_DR ADC_DR(ADC3)
/* --- ADC Channels ------------------------------------------------------- */
/****************************************************************************/
/** @defgroup adc_channel ADC Channel Numbers
@ingroup adc_defines
@{*/
#define ADC_CHANNEL0 0x00
#define ADC_CHANNEL1 0x01
#define ADC_CHANNEL2 0x02
#define ADC_CHANNEL3 0x03
#define ADC_CHANNEL4 0x04
#define ADC_CHANNEL5 0x05
#define ADC_CHANNEL6 0x06
#define ADC_CHANNEL7 0x07
#define ADC_CHANNEL8 0x08
#define ADC_CHANNEL9 0x09
#define ADC_CHANNEL10 0x0A
#define ADC_CHANNEL11 0x0B
#define ADC_CHANNEL12 0x0C
#define ADC_CHANNEL13 0x0D
#define ADC_CHANNEL14 0x0E
#define ADC_CHANNEL15 0x0F
#define ADC_CHANNEL16 0x10
#define ADC_CHANNEL17 0x11
/**@}*/
#define ADC_MASK 0x1F
#define ADC_SHIFT 0
/* --- ADC_SR values ------------------------------------------------------- */
#define ADC_SR_STRT (1 << 4)
#define ADC_SR_JSTRT (1 << 3)
#define ADC_SR_JEOC (1 << 2)
#define ADC_SR_EOC (1 << 1)
#define ADC_SR_AWD (1 << 0)
/* --- ADC_CR1 values ------------------------------------------------------ */
/* AWDEN: Analog watchdog enable on regular channels */
#define ADC_CR1_AWDEN (1 << 23)
/* JAWDEN: Analog watchdog enable on injected channels */
#define ADC_CR1_JAWDEN (1 << 22)
/* Note: Bits [21:20] are reserved, and must be kept at reset value. */
/* DUALMOD[3:0]: Dual mode selection. (ADC1 only) */
/* Legend:
* IND: Independent mode.
* CRSISM: Combined regular simultaneous + injected simultaneous mode.
* CRSATM: Combined regular simultaneous + alternate trigger mode.
* CISFIM: Combined injected simultaneous + fast interleaved mode.
* CISSIM: Combined injected simultaneous + slow interleaved mode.
* ISM: Injected simultaneous mode only.
* RSM: Regular simultaneous mode only.
* FIM: Fast interleaved mode only.
* SIM: Slow interleaved mode only.
* ATM: Alternate trigger mode only.
*/
/****************************************************************************/
/* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */
/** @defgroup adc_cr1_dualmod ADC Mode Selection
@ingroup adc_defines
@{*/
/** Independent (non-dual) mode */
#define ADC_CR1_DUALMOD_IND (0x0 << 16)
/** Combined regular simultaneous + injected simultaneous mode. */
#define ADC_CR1_DUALMOD_CRSISM (0x1 << 16)
/** Combined regular simultaneous + alternate trigger mode. */
#define ADC_CR1_DUALMOD_CRSATM (0x2 << 16)
/** Combined injected simultaneous + fast interleaved mode. */
#define ADC_CR1_DUALMOD_CISFIM (0x3 << 16)
/** Combined injected simultaneous + slow interleaved mode. */
#define ADC_CR1_DUALMOD_CISSIM (0x4 << 16)
/** Injected simultaneous mode only. */
#define ADC_CR1_DUALMOD_ISM (0x5 << 16)
/** Regular simultaneous mode only. */
#define ADC_CR1_DUALMOD_RSM (0x6 << 16)
/** Fast interleaved mode only. */
#define ADC_CR1_DUALMOD_FIM (0x7 << 16)
/** Slow interleaved mode only. */
#define ADC_CR1_DUALMOD_SIM (0x8 << 16)
/** Alternate trigger mode only. */
#define ADC_CR1_DUALMOD_ATM (0x9 << 16)
/**@}*/
#define ADC_CR1_DUALMOD_MASK (0xF << 16)
#define ADC_CR1_DUALMOD_SHIFT 16
/* DISCNUM[2:0]: Discontinuous mode channel count. */
/****************************************************************************/
/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
@ingroup adc_defines
@{*/
#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13)
#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13)
#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13)
#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13)
#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
/**@}*/
#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
#define ADC_CR1_DISCNUM_SHIFT 13
/* JDISCEN: */ /** Discontinuous mode on injected channels. */
#define ADC_CR1_JDISCEN (1 << 12)
/* DISCEN: */ /** Discontinuous mode on regular channels. */
#define ADC_CR1_DISCEN (1 << 11)
/* JAUTO: */ /** Automatic Injection Group conversion. */
#define ADC_CR1_JAUTO (1 << 10)
/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */
#define ADC_CR1_AWDSGL (1 << 9)
/* SCAN: */ /** Scan mode. */
#define ADC_CR1_SCAN (1 << 8)
/* JEOCIE: */ /** Interrupt enable for injected channels. */
#define ADC_CR1_JEOCIE (1 << 7)
/* AWDIE: */ /** Analog watchdog interrupt enable. */
#define ADC_CR1_AWDIE (1 << 6)
/* EOCIE: */ /** Interrupt enable EOC. */
#define ADC_CR1_EOCIE (1 << 5)
/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
/* Notes:
* ADC1: Analog channel 16 and 17 are internally connected to the temperature
* sensor and V_REFINT, respectively.
* ADC2: Analog channel 16 and 17 are internally connected to V_SS.
* ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
*/
/****************************************************************************/
/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */
/** @defgroup adc_watchdog_channel ADC watchdog channel
@ingroup adc_defines
@{*/
#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0)
#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0)
#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0)
#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0)
#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0)
#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0)
#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0)
#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0)
#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0)
#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0)
#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0)
#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0)
#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0)
#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0)
#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
/**@}*/
#define ADC_CR1_AWDCH_MASK (0x1F << 0)
#define ADC_CR1_AWDCH_SHIFT 0
/* --- ADC_CR2 values ------------------------------------------------------ */
/* TSVREFE: */ /** Temperature sensor and V_REFINT enable. (ADC1 only!) */
#define ADC_CR2_TSVREFE (1 << 23)
/* SWSTART: */ /** Start conversion of regular channels. */
#define ADC_CR2_SWSTART (1 << 22)
/* JSWSTART: */ /** Start conversion of injected channels. */
#define ADC_CR2_JSWSTART (1 << 21)
/* EXTTRIG: */ /** External trigger conversion mode for regular channels. */
#define ADC_CR2_EXTTRIG (1 << 20)
/* EXTSEL[2:0]: External event select for regular group. */
/* The following are only valid for ADC1 and ADC2. */
/****************************************************************************/
/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */
/** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2
@ingroup adc_defines
@{*/
/** Timer 1 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
/** Timer 1 Compare Output 2 */
#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
/** Timer 1 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
/** Timer 2 Compare Output 2 */
#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
/** Timer 3 Trigger Output */
#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
/** Timer 4 Compare Output 4 */
#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
/** External Interrupt 11 */
#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
/** Software Trigger */
#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
/**@}*/
/* The following are only valid for ADC3 */
/****************************************************************************/
/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */
/** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3
@ingroup adc_defines
@{*/
/** Timer 2 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17)
/** Timer 2 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17)
/** Timer 1 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
/** Timer 8 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17)
/** Timer 8 Trigger Output */
#define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17)
/** Timer 5 Compare Output 1 */
#define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17)
/** Timer 5 Compare Output 3 */
#define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17)
/**@}*/
#define ADC_CR2_EXTSEL_MASK (0x7 << 17)
#define ADC_CR2_EXTSEL_SHIFT 17
/* Note: Bit 16 is reserved, must be kept at reset value. */
/* JEXTTRIG: External trigger conversion mode for injected channels. */
#define ADC_CR2_JEXTTRIG (1 << 15)
/* JEXTSEL[2:0]: External event selection for injected group. */
/* The following are only valid for ADC1 and ADC2. */
/****************************************************************************/
/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */
/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1
and ADC2
@ingroup adc_defines
@{*/
/** Timer 1 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
/** Timer 1 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
/** Timer 2 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
/** Timer 2 Compare Output 1 */
#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
/** Timer 3 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
/** Timer 4 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
/** External Interrupt 15 */
#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
/** Injected Software Trigger */
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
/**@}*/
/* The following are the different meanings for ADC3 only. */
/****************************************************************************/
/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */
/** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3
@ingroup adc_defines
@{*/
/** Timer 1 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
/** Timer 1 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
/** Timer 4 Compare Output 3 */
#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12)
/** Timer 8 Compare Output 2 */
#define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12)
/** Timer 8 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
/** Timer 5 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
/** Timer 5 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
/** Injected Software Trigger */
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
/**@}*/
#define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
#define ADC_CR2_JEXTSEL_SHIFT 12
/* ALIGN: Data alignment. */
#define ADC_CR2_ALIGN_RIGHT (0 << 11)
#define ADC_CR2_ALIGN_LEFT (1 << 11)
#define ADC_CR2_ALIGN (1 << 11)
/* Note: Bits [10:9] are reserved and must be kept at reset value. */
/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */
#define ADC_CR2_DMA (1 << 8)
/* Note: Bits [7:4] are reserved and must be kept at reset value. */
/* RSTCAL: Reset calibration. */
#define ADC_CR2_RSTCAL (1 << 3)
/* CAL: A/D Calibration. */
#define ADC_CR2_CAL (1 << 2)
/* CONT: Continous conversion. */
#define ADC_CR2_CONT (1 << 1)
/* ADON: A/D converter On/Off. */
/* Note: If any other bit in this register apart from ADON is changed at the
* same time, then conversion is not triggered. This is to prevent triggering
* an erroneous conversion.
* Conclusion: Must be separately written.
*/
#define ADC_CR2_ADON (1 << 0)
/* --- ADC_SMPR1 values ---------------------------------------------------- */
#define ADC_SMPR1_SMP17_LSB 21
#define ADC_SMPR1_SMP16_LSB 18
#define ADC_SMPR1_SMP15_LSB 15
#define ADC_SMPR1_SMP14_LSB 12
#define ADC_SMPR1_SMP13_LSB 9
#define ADC_SMPR1_SMP12_LSB 6
#define ADC_SMPR1_SMP11_LSB 3
#define ADC_SMPR1_SMP10_LSB 0
#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB)
#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB)
#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB)
#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB)
#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB)
#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB)
#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB)
#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB)
/* --- ADC_SMPR2 values ---------------------------------------------------- */
#define ADC_SMPR2_SMP9_LSB 27
#define ADC_SMPR2_SMP8_LSB 24
#define ADC_SMPR2_SMP7_LSB 21
#define ADC_SMPR2_SMP6_LSB 18
#define ADC_SMPR2_SMP5_LSB 15
#define ADC_SMPR2_SMP4_LSB 12
#define ADC_SMPR2_SMP3_LSB 9
#define ADC_SMPR2_SMP2_LSB 6
#define ADC_SMPR2_SMP1_LSB 3
#define ADC_SMPR2_SMP0_LSB 0
#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB)
#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB)
#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB)
#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB)
#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB)
#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB)
#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB)
#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB)
#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB)
#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB)
/* --- ADC_SMPRx values --------------------------------------------------- */
/****************************************************************************/
/* ADC_SMPRG ADC Sample Time Selection for Channels */
/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
@ingroup adc_defines
@{*/
#define ADC_SMPR_SMP_1DOT5CYC 0x0
#define ADC_SMPR_SMP_7DOT5CYC 0x1
#define ADC_SMPR_SMP_13DOT5CYC 0x2
#define ADC_SMPR_SMP_28DOT5CYC 0x3
#define ADC_SMPR_SMP_41DOT5CYC 0x4
#define ADC_SMPR_SMP_55DOT5CYC 0x5
#define ADC_SMPR_SMP_71DOT5CYC 0x6
#define ADC_SMPR_SMP_239DOT5CYC 0x7
/**@}*/
/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */
#define ADC_JOFFSET_LSB 0
#define ADC_JOFFSET_MSK (0x7ff << 0)
#define ADC_HT_LSB 0
#define ADC_HT_MSK (0x7ff << 0)
#define ADC_LT_LSB 0
#define ADC_LT_MSK (0x7ff << 0)
/* --- ADC_SQR1 values ----------------------------------------------------- */
#define ADC_SQR1_L_LSB 20
#define ADC_SQR1_SQ16_LSB 15
#define ADC_SQR1_SQ15_LSB 10
#define ADC_SQR1_SQ14_LSB 5
#define ADC_SQR1_SQ13_LSB 0
#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
/* --- ADC_SQR2 values ----------------------------------------------------- */
#define ADC_SQR2_SQ12_LSB 25
#define ADC_SQR2_SQ11_LSB 20
#define ADC_SQR2_SQ10_LSB 15
#define ADC_SQR2_SQ9_LSB 10
#define ADC_SQR2_SQ8_LSB 5
#define ADC_SQR2_SQ7_LSB 0
#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
/* --- ADC_SQR3 values ----------------------------------------------------- */
#define ADC_SQR3_SQ6_LSB 25
#define ADC_SQR3_SQ5_LSB 20
#define ADC_SQR3_SQ4_LSB 15
#define ADC_SQR3_SQ3_LSB 10
#define ADC_SQR3_SQ2_LSB 5
#define ADC_SQR3_SQ1_LSB 0
#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
/* --- ADC_JSQR values ----------------------------------------------------- */
#define ADC_JSQR_JL_LSB 20
#define ADC_JSQR_JSQ4_LSB 15
#define ADC_JSQR_JSQ3_LSB 10
#define ADC_JSQR_JSQ2_LSB 5
#define ADC_JSQR_JSQ1_LSB 0
/* JL[2:0]: Discontinuous mode channel count injected channels. */
/****************************************************************************/
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode from
injected channels.
@ingroup adc_defines
@{*/
#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB)
/**@}*/
#define ADC_JSQR_JL_SHIFT 13
#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
#define ADC_JDATA_LSB 0
#define ADC_DATA_LSB 0
#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */
#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
#define ADC_DATA_MSK (0xffff << ADC_DA)
#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB)
/* ADC1 only (dual mode) */
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void adc_power_on(uint32_t adc);
void adc_start_conversion_direct(uint32_t adc);
void adc_set_single_channel(uint32_t adc, uint8_t channel);
void adc_set_dual_mode(uint32_t mode);
bool adc_eoc(uint32_t adc);
bool adc_eoc_injected(uint32_t adc);
uint32_t adc_read_regular(uint32_t adc);
uint32_t adc_read_injected(uint32_t adc, uint8_t reg);
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
void adc_enable_analog_watchdog_regular(uint32_t adc);
void adc_disable_analog_watchdog_regular(uint32_t adc);
void adc_enable_analog_watchdog_injected(uint32_t adc);
void adc_disable_analog_watchdog_injected(uint32_t adc);
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length);
void adc_disable_discontinuous_mode_regular(uint32_t adc);
void adc_enable_discontinuous_mode_injected(uint32_t adc);
void adc_disable_discontinuous_mode_injected(uint32_t adc);
void adc_enable_automatic_injected_group_conversion(uint32_t adc);
void adc_disable_automatic_injected_group_conversion(uint32_t adc);
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
uint8_t channel);
void adc_enable_scan_mode(uint32_t adc);
void adc_disable_scan_mode(uint32_t adc);
void adc_enable_eoc_interrupt_injected(uint32_t adc);
void adc_disable_eoc_interrupt_injected(uint32_t adc);
void adc_enable_awd_interrupt(uint32_t adc);
void adc_disable_awd_interrupt(uint32_t adc);
void adc_enable_eoc_interrupt(uint32_t adc);
void adc_disable_eoc_interrupt(uint32_t adc);
void adc_enable_temperature_sensor(uint32_t adc);
void adc_disable_temperature_sensor(uint32_t adc);
void adc_start_conversion_regular(uint32_t adc);
void adc_start_conversion_injected(uint32_t adc);
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger);
void adc_disable_external_trigger_regular(uint32_t adc);
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger);
void adc_disable_external_trigger_injected(uint32_t adc);
void adc_set_left_aligned(uint32_t adc);
void adc_set_right_aligned(uint32_t adc);
void adc_enable_dma(uint32_t adc);
void adc_disable_dma(uint32_t adc);
void adc_reset_calibration(uint32_t adc);
void adc_calibration(uint32_t adc);
void adc_set_continuous_conversion_mode(uint32_t adc);
void adc_set_single_conversion_mode(uint32_t adc);
void adc_on(uint32_t adc)
LIBOPENCM3_DEPRECATED("will be removed in the first release");
void adc_off(uint32_t adc);
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time);
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold);
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold);
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
void adc_set_continous_conversion_mode(uint32_t adc)
LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode");
void adc_set_conversion_time(uint32_t adc, uint8_t channel, uint8_t time)
LIBOPENCM3_DEPRECATED("change to adc_set_sample_time");
void adc_set_conversion_time_on_all_channels(uint32_t adc, uint8_t time)
LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels");
void adc_enable_jeoc_interrupt(uint32_t adc)
LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected");
void adc_disable_jeoc_interrupt(uint32_t adc)
LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected");
END_DECLS
#endif
/**@}*/

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_BKP_H
#define LIBOPENCM3_BKP_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- BKP registers ------------------------------------------------------- */
/* Backup data register 1 (BKP_DR1) */
#define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04)
/* Backup data register 2 (BKP_DR2) */
#define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08)
/* Backup data register 3 (BKP_DR3) */
#define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C)
/* Backup data register 4 (BKP_DR4) */
#define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10)
/* Backup data register 5 (BKP_DR5) */
#define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14)
/* Backup data register 6 (BKP_DR6) */
#define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18)
/* Backup data register 7 (BKP_DR7) */
#define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C)
/* Backup data register 8 (BKP_DR8) */
#define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20)
/* Backup data register 9 (BKP_DR9) */
#define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24)
/* Backup data register 10 (BKP_DR10) */
#define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28)
/* RTC clock calibration register (BKP_RTCCR) */
#define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C)
/* Backup control register (BKP_CR) */
#define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30)
/* Backup control/status register (BKP_CSR) */
#define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34)
/* Backup data register 11 (BKP_DR11) */
#define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40)
/* Backup data register 12 (BKP_DR12) */
#define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44)
/* Backup data register 13 (BKP_DR13) */
#define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48)
/* Backup data register 14 (BKP_DR14) */
#define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C)
/* Backup data register 15 (BKP_DR15) */
#define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50)
/* Backup data register 16 (BKP_DR16) */
#define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54)
/* Backup data register 17 (BKP_DR17) */
#define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58)
/* Backup data register 18 (BKP_DR18) */
#define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C)
/* Backup data register 19 (BKP_DR19) */
#define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60)
/* Backup data register 20 (BKP_DR20) */
#define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64)
/* Backup data register 21 (BKP_DR21) */
#define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68)
/* Backup data register 22 (BKP_DR22) */
#define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C)
/* Backup data register 23 (BKP_DR23) */
#define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70)
/* Backup data register 24 (BKP_DR24) */
#define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74)
/* Backup data register 25 (BKP_DR25) */
#define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78)
/* Backup data register 26 (BKP_DR26) */
#define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C)
/* Backup data register 27 (BKP_DR27) */
#define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80)
/* Backup data register 28 (BKP_DR28) */
#define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84)
/* Backup data register 29 (BKP_DR29) */
#define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88)
/* Backup data register 30 (BKP_DR30) */
#define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C)
/* Backup data register 31 (BKP_DR31) */
#define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90)
/* Backup data register 32 (BKP_DR32) */
#define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94)
/* Backup data register 33 (BKP_DR33) */
#define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98)
/* Backup data register 34 (BKP_DR34) */
#define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C)
/* Backup data register 35 (BKP_DR35) */
#define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0)
/* Backup data register 36 (BKP_DR36) */
#define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4)
/* Backup data register 37 (BKP_DR37) */
#define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8)
/* Backup data register 38 (BKP_DR38) */
#define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC)
/* Backup data register 39 (BKP_DR39) */
#define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0)
/* Backup data register 40 (BKP_DR40) */
#define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4)
/* Backup data register 41 (BKP_DR41) */
#define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8)
/* Backup data register 42 (BKP_DR42) */
#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC)
/* --- BKP_RTCCR values ---------------------------------------------------- */
/* ASOS: Alarm or second output selection */
#define BKP_RTCCR_ASOS (1 << 9)
/* ASOE: Alarm or second output enable */
#define BKP_RTCCR_ASOE (1 << 8)
/* CCO: Calibration clock output */
#define BKP_RTCCR_CCO (1 << 7)
/* CAL[6:0]: Calibration value */
#define BKP_RTCCR_CAL_LSB 0
/* --- BKP_CR values ------------------------------------------------------- */
/* TPAL: TAMPER pin active level */
#define BKP_CR_TAL (1 << 1)
/* TPE: TAMPER pin enable */
#define BKP_CR_TPE (1 << 0)
/* --- BKP_CSR values ------------------------------------------------------ */
/* TIF: Tamper interrupt flag */
#define BKP_CSR_TIF (1 << 9)
/* TEF: Tamper event flag */
#define BKP_CSR_TEF (1 << 8)
/* TPIE: TAMPER pin interrupt enable */
#define BKP_CSR_TPIE (1 << 2)
/* CTI: Clear tamper interrupt */
#define BKP_CSR_CTI (1 << 1)
/* CTE: Clear tamper event */
#define BKP_CSR_CTE (1 << 0)
/* --- BKP_DRx values ------------------------------------------------------ */
/* Bits[15:0]: Backup data */
/* --- BKP function prototypes --------------------------------------------- */
#endif

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/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx CRC
Generator </b>
@ingroup STM32F1xx_defines
@version 1.0.0
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CRC_H
#define LIBOPENCM3_CRC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/crc_common_all.h>
#endif

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/** @defgroup dac_defines DAC Defines
@brief <b>Defined Constants and Types for the STM32F1xx DAC</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@date 5 December 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_DAC_H
#define LIBOPENCM3_DAC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/dac_common_all.h>
#endif

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/** @defgroup dma_defines DMA Defines
@ingroup STM32F1xx_defines
@brief Defined Constants and Types for the STM32F1xx DMA Controller
@version 1.0.0
@date 30 November 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/dma_common_l1f013.h>
#endif

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/** @mainpage libopencm3 STM32F1
@version 1.0.0
@date 7 September 2012
API documentation for ST Microelectronics STM32F1 Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F1xx STM32F1xx
Libraries for ST Microelectronics STM32F1xx series.
@version 1.0.0
@date 7 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F1xx_defines STM32F1xx Defines
@brief Defined Constants and Types for the STM32F1xx series
@version 1.0.0
@date 7 September 2012
LGPL License Terms @ref lgpl_license
*/

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_ETHERNET_H
#define LIBOPENCM3_ETHERNET_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* Ethernet MAC registers */
#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00)
#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04)
#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08)
#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C)
#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10)
#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14)
#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18)
#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C)
#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28)
#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C)
#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38)
#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C)
#define ETH_MACA0HR MMIO32(ETHERNET_BASE + 0x40)
#define ETH_MACA0LR MMIO32(ETHERNET_BASE + 0x44)
#define ETH_MACA1HR MMIO32(ETHERNET_BASE + 0x48)
#define ETH_MACA1LR MMIO32(ETHERNET_BASE + 0x4C)
#define ETH_MACA2HR MMIO32(ETHERNET_BASE + 0x50)
#define ETH_MACA2LR MMIO32(ETHERNET_BASE + 0x54)
#define ETH_MACA3HR MMIO32(ETHERNET_BASE + 0x58)
#define ETH_MACA3LR MMIO32(ETHERNET_BASE + 0x5C)
/* Ethernet MMC registers */
#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100)
#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104)
#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108)
#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C)
#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110)
#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C)
#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150)
#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168)
#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194)
#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198)
#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4)
/* Ethrenet IEEE 1588 time stamp registers */
#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700)
#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704)
#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708)
#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C)
#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710)
#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714)
#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718)
#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C)
#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720)
/* Ethernet DMA registers */
#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000)
#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004)
#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008)
#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C)
#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010)
#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010)
#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014)
#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018)
#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C)
#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020)
#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048)
#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C)
#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050)
#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054)
/* Ethernet MAC Register bit definitions */
/* Ethernet MAC configuration register ETH_MACCR bits */
#define ETH_MACCR_RE 0x00000004
#define ETH_MACCR_TE 0x00000008
#define ETH_MACCR_DC 0x00000010
#define ETH_MACCR_BL 0x00000060
#define ETH_MACCR_APCS 0x00000080
#define ETH_MACCR_RD 0x00000200
#define ETH_MACCR_IPCO 0x00000400
#define ETH_MACCR_DM 0x00000800
#define ETH_MACCR_LM 0x00001000
#define ETH_MACCR_ROD 0x00002000
#define ETH_MACCR_FES 0x00004000
#define ETH_MACCR_CSD 0x00010000
#define ETH_MACCR_IFG 0x000E0000
#define ETH_MACCR_JD 0x00400000
#define ETH_MACCR_WD 0x00800000
/* Ethernet MAC frame filter register ETH_MACFFR bits */
#define ETH_MACFFR_PM 0x00000001
#define ETH_MACFFR_HU 0x00000002
#define ETH_MACFFR_HM 0x00000004
#define ETH_MACFFR_DAIF 0x00000008
#define ETH_MACFFR_PAM 0x00000010
#define ETH_MACFFR_BFD 0x00000020
#define ETH_MACFFR_PCF 0x000000C0
#define ETH_MACFFR_SAIF 0x00000100
#define ETH_MACFFR_SAF 0x00000200
#define ETH_MACFFR_HPF 0x00000400
#define ETH_MACFFR_PA 0x80000000
/* Ethernet MAC MII address register ETH_MACMIIAR bits */
#define ETH_MACMIIAR_MB 0x0001
#define ETH_MACMIIAR_MW 0x0002
/* Clock Range for MDC frequency */
#define ETH_MACMIIAR_CR_MASK 0x001C
#define ETH_MACMIIAR_CR_HCLK_DIV_42 0x0000 /* For HCLK 60-72 MHz */
#define ETH_MACMIIAR_CR_HCLK_DIV_16 0x0008 /* For HCLK 20-35 MHz */
#define ETH_MACMIIAR_CR_HCLK_DIV_24 0x000C /* For HCLK 35-60 MHz */
#define ETH_MACMIIAR_MR 0x07C0
#define ETH_MACMIIAR_PA 0xF800
/* Ethernet MAC flow control register ETH_MACFCR bits */
#define ETH_MACFCR_FCB 0x00000001
#define ETH_MACFCR_BPA 0x00000001
#define ETH_MACFCR_TFCE 0x00000002
#define ETH_MACFCR_RFCE 0x00000004
#define ETH_MACFCR_UPFD 0x00000008
#define ETH_MACFCR_PLT 0x00000030
#define ETH_MACFCR_ZQPD 0x00000080
#define ETH_MACFCR_PT 0xFFFF0000
/* Ethernet MAC interrupt status register ETH_MACSR bits */
#define ETH_MACSR_PMTS 0x0008
#define ETH_MACSR_MMCS 0x0010
#define ETH_MACSR_MMCRS 0x0020
#define ETH_MACSR_MMCTS 0x0040
#define ETH_MACSR_TSTS 0x0200
/* Ethernet MAC interrupt mask register ETH_MACIMR bits */
#define ETH_MACIMR_PMTIM 0x0008
#define ETH_MACIMR_TSTIM 0x0200
/* Ethernet DMA Register bit definitions */
/* Ethernet DMA bus mode register ETH_DMABMR bits */
#define ETH_DMABMR_SR 0x00000001
#define ETH_DMABMR_DA 0x00000002
#define ETH_DMABMR_DSL_MASK 0x0000007C
#define ETH_DMABMR_PBL_MASK 0x00003F00
#define ETH_DMABMR_RTPR_MASK 0x0000C000
#define ETH_DMABMR_RTPR_1TO1 0x00000000
#define ETH_DMABMR_RTPR_2TO1 0x00004000
#define ETH_DMABMR_RTPR_3TO1 0x00008000
#define ETH_DMABMR_RTPR_4TO1 0x0000C000
#define ETH_DMABMR_FB 0x00010000
#define ETH_DMABMR_RDP_MASK 0x007E0000
#define ETH_DMABMR_USP 0x00800000
#define ETH_DMABMR_FPM 0x01000000
#define ETH_DMABMR_AAB 0x02000000
/* Ethernet DMA operation mode register ETH_DMAOMR bits */
#define ETH_DMAOMR_SR 0x00000002
#define ETH_DMAOMR_OSF 0x00000004
#define ETH_DMAOMR_RTC_MASK 0x00000018
#define ETH_DMAOMR_RTC_64 0x00000000
#define ETH_DMAOMR_RTC_32 0x00000008
#define ETH_DMAOMR_RTC_96 0x00000010
#define ETH_DMAOMR_RTC_128 0x00000018
#define ETH_DMAOMR_FUGF 0x00000040
#define ETH_DMAOMR_FEF 0x00000080
#define ETH_DMAOMR_ST 0x00002000
#define ETH_DMAOMR_TTC_MASK 0x0001C000
#define ETH_DMAOMR_FTF 0x00100000
#define ETH_DMAOMR_TSF 0x00200000
#define ETH_DMAOMR_DFRF 0x01000000
#define ETH_DMAOMR_RSF 0x02000000
#define ETH_DMAOMR_DTCEFD 0x04000000
/* Ethernet DMA interrupt enable register ETH_DMAIER bits */
#define ETH_DMAIER_TIE 0x00000001
#define ETH_DMAIER_TPSIE 0x00000002
#define ETH_DMAIER_TBUIE 0x00000004
#define ETH_DMAIER_TJTIE 0x00000008
#define ETH_DMAIER_ROIE 0x00000010
#define ETH_DMAIER_TUIE 0x00000020
#define ETH_DMAIER_RIE 0x00000040
#define ETH_DMAIER_RBUIE 0x00000080
#define ETH_DMAIER_RPSIE 0x00000100
#define ETH_DMAIER_RWTIE 0x00000200
#define ETH_DMAIER_ETIE 0x00000400
#define ETH_DMAIER_FBEIE 0x00002000
#define ETH_DMAIER_ERIE 0x00004000
#define ETH_DMAIER_AISE 0x00008000
#define ETH_DMAIER_NSIE 0x00010000
BEGIN_DECLS
void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data);
uint16_t eth_smi_read(uint8_t phy, uint8_t reg);
END_DECLS
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Piotr Esden-Tempski <piotr@esden.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_EXTI_H
#define LIBOPENCM3_EXTI_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/exti_common_all.h>
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* For details see:
* PM0075 programming manual: STM32F10xxx Flash programming
* August 2010, Doc ID 17863 Rev 1
* https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/CD00283419.pdf
*/
#ifndef LIBOPENCM3_FLASH_H
#define LIBOPENCM3_FLASH_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- FLASH registers ----------------------------------------------------- */
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C)
#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_ACR_PRFTBS (1 << 5)
#define FLASH_ACR_PRFTBE (1 << 4)
#define FLASH_ACR_HLFCYA (1 << 3)
#define FLASH_ACR_LATENCY_0WS 0x00
#define FLASH_ACR_LATENCY_1WS 0x01
#define FLASH_ACR_LATENCY_2WS 0x02
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_SR_EOP (1 << 5)
#define FLASH_SR_WRPRTERR (1 << 4)
#define FLASH_SR_PGERR (1 << 2)
#define FLASH_SR_BSY (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_CR_EOPIE (1 << 12)
#define FLASH_CR_ERRIE (1 << 10)
#define FLASH_CR_OPTWRE (1 << 9)
#define FLASH_CR_LOCK (1 << 7)
#define FLASH_CR_STRT (1 << 6)
#define FLASH_CR_OPTER (1 << 5)
#define FLASH_CR_OPTPG (1 << 4)
#define FLASH_CR_MER (1 << 2)
#define FLASH_CR_PER (1 << 1)
#define FLASH_CR_PG (1 << 0)
/* --- FLASH_OBR values ---------------------------------------------------- */
/* FLASH_OBR[25:18]: Data1 */
/* FLASH_OBR[17:10]: Data0 */
#define FLASH_OBR_NRST_STDBY (1 << 4)
#define FLASH_OBR_NRST_STOP (1 << 3)
#define FLASH_OBR_WDG_SW (1 << 2)
#define FLASH_OBR_RDPRT (1 << 1)
#define FLASH_OBR_OPTERR (1 << 0)
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_RDP_KEY ((uint16_t)0x00a5)
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void flash_prefetch_buffer_enable(void);
void flash_prefetch_buffer_disable(void);
void flash_halfcycle_enable(void);
void flash_halfcycle_disable(void);
void flash_set_ws(uint32_t ws);
void flash_unlock(void);
void flash_lock(void);
void flash_clear_pgerr_flag(void);
void flash_clear_eop_flag(void);
void flash_clear_wrprterr_flag(void);
void flash_clear_bsy_flag(void);
void flash_clear_status_flags(void);
uint32_t flash_get_status_flags(void);
void flash_unlock_option_bytes(void);
void flash_erase_all_pages(void);
void flash_erase_page(uint32_t page_address);
void flash_program_word(uint32_t address, uint32_t data);
void flash_program_half_word(uint32_t address, uint16_t data);
void flash_wait_for_last_operation(void);
void flash_erase_option_bytes(void);
void flash_program_option_bytes(uint32_t address, uint16_t data);
END_DECLS
#endif

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/** @defgroup gpio_defines GPIO Defines
@brief <b>Defined Constants and Types for the STM32F1xx General Purpose I/O</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@date 1 July 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/gpio_common_all.h>
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
/** @defgroup gpio_port_id GPIO Port IDs
@ingroup gpio_defines
@{*/
/* GPIO port base addresses (for convenience) */
#define GPIOA GPIO_PORT_A_BASE
#define GPIOB GPIO_PORT_B_BASE
#define GPIOC GPIO_PORT_C_BASE
#define GPIOD GPIO_PORT_D_BASE
#define GPIOE GPIO_PORT_E_BASE
#define GPIOF GPIO_PORT_F_BASE
#define GPIOG GPIO_PORT_G_BASE
/**@}*/
/* --- Alternate function GPIOs -------------------------------------------- */
/* Default alternate functions of some pins (with and without remapping) */
/* CAN1 / CAN GPIO */
#define GPIO_CAN1_RX GPIO11 /* PA11 */
#define GPIO_CAN1_TX GPIO12 /* PA12 */
#define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */
#define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */
#define GPIO_CAN_PB_RX GPIO8 /* PB8 */
#define GPIO_CAN_PB_TX GPIO9 /* PB9 */
#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */
#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */
#define GPIO_CAN_PD_RX GPIO0 /* PD0 */
#define GPIO_CAN_PD_TX GPIO1 /* PD1 */
#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */
#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */
/* CAN1 / CAN BANK */
#define GPIO_BANK_CAN1_RX GPIOA /* PA11 */
#define GPIO_BANK_CAN1_TX GPIOA /* PA12 */
#define GPIO_BANK_CAN_RX GPIO_BANK_CAN1_RX /* Alias */
#define GPIO_BANK_CAN_TX GPIO_BANK_CAN1_TX /* Alias */
#define GPIO_BANK_CAN_PB_RX GPIOB /* PB8 */
#define GPIO_BANK_CAN_PB_TX GPIOB /* PB9 */
#define GPIO_BANK_CAN1_PB_RX GPIO_BANK_CAN_PB_RX /* Alias */
#define GPIO_BANK_CAN1_PB_TX GPIO_BANK_CAN_PB_TX /* Alias */
#define GPIO_BANK_CAN_PD_RX GPIOD /* PD0 */
#define GPIO_BANK_CAN_PD_TX GPIOD /* PD1 */
#define GPIO_BANK_CAN1_PD_RX GPIO_BANK_CAN_PD_RX /* Alias */
#define GPIO_BANK_CAN1_PD_TX GPIO_BANK_CAN_PD_TX /* Alias */
/* CAN2 GPIO */
#define GPIO_CAN2_RX GPIO12 /* PB12 */
#define GPIO_CAN2_TX GPIO13 /* PB13 */
#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */
#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */
/* CAN2 BANK */
#define GPIO_BANK_CAN2_RX GPIOB /* PB12 */
#define GPIO_BANK_CAN2_TX GPIOB /* PB13 */
#define GPIO_BANK_CAN2_RE_RX GPIOB /* PB5 */
#define GPIO_BANK_CAN2_RE_TX GPIOB /* PB6 */
/* JTAG/SWD GPIO */
#define GPIO_JTMS_SWDIO GPIO13 /* PA13 */
#define GPIO_JTCK_SWCLK GPIO14 /* PA14 */
#define GPIO_JTDI GPIO15 /* PA15 */
#define GPIO_JTDO_TRACESWO GPIO3 /* PB3 */
#define GPIO_JNTRST GPIO4 /* PB4 */
#define GPIO_TRACECK GPIO2 /* PE2 */
#define GPIO_TRACED0 GPIO3 /* PE3 */
#define GPIO_TRACED1 GPIO4 /* PE4 */
#define GPIO_TRACED2 GPIO5 /* PE5 */
#define GPIO_TRACED3 GPIO6 /* PE6 */
/* JTAG/SWD BANK */
#define GPIO_BANK_JTMS_SWDIO GPIOA /* PA13 */
#define GPIO_BANK_JTCK_SWCLK GPIOA /* PA14 */
#define GPIO_BANK_JTDI GPIOA /* PA15 */
#define GPIO_BANK_JTDO_TRACESWO GPIOB /* PB3 */
#define GPIO_BANK_JNTRST GPIOB /* PB4 */
#define GPIO_BANK_TRACECK GPIOE /* PE2 */
#define GPIO_BANK_TRACED0 GPIOE /* PE3 */
#define GPIO_BANK_TRACED1 GPIOE /* PE4 */
#define GPIO_BANK_TRACED2 GPIOE /* PE5 */
#define GPIO_BANK_TRACED3 GPIOE /* PE6 */
/* Timer5 GPIO */
#define GPIO_TIM5_CH1 GPIO0 /* PA0 */
#define GPIO_TIM5_CH2 GPIO1 /* PA1 */
#define GPIO_TIM5_CH3 GPIO2 /* PA2 */
#define GPIO_TIM5_CH4 GPIO3 /* PA3 */
/* Timer5 BANK */
#define GPIO_BANK_TIM5_CH1 GPIOA /* PA0 */
#define GPIO_BANK_TIM5_CH2 GPIOA /* PA1 */
#define GPIO_BANK_TIM5_CH3 GPIOA /* PA2 */
#define GPIO_BANK_TIM5_CH4 GPIOA /* PA3 */
#define GPIO_BANK_TIM5 GPIOA
/* Timer4 GPIO */
#define GPIO_TIM4_CH1 GPIO6 /* PB6 */
#define GPIO_TIM4_CH2 GPIO7 /* PB7 */
#define GPIO_TIM4_CH3 GPIO8 /* PB8 */
#define GPIO_TIM4_CH4 GPIO9 /* PB9 */
#define GPIO_TIM4_RE_CH1 GPIO12 /* PD12 */
#define GPIO_TIM4_RE_CH2 GPIO13 /* PD13 */
#define GPIO_TIM4_RE_CH3 GPIO14 /* PD14 */
#define GPIO_TIM4_RE_CH4 GPIO15 /* PD15 */
/* Timer4 BANK */
#define GPIO_BANK_TIM4_CH1 GPIOB /* PB6 */
#define GPIO_BANK_TIM4_CH2 GPIOB /* PB7 */
#define GPIO_BANK_TIM4_CH3 GPIOB /* PB8 */
#define GPIO_BANK_TIM4_CH4 GPIOB /* PB9 */
#define GPIO_BANK_TIM4 GPIOB
#define GPIO_BANK_TIM4_RE_CH1 GPIOD /* PD12 */
#define GPIO_BANK_TIM4_RE_CH2 GPIOD /* PD13 */
#define GPIO_BANK_TIM4_RE_CH3 GPIOD /* PD14 */
#define GPIO_BANK_TIM4_RE_CH4 GPIOD /* PD15 */
#define GPIO_BANK_TIM4_RE GPIOD
/* Timer3 GPIO */
#define GPIO_TIM3_CH1 GPIO6 /* PA6 */
#define GPIO_TIM3_CH2 GPIO7 /* PA7 */
#define GPIO_TIM3_CH3 GPIO0 /* PB0 */
#define GPIO_TIM3_CH4 GPIO1 /* PB1 */
#define GPIO_TIM3_PR_CH1 GPIO4 /* PB4 */
#define GPIO_TIM3_PR_CH2 GPIO5 /* PB5 */
#define GPIO_TIM3_PR_CH3 GPIO0 /* PB0 */
#define GPIO_TIM3_PR_CH4 GPIO1 /* PB1 */
#define GPIO_TIM3_FR_CH1 GPIO6 /* PC6 */
#define GPIO_TIM3_FR_CH2 GPIO7 /* PC7 */
#define GPIO_TIM3_FR_CH3 GPIO8 /* PC8 */
#define GPIO_TIM3_FR_CH4 GPIO9 /* PC9 */
/* Timer3 BANK */
#define GPIO_BANK_TIM3_CH1 GPIOA /* PA6 */
#define GPIO_BANK_TIM3_CH2 GPIOA /* PA7 */
#define GPIO_BANK_TIM3_CH3 GPIOB /* PB0 */
#define GPIO_BANK_TIM3_CH4 GPIOB /* PB1 */
#define GPIO_BANK_TIM3_CH12 GPIOA
#define GPIO_BANK_TIM3_CH34 GPIOB
#define GPIO_BANK_TIM3_PR_CH1 GPIOB /* PB4 */
#define GPIO_BANK_TIM3_PR_CH2 GPIOB /* PB5 */
#define GPIO_BANK_TIM3_PR_CH3 GPIOB /* PB0 */
#define GPIO_BANK_TIM3_PR_CH4 GPIOB /* PB1 */
#define GPIO_BANK_TIM3_PR GPIOB
#define GPIO_BANK_TIM3_FR_CH1 GPIOC /* PC6 */
#define GPIO_BANK_TIM3_FR_CH2 GPIOC /* PC7 */
#define GPIO_BANK_TIM3_FR_CH3 GPIOC /* PC8 */
#define GPIO_BANK_TIM3_FR_CH4 GPIOC /* PC9 */
#define GPIO_BANK_TIM3_FR GPIOC
/* Timer2 GPIO */
#define GPIO_TIM2_CH1_ETR GPIO0 /* PA0 */
#define GPIO_TIM2_CH2 GPIO1 /* PA1 */
#define GPIO_TIM2_CH3 GPIO2 /* PA2 */
#define GPIO_TIM2_CH4 GPIO3 /* PA3 */
#define GPIO_TIM2_PR1_CH1_ETR GPIO15 /* PA15 */
#define GPIO_TIM2_PR1_CH2 GPIO3 /* PB3 */
#define GPIO_TIM2_PR1_CH3 GPIO2 /* PA2 */
#define GPIO_TIM2_PR1_CH4 GPIO3 /* PA3 */
#define GPIO_TIM2_PR2_CH1_ETR GPIO0 /* PA0 */
#define GPIO_TIM2_PR2_CH2 GPIO1 /* PA1 */
#define GPIO_TIM2_PR2_CH3 GPIO10 /* PB10 */
#define GPIO_TIM2_PR2_CH4 GPIO11 /* PB11 */
#define GPIO_TIM2_FR_CH1_ETR GPIO15 /* PA15 */
#define GPIO_TIM2_FR_CH2 GPIO3 /* PB3 */
#define GPIO_TIM2_FR_CH3 GPIO10 /* PB10 */
#define GPIO_TIM2_FR_CH4 GPIO11 /* PB11 */
/* Timer2 BANK */
#define GPIO_BANK_TIM2_CH1_ETR GPIOA /* PA0 */
#define GPIO_BANK_TIM2_CH2 GPIOA /* PA1 */
#define GPIO_BANK_TIM2_CH3 GPIOA /* PA2 */
#define GPIO_BANK_TIM2_CH4 GPIOA /* PA3 */
#define GPIO_BANK_TIM2 GPIOA
#define GPIO_BANK_TIM2_PR1_CH1_ETR GPIOA /* PA15 */
#define GPIO_BANK_TIM2_PR1_CH2 GPIOB /* PB3 */
#define GPIO_BANK_TIM2_PR1_CH3 GPIOA /* PA2 */
#define GPIO_BANK_TIM2_PR1_CH4 GPIOA /* PA3 */
#define GPIO_BANK_TIM2_PR1_CH134 GPIOA
#define GPIO_BANK_TIM2_PR2_CH1_ETR GPIOA /* PA0 */
#define GPIO_BANK_TIM2_PR2_CH2 GPIOA /* PA1 */
#define GPIO_BANK_TIM2_PR2_CH3 GPIOB /* PB10 */
#define GPIO_BANK_TIM2_PR2_CH4 GPIOB /* PB11 */
#define GPIO_BANK_TIM2_PR2_CH12 GPIOA
#define GPIO_BANK_TIM2_PR2_CH34 GPIOB
#define GPIO_BANK_TIM2_FR_CH1_ETR GPIOA /* PA15 */
#define GPIO_BANK_TIM2_FR_CH2 GPIOB /* PB3 */
#define GPIO_BANK_TIM2_FR_CH3 GPIOB /* PB10 */
#define GPIO_BANK_TIM2_FR_CH4 GPIOB /* PB11 */
#define GPIO_BANK_TIM2_FR_CH234 GPIOB
/* Timer1 GPIO */
#define GPIO_TIM1_ETR GPIO12 /* PA12 */
#define GPIO_TIM1_CH1 GPIO8 /* PA8 */
#define GPIO_TIM1_CH2 GPIO9 /* PA9 */
#define GPIO_TIM1_CH3 GPIO10 /* PA10 */
#define GPIO_TIM1_CH4 GPIO11 /* PA11 */
#define GPIO_TIM1_BKIN GPIO12 /* PB12 */
#define GPIO_TIM1_CH1N GPIO13 /* PB13 */
#define GPIO_TIM1_CH2N GPIO14 /* PB14 */
#define GPIO_TIM1_CH3N GPIO15 /* PB15 */
#define GPIO_TIM1_PR_ETR GPIO12 /* PA12 */
#define GPIO_TIM1_PR_CH1 GPIO8 /* PA8 */
#define GPIO_TIM1_PR_CH2 GPIO9 /* PA9 */
#define GPIO_TIM1_PR_CH3 GPIO10 /* PA10 */
#define GPIO_TIM1_PR_CH4 GPIO11 /* PA11 */
#define GPIO_TIM1_PR_BKIN GPIO6 /* PA6 */
#define GPIO_TIM1_PR_CH1N GPIO7 /* PA7 */
#define GPIO_TIM1_PR_CH2N GPIO0 /* PB0 */
#define GPIO_TIM1_PR_CH3N GPIO1 /* PB1 */
#define GPIO_TIM1_FR_ETR GPIO7 /* PE7 */
#define GPIO_TIM1_FR_CH1 GPIO9 /* PE9 */
#define GPIO_TIM1_FR_CH2 GPIO11 /* PE11 */
#define GPIO_TIM1_FR_CH3 GPIO13 /* PE13 */
#define GPIO_TIM1_FR_CH4 GPIO14 /* PE14 */
#define GPIO_TIM1_FR_BKIN GPIO15 /* PE15 */
#define GPIO_TIM1_FR_CH1N GPIO8 /* PE8 */
#define GPIO_TIM1_FR_CH2N GPIO10 /* PE10 */
#define GPIO_TIM1_FR_CH3N GPIO12 /* PE12 */
/* Timer1 BANK */
#define GPIO_BANK_TIM1_ETR GPIOA /* PA12 */
#define GPIO_BANK_TIM1_CH1 GPIOA /* PA8 */
#define GPIO_BANK_TIM1_CH2 GPIOA /* PA9 */
#define GPIO_BANK_TIM1_CH3 GPIOA /* PA10 */
#define GPIO_BANK_TIM1_CH4 GPIOA /* PA11 */
#define GPIO_BANK_TIM1_BKIN GPIOB /* PB12 */
#define GPIO_BANK_TIM1_CH1N GPIOB /* PB13 */
#define GPIO_BANK_TIM1_CH2N GPIOB /* PB14 */
#define GPIO_BANK_TIM1_CH3N GPIOB /* PB15 */
#define GPIO_BANK_TIM1_ETR_CH1234 GPIOA
#define GPIO_BANK_TIM1_BKIN_CH123N GPIOB
#define GPIO_BANK_TIM1_PR_ETR GPIOA /* PA12 */
#define GPIO_BANK_TIM1_PR_CH1 GPIOA /* PA8 */
#define GPIO_BANK_TIM1_PR_CH2 GPIOA /* PA9 */
#define GPIO_BANK_TIM1_PR_CH3 GPIOA /* PA10 */
#define GPIO_BANK_TIM1_PR_CH4 GPIOA /* PA11 */
#define GPIO_BANK_TIM1_PR_BKIN GPIOA /* PA6 */
#define GPIO_BANK_TIM1_PR_CH1N GPIOA /* PA7 */
#define GPIO_BANK_TIM1_PR_CH2N GPIOB /* PB0 */
#define GPIO_BANK_TIM1_PR_CH3N GPIOB /* PB1 */
#define GPIO_BANK_TIM1_PR_ETR_CH1234_BKIN_CH1N GPIOA
#define GPIO_BANK_TIM1_PR_CH23N GPIOB
#define GPIO_BANK_TIM1_FR_ETR GPIOE /* PE7 */
#define GPIO_BANK_TIM1_FR_CH1 GPIOE /* PE9 */
#define GPIO_BANK_TIM1_FR_CH2 GPIOE /* PE11 */
#define GPIO_BANK_TIM1_FR_CH3 GPIOE /* PE13 */
#define GPIO_BANK_TIM1_FR_CH4 GPIOE /* PE14 */
#define GPIO_BANK_TIM1_FR_BKIN GPIOE /* PE15 */
#define GPIO_BANK_TIM1_FR_CH1N GPIOE /* PE8 */
#define GPIO_BANK_TIM1_FR_CH2N GPIOE /* PE10 */
#define GPIO_BANK_TIM1_FR_CH3N GPIOE /* PE12 */
#define GPIO_BANK_TIM1_FR GPIOE
/* UART5 GPIO */
#define GPIO_UART5_TX GPIO12 /* PC12 */
#define GPIO_UART5_RX GPIO2 /* PD2 */
/* UART5 BANK */
#define GPIO_BANK_UART5_TX GPIOC /* PC12 */
#define GPIO_BANK_UART5_RX GPIOD /* PD2 */
/* UART4 GPIO */
#define GPIO_UART4_TX GPIO10 /* PC10 */
#define GPIO_UART4_RX GPIO11 /* PC11 */
/* UART4 BANK */
#define GPIO_BANK_UART4_TX GPIOC /* PC10 */
#define GPIO_BANK_UART4_RX GPIOC /* PC11 */
/* USART3 GPIO */
#define GPIO_USART3_TX GPIO10 /* PB10 */
#define GPIO_USART3_RX GPIO11 /* PB11 */
#define GPIO_USART3_CK GPIO12 /* PB12 */
#define GPIO_USART3_CTS GPIO13 /* PB13 */
#define GPIO_USART3_RTS GPIO14 /* PB14 */
#define GPIO_USART3_PR_TX GPIO10 /* PC10 */
#define GPIO_USART3_PR_RX GPIO11 /* PC11 */
#define GPIO_USART3_PR_CK GPIO12 /* PC12 */
#define GPIO_USART3_PR_CTS GPIO13 /* PB13 */
#define GPIO_USART3_PR_RTS GPIO14 /* PB14 */
#define GPIO_USART3_FR_TX GPIO8 /* PD8 */
#define GPIO_USART3_FR_RX GPIO9 /* PD9 */
#define GPIO_USART3_FR_CK GPIO10 /* PD10 */
#define GPIO_USART3_FR_CTS GPIO11 /* PD11 */
#define GPIO_USART3_FR_RTS GPIO12 /* PD12 */
/* USART3 BANK */
#define GPIO_BANK_USART3_TX GPIOB /* PB10 */
#define GPIO_BANK_USART3_RX GPIOB /* PB11 */
#define GPIO_BANK_USART3_CK GPIOB /* PB12 */
#define GPIO_BANK_USART3_CTS GPIOB /* PB13 */
#define GPIO_BANK_USART3_RTS GPIOB /* PB14 */
#define GPIO_BANK_USART3_PR_TX GPIOC /* PC10 */
#define GPIO_BANK_USART3_PR_RX GPIOC /* PC11 */
#define GPIO_BANK_USART3_PR_CK GPIOC /* PC12 */
#define GPIO_BANK_USART3_PR_CTS GPIOB /* PB13 */
#define GPIO_BANK_USART3_PR_RTS GPIOB /* PB14 */
#define GPIO_BANK_USART3_FR_TX GPIOD /* PD8 */
#define GPIO_BANK_USART3_FR_RX GPIOD /* PD9 */
#define GPIO_BANK_USART3_FR_CK GPIOD /* PD10 */
#define GPIO_BANK_USART3_FR_CTS GPIOD /* PD11 */
#define GPIO_BANK_USART3_FR_RTS GPIOD /* PD12 */
/* USART2 GPIO */
#define GPIO_USART2_CTS GPIO0 /* PA0 */
#define GPIO_USART2_RTS GPIO1 /* PA1 */
#define GPIO_USART2_TX GPIO2 /* PA2 */
#define GPIO_USART2_RX GPIO3 /* PA3 */
#define GPIO_USART2_CK GPIO4 /* PA4 */
#define GPIO_USART2_RE_CTS GPIO3 /* PD3 */
#define GPIO_USART2_RE_RTS GPIO4 /* PD4 */
#define GPIO_USART2_RE_TX GPIO5 /* PD5 */
#define GPIO_USART2_RE_RX GPIO6 /* PD6 */
#define GPIO_USART2_RE_CK GPIO7 /* PD7 */
/* USART2 BANK */
#define GPIO_BANK_USART2_CTS GPIOA /* PA0 */
#define GPIO_BANK_USART2_RTS GPIOA /* PA1 */
#define GPIO_BANK_USART2_TX GPIOA /* PA2 */
#define GPIO_BANK_USART2_RX GPIOA /* PA3 */
#define GPIO_BANK_USART2_CK GPIOA /* PA4 */
#define GPIO_BANK_USART2_RE_CTS GPIOD /* PD3 */
#define GPIO_BANK_USART2_RE_RTS GPIOD /* PD4 */
#define GPIO_BANK_USART2_RE_TX GPIOD /* PD5 */
#define GPIO_BANK_USART2_RE_RX GPIOD /* PD6 */
#define GPIO_BANK_USART2_RE_CK GPIOD /* PD7 */
/* USART1 GPIO */
#define GPIO_USART1_TX GPIO9 /* PA9 */
#define GPIO_USART1_RX GPIO10 /* PA10 */
#define GPIO_USART1_RE_TX GPIO6 /* PB6 */
#define GPIO_USART1_RE_RX GPIO7 /* PB7 */
/* USART1 BANK */
#define GPIO_BANK_USART1_TX GPIOA /* PA9 */
#define GPIO_BANK_USART1_RX GPIOA /* PA10 */
#define GPIO_BANK_USART1_RE_TX GPIOB /* PB6 */
#define GPIO_BANK_USART1_RE_RX GPIOB /* PB7 */
/* I2C1 GPIO */
#define GPIO_I2C1_SMBAI GPIO5 /* PB5 */
#define GPIO_I2C1_SCL GPIO6 /* PB6 */
#define GPIO_I2C1_SDA GPIO7 /* PB7 */
#define GPIO_I2C1_RE_SMBAI GPIO5 /* PB5 */
#define GPIO_I2C1_RE_SCL GPIO8 /* PB8 */
#define GPIO_I2C1_RE_SDA GPIO9 /* PB9 */
/* I2C1 BANK */
#define GPIO_BANK_I2C1_SMBAI GPIOB /* PB5 */
#define GPIO_BANK_I2C1_SCL GPIOB /* PB6 */
#define GPIO_BANK_I2C1_SDA GPIOB /* PB7 */
#define GPIO_BANK_I2C1_RE_SMBAI GPIOB /* PB5 */
#define GPIO_BANK_I2C1_RE_SCL GPIOB /* PB8 */
#define GPIO_BANK_I2C1_RE_SDA GPIOB /* PB9 */
/* I2C2 GPIO */
#define GPIO_I2C2_SCL GPIO10 /* PB10 */
#define GPIO_I2C2_SDA GPIO11 /* PB11 */
#define GPIO_I2C2_SMBAI GPIO12 /* PB12 */
/* I2C2 BANK */
#define GPIO_BANK_I2C2_SCL GPIOB /* PB10 */
#define GPIO_BANK_I2C2_SDA GPIOB /* PB11 */
#define GPIO_BANK_I2C2_SMBAI GPIOB /* PB12 */
/* SPI1 GPIO */
#define GPIO_SPI1_NSS GPIO4 /* PA4 */
#define GPIO_SPI1_SCK GPIO5 /* PA5 */
#define GPIO_SPI1_MISO GPIO6 /* PA6 */
#define GPIO_SPI1_MOSI GPIO7 /* PA7 */
#define GPIO_SPI1_RE_NSS GPIO15 /* PA15 */
#define GPIO_SPI1_RE_SCK GPIO3 /* PB3 */
#define GPIO_SPI1_RE_MISO GPIO4 /* PB4 */
#define GPIO_SPI1_RE_MOSI GPIO5 /* PB5 */
/* SPI1 BANK */
#define GPIO_BANK_SPI1_NSS GPIOA /* PA4 */
#define GPIO_BANK_SPI1_SCK GPIOA /* PA5 */
#define GPIO_BANK_SPI1_MISO GPIOA /* PA6 */
#define GPIO_BANK_SPI1_MOSI GPIOA /* PA7 */
#define GPIO_BANK_SPI1_RE_NSS GPIOA /* PA15 */
#define GPIO_BANK_SPI1_RE_SCK GPIOB /* PB3 */
#define GPIO_BANK_SPI1_RE_MISO GPIOB /* PB4 */
#define GPIO_BANK_SPI1_RE_MOSI GPIOB /* PB5 */
/* SPI2 GPIO */
#define GPIO_SPI2_NSS GPIO12 /* PB12 */
#define GPIO_SPI2_SCK GPIO13 /* PB13 */
#define GPIO_SPI2_MISO GPIO14 /* PB14 */
#define GPIO_SPI2_MOSI GPIO15 /* PB15 */
/* SPI2 BANK */
#define GPIO_BANK_SPI2_NSS GPIOB /* PB12 */
#define GPIO_BANK_SPI2_SCK GPIOB /* PB13 */
#define GPIO_BANK_SPI2_MISO GPIOB /* PB14 */
#define GPIO_BANK_SPI2_MOSI GPIOB /* PB15 */
/* SPI3 GPIO */
#define GPIO_SPI3_NSS GPIO15 /* PA15 */
#define GPIO_SPI3_SCK GPIO3 /* PB3 */
#define GPIO_SPI3_MISO GPIO4 /* PB4 */
#define GPIO_SPI3_MOSI GPIO5 /* PB5 */
#define GPIO_SPI3_RE_NSS GPIO4 /* PA4 */
#define GPIO_SPI3_RE_SCK GPIO10 /* PC10 */
#define GPIO_SPI3_RE_MISO GPIO11 /* PC11 */
#define GPIO_SPI3_RE_MOSI GPIO12 /* PC12 */
/* SPI3 BANK */
#define GPIO_BANK_SPI3_NSS GPIOA /* PA15 */
#define GPIO_BANK_SPI3_SCK GPIOB /* PB3 */
#define GPIO_BANK_SPI3_MISO GPIOB /* PB4 */
#define GPIO_BANK_SPI3_MOSI GPIOB /* PB5 */
#define GPIO_BANK_SPI3_RE_NSS GPIOA /* PA4 */
#define GPIO_BANK_SPI3_RE_SCK GPIOC /* PC10 */
#define GPIO_BANK_SPI3_RE_MISO GPIOC /* PC11 */
#define GPIO_BANK_SPI3_RE_MOSI GPIOC /* PC12 */
/* ETH GPIO */
#define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */
#define GPIO_ETH_RXD0 GPIO4 /* PC4 */
#define GPIO_ETH_RXD1 GPIO5 /* PC5 */
#define GPIO_ETH_RXD2 GPIO0 /* PB0 */
#define GPIO_ETH_RXD3 GPIO1 /* PB1 */
#define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */
#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */
#define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */
#define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */
#define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */
/* ETH BANK */
#define GPIO_BANK_ETH_RX_DV_CRS_DV GPIOA /* PA7 */
#define GPIO_BANK_ETH_RXD0 GPIOC /* PC4 */
#define GPIO_BANK_ETH_RXD1 GPIOC /* PC5 */
#define GPIO_BANK_ETH_RXD2 GPIOB /* PB0 */
#define GPIO_BANK_ETH_RXD3 GPIOB /* PB1 */
#define GPIO_BANK_ETH_RE_RX_DV_CRS_DV GPIOD /* PD8 */
#define GPIO_BANK_ETH_RE_RXD0 GPIOD /* PD9 */
#define GPIO_BANK_ETH_RE_RXD1 GPIOD /* PD10 */
#define GPIO_BANK_ETH_RE_RXD2 GPIOD /* PD11 */
#define GPIO_BANK_ETH_RE_RXD3 GPIOD /* PD12 */
/* --- GPIO registers ------------------------------------------------------ */
/* Port configuration register low (GPIOx_CRL) */
#define GPIO_CRL(port) MMIO32(port + 0x00)
#define GPIOA_CRL GPIO_CRL(GPIOA)
#define GPIOB_CRL GPIO_CRL(GPIOB)
#define GPIOC_CRL GPIO_CRL(GPIOC)
#define GPIOD_CRL GPIO_CRL(GPIOD)
#define GPIOE_CRL GPIO_CRL(GPIOE)
#define GPIOF_CRL GPIO_CRL(GPIOF)
#define GPIOG_CRL GPIO_CRL(GPIOG)
/* Port configuration register low (GPIOx_CRH) */
#define GPIO_CRH(port) MMIO32(port + 0x04)
#define GPIOA_CRH GPIO_CRH(GPIOA)
#define GPIOB_CRH GPIO_CRH(GPIOB)
#define GPIOC_CRH GPIO_CRH(GPIOC)
#define GPIOD_CRH GPIO_CRH(GPIOD)
#define GPIOE_CRH GPIO_CRH(GPIOE)
#define GPIOF_CRH GPIO_CRH(GPIOF)
#define GPIOG_CRH GPIO_CRH(GPIOG)
/* Port input data register (GPIOx_IDR) */
#define GPIO_IDR(port) MMIO32(port + 0x08)
#define GPIOA_IDR GPIO_IDR(GPIOA)
#define GPIOB_IDR GPIO_IDR(GPIOB)
#define GPIOC_IDR GPIO_IDR(GPIOC)
#define GPIOD_IDR GPIO_IDR(GPIOD)
#define GPIOE_IDR GPIO_IDR(GPIOE)
#define GPIOF_IDR GPIO_IDR(GPIOF)
#define GPIOG_IDR GPIO_IDR(GPIOG)
/* Port output data register (GPIOx_ODR) */
#define GPIO_ODR(port) MMIO32(port + 0x0c)
#define GPIOA_ODR GPIO_ODR(GPIOA)
#define GPIOB_ODR GPIO_ODR(GPIOB)
#define GPIOC_ODR GPIO_ODR(GPIOC)
#define GPIOD_ODR GPIO_ODR(GPIOD)
#define GPIOE_ODR GPIO_ODR(GPIOE)
#define GPIOF_ODR GPIO_ODR(GPIOF)
#define GPIOG_ODR GPIO_ODR(GPIOG)
/* Port bit set/reset register (GPIOx_BSRR) */
#define GPIO_BSRR(port) MMIO32(port + 0x10)
#define GPIOA_BSRR GPIO_BSRR(GPIOA)
#define GPIOB_BSRR GPIO_BSRR(GPIOB)
#define GPIOC_BSRR GPIO_BSRR(GPIOC)
#define GPIOD_BSRR GPIO_BSRR(GPIOD)
#define GPIOE_BSRR GPIO_BSRR(GPIOE)
#define GPIOF_BSRR GPIO_BSRR(GPIOF)
#define GPIOG_BSRR GPIO_BSRR(GPIOG)
/* Port bit reset register (GPIOx_BRR) */
#define GPIO_BRR(port) MMIO16(port + 0x14)
#define GPIOA_BRR GPIO_BRR(GPIOA)
#define GPIOB_BRR GPIO_BRR(GPIOB)
#define GPIOC_BRR GPIO_BRR(GPIOC)
#define GPIOD_BRR GPIO_BRR(GPIOD)
#define GPIOE_BRR GPIO_BRR(GPIOE)
#define GPIOF_BRR GPIO_BRR(GPIOF)
#define GPIOG_BRR GPIO_BRR(GPIOG)
/* Port configuration lock register (GPIOx_LCKR) */
#define GPIO_LCKR(port) MMIO32(port + 0x18)
#define GPIOA_LCKR GPIO_LCKR(GPIOA)
#define GPIOB_LCKR GPIO_LCKR(GPIOB)
#define GPIOC_LCKR GPIO_LCKR(GPIOC)
#define GPIOD_LCKR GPIO_LCKR(GPIOD)
#define GPIOE_LCKR GPIO_LCKR(GPIOE)
#define GPIOF_LCKR GPIO_LCKR(GPIOF)
#define GPIOG_LCKR GPIO_LCKR(GPIOG)
/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
/** @defgroup gpio_cnf GPIO Pin Configuration
@ingroup gpio_defines
If mode specifies input, configuration can be
@li Analog input
@li Floating input
@li Pull up/down input
If mode specifies output, configuration can be
@li Digital push-pull
@li Digital open drain
@li Alternate function push-pull or analog output
@li Alternate function open drain or analog output
@{*/
/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
/** Analog Input */
#define GPIO_CNF_INPUT_ANALOG 0x00
/** Digital Input Floating */
#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */
/** Digital Input Pull Up and Down */
#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02
/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
/** Digital Output Pushpull */
#define GPIO_CNF_OUTPUT_PUSHPULL 0x00
/** Digital Output Open Drain */
#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01
/** Alternate Function Output Pushpull */
#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02
/** Alternate Function Output Open Drain */
#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03
/**@}*/
/* Pin mode (MODE[1:0]) values */
/** @defgroup gpio_mode GPIO Pin Mode
@ingroup gpio_defines
@li Input (default after reset)
@li Output mode at 10 MHz maximum speed
@li Output mode at 2 MHz maximum speed
@li Output mode at 50 MHz maximum speed
@{*/
#define GPIO_MODE_INPUT 0x00 /* Default */
#define GPIO_MODE_OUTPUT_10_MHZ 0x01
#define GPIO_MODE_OUTPUT_2_MHZ 0x02
#define GPIO_MODE_OUTPUT_50_MHZ 0x03
/**@}*/
/* --- GPIO_IDR values ----------------------------------------------------- */
/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
/* --- GPIO_ODR values ----------------------------------------------------- */
/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
/* --- GPIO_BSRR values ---------------------------------------------------- */
/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
/* --- GPIO_BRR values ----------------------------------------------------- */
/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */
/* --- AFIO registers ------------------------------------------------------ */
/* Event control register (AFIO_EVCR) */
#define AFIO_EVCR MMIO32(AFIO_BASE + 0x00)
/* AF remap and debug I/O configuration register (AFIO_MAPR) */
#define AFIO_MAPR MMIO32(AFIO_BASE + 0x04)
/* External interrupt configuration register [0..3] (AFIO_EXTICR[1..4])*/
#define AFIO_EXTICR(i) MMIO32(AFIO_BASE + 0x08 + (i)*4)
#define AFIO_EXTICR1 AFIO_EXTICR(0)
#define AFIO_EXTICR2 AFIO_EXTICR(1)
#define AFIO_EXTICR3 AFIO_EXTICR(2)
#define AFIO_EXTICR4 AFIO_EXTICR(3)
/* AF remap and debug I/O configuration register (AFIO_MAPR) */
#define AFIO_MAPR2 MMIO32(AFIO_BASE + 0x1C)
/* --- AFIO_EVCR values ---------------------------------------------------- */
/* EVOE: Event output enable */
#define AFIO_EVCR_EVOE (1 << 7)
/* PORT[2:0]: Port selection */
/** @defgroup afio_evcr_port EVENTOUT Port selection
@ingroup gpio_defines
@{*/
#define AFIO_EVCR_PORT_PA (0x0 << 4)
#define AFIO_EVCR_PORT_PB (0x1 << 4)
#define AFIO_EVCR_PORT_PC (0x2 << 4)
#define AFIO_EVCR_PORT_PD (0x3 << 4)
#define AFIO_EVCR_PORT_PE (0x4 << 4)
/**@}*/
/* PIN[3:0]: Pin selection */
/** @defgroup afio_evcr_pin EVENTOUT Pin selection
@ingroup gpio_defines
@{*/
#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
#define AFIO_EVCR_PIN_Px1 (0x1 << 0)
#define AFIO_EVCR_PIN_Px2 (0x2 << 0)
#define AFIO_EVCR_PIN_Px3 (0x3 << 0)
#define AFIO_EVCR_PIN_Px4 (0x4 << 0)
#define AFIO_EVCR_PIN_Px5 (0x5 << 0)
#define AFIO_EVCR_PIN_Px6 (0x6 << 0)
#define AFIO_EVCR_PIN_Px7 (0x7 << 0)
#define AFIO_EVCR_PIN_Px8 (0x8 << 0)
#define AFIO_EVCR_PIN_Px9 (0x9 << 0)
#define AFIO_EVCR_PIN_Px10 (0xA << 0)
#define AFIO_EVCR_PIN_Px11 (0xB << 0)
#define AFIO_EVCR_PIN_Px12 (0xC << 0)
#define AFIO_EVCR_PIN_Px13 (0xD << 0)
#define AFIO_EVCR_PIN_Px14 (0xE << 0)
#define AFIO_EVCR_PIN_Px15 (0xF << 0)
/**@}*/
/* --- AFIO_MAPR values ---------------------------------------------------- */
/* 31 reserved */
/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity
Line Devices only
@ingroup gpio_defines
@{*/
/* PTP_PPS_REMAP: */
/** Ethernet PTP PPS remapping (only connectivity line devices) */
#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
/* TIM2ITR1_IREMAP: */
/** TIM2 internal trigger 1 remapping (only connectivity line devices) */
#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
/* SPI3_REMAP: */
/** SPI3/I2S3 remapping (only connectivity line devices) */
#define AFIO_MAPR_SPI3_REMAP (1 << 28)
/* MII_REMAP: */
/** MII or RMII selection (only connectivity line devices) */
#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
/* CAN2_REMAP: */
/** CAN2 I/O remapping (only connectivity line devices) */
#define AFIO_MAPR_CAN2_REMAP (1 << 22)
/* ETH_REMAP: */
/** Ethernet MAC I/O remapping (only connectivity line devices) */
#define AFIO_MAPR_ETH_REMAP (1 << 21)
/**@}*/
/* 27 reserved */
/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
/** @defgroup afio_swj_disable Serial Wire JTAG disables
@ingroup gpio_defines
@{*/
#define AFIO_MAPR_SWJ_MASK (0x7 << 24)
/** Full Serial Wire JTAG capability */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
/** Full Serial Wire JTAG capability without JNTRST */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
/** JTAG-DP disabled with SW-DP enabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
/** JTAG-DP disabled and SW-DP disabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24)
/**@}*/
/** @defgroup afio_remap Alternate Function Remap Controls
@ingroup gpio_defines
@{*/
/* ADC2_ETRGREG_REMAP: */
/**
* ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-density devices)
*/
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
/* ADC2_ETRGINJ_REMAP: */
/**
* ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-density devices)
*/
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
/* ADC1_ETRGREG_REMAP: */
/**
* ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-density devices)
*/
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
/* ADC1_ETRGINJ_REMAP: */
/**
* ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-density devices)
*/
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
/* TIM5CH4_IREMAP: */
/** TIM5 channel 4 internal remap */
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
/* PD01_REMAP: */
/** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_MAPR_PD01_REMAP (1 << 15)
/* TIM4_REMAP: */
/** TIM4 remapping */
#define AFIO_MAPR_TIM4_REMAP (1 << 12)
/* USART2_REMAP[1:0]: */
/** USART2 remapping */
#define AFIO_MAPR_USART2_REMAP (1 << 3)
/* USART1_REMAP[1:0]: */
/** USART1 remapping */
#define AFIO_MAPR_USART1_REMAP (1 << 2)
/* I2C1_REMAP[1:0]: */
/** I2C1 remapping */
#define AFIO_MAPR_I2C1_REMAP (1 << 1)
/* SPI1_REMAP[1:0]: */
/** SPI1 remapping */
#define AFIO_MAPR_SPI1_REMAP (1 << 0)
/**@}*/
/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1
@ingroup gpio_defines
@{*/
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
/**@}*/
/* TIM3_REMAP[1:0]: TIM3 remapping */
/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3
@ingroup gpio_defines
@{*/
#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10)
#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10)
/**@}*/
/* TIM2_REMAP[1:0]: TIM2 remapping */
/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2
@ingroup gpio_defines
@{*/
#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8)
#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8)
/**@}*/
/* TIM1_REMAP[1:0]: TIM1 remapping */
/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1
@ingroup gpio_defines
@{*/
#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6)
#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6)
/**@}*/
/* USART3_REMAP[1:0]: USART3 remapping */
/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3
@ingroup gpio_defines
@{*/
#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4)
#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4)
/**@}*/
/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set
@ingroup gpio_defines
@{*/
/* FSMC_NADV_DISCONNECT: */
/** The NADV is disconnected from its allocated pin */
#define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10)
/* TIM14_REMAP: */
/** TIM14 remapping */
#define AFIO_MAPR2_TIM14_REMAP (1 << 9)
/* TIM13_REMAP: */
/** TIM13 remapping */
#define AFIO_MAPR2_TIM13_REMAP (1 << 8)
/* TIM11_REMAP: */
/** TIM11 remapping */
#define AFIO_MAPR2_TIM11_REMAP (1 << 7)
/* TIM10_REMAP: */
/** TIM10 remapping */
#define AFIO_MAPR2_TIM10_REMAP (1 << 6)
/* TIM9_REMAP: */
/** TIM9 remapping */
#define AFIO_MAPR2_TIM9_REMAP (1 << 5)
/**@}*/
/* --- AFIO_EXTICR1 values ------------------------------------------------- */
/* --- AFIO_EXTICR2 values ------------------------------------------------- */
/* --- AFIO_EXTICR3 values ------------------------------------------------- */
/* --- AFIO_EXTICR4 values ------------------------------------------------- */
/** @defgroup afio_exti Alternate Function EXTI pin number
@ingroup gpio_defines
@{*/
#define AFIO_EXTI0 0
#define AFIO_EXTI1 1
#define AFIO_EXTI2 2
#define AFIO_EXTI3 3
#define AFIO_EXTI4 4
#define AFIO_EXTI5 5
#define AFIO_EXTI6 6
#define AFIO_EXTI7 7
#define AFIO_EXTI8 8
#define AFIO_EXTI9 9
#define AFIO_EXTI10 10
#define AFIO_EXTI11 11
#define AFIO_EXTI12 12
#define AFIO_EXTI13 13
#define AFIO_EXTI14 14
#define AFIO_EXTI15 15
/**@}*/
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf,
uint16_t gpios);
void gpio_set_eventout(uint8_t evoutport, uint8_t evoutpin);
void gpio_primary_remap(uint32_t swjenable, uint32_t maps);
void gpio_secondary_remap(uint32_t maps);
END_DECLS
#endif
/**@}*/

38
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/f1/i2c.h Normal file
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@@ -0,0 +1,38 @@
/** @defgroup i2c_defines I2C Defines
@brief <b>Defined Constants and Types for the STM32F1xx I2C </b>
@ingroup STM32F1xx_defines
@version 1.0.0
@date 12 October 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_I2C_H
#define LIBOPENCM3_I2C_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/i2c_common_all.h>
#endif

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includeguard: LIBOPENCM3_STM32_F1_NVIC_H
partname_humanreadable: STM32 F1 series
partname_doxygen: STM32F1
irqs:
- wwdg
- pvd
- tamper
- rtc
- flash
- rcc
- exti0
- exti1
- exti2
- exti3
- exti4
- dma1_channel1
- dma1_channel2
- dma1_channel3
- dma1_channel4
- dma1_channel5
- dma1_channel6
- dma1_channel7
- adc1_2
- usb_hp_can_tx
- usb_lp_can_rx0
- can_rx1
- can_sce
- exti9_5
- tim1_brk
- tim1_up
- tim1_trg_com
- tim1_cc
- tim2
- tim3
- tim4
- i2c1_ev
- i2c1_er
- i2c2_ev
- i2c2_er
- spi1
- spi2
- usart1
- usart2
- usart3
- exti15_10
- rtc_alarm
- usb_wakeup
- tim8_brk
- tim8_up
- tim8_trg_com
- tim8_cc
- adc3
- fsmc
- sdio
- tim5
- spi3
- uart4
- uart5
- tim6
- tim7
- dma2_channel1
- dma2_channel2
- dma2_channel3
- dma2_channel4_5
- dma2_channel5
- eth
- eth_wkup
- can2_tx
- can2_rx0
- can2_rx1
- can2_sce
- otg_fs

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/** @defgroup iwdg_defines IWDG Defines
@brief <b>Defined Constants and Types for the STM32F1xx Independent Watchdog
Timer</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_IWDG_H
#define LIBOPENCM3_IWDG_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/iwdg_common_all.h>
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_MEMORYMAP_H
#define LIBOPENCM3_MEMORYMAP_H
#include <libopencm3/cm3/memorymap.h>
/* --- STM32 specific peripheral definitions ------------------------------- */
/* Memory map for all buses */
#define FLASH_BASE ((uint32_t)0x08000000)
#define PERIPH_BASE ((uint32_t)0x40000000)
#define INFO_BASE ((uint32_t)0x1ffff000)
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)
/* Register boundary addresses */
/* APB1 */
#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)
#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)
#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800)
#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00)
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00)
#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */
#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00)
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */
/* APB2 */
#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000)
#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400)
#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800)
#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00)
#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000)
#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400)
#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800)
#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00)
#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000)
#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)
#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800)
#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00)
#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)
#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00)
/* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 4FFF): Reserved */
#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00)
#define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000)
#define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400)
/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */
/* AHB */
#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000)
/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */
#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000)
#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400)
/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */
#define RCC_BASE (PERIPH_BASE_AHB + 0x09000)
/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000)
#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000)
/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */
#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */
#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000)
/* PPIB */
#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
/* FSMC */
#define FSMC_BASE (PERIPH_BASE + 0x60000000)
/* Device Electronic Signature */
#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0)
#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8)
#endif

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/** @defgroup pwr_defines PWR Defines
@brief <b>Defined Constants and Types for the STM32F1xx PWR Control</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@date 5 December 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_PWR_H
#define LIBOPENCM3_PWR_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/pwr_common_all.h>
#endif

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/** @defgroup STM32F1xx_rcc_defines RCC Defines
@brief <b>libopencm3 STM32F1xx Reset and Clock Control</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009
Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009
Uwe Hermann <uwe@hermann-uwe.de>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_RCC_H
#define LIBOPENCM3_RCC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */
/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */
/* --- RCC registers ------------------------------------------------------- */
#define RCC_CR MMIO32(RCC_BASE + 0x00)
#define RCC_CFGR MMIO32(RCC_BASE + 0x04)
#define RCC_CIR MMIO32(RCC_BASE + 0x08)
#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c)
#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10)
#define RCC_AHBENR MMIO32(RCC_BASE + 0x14)
#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18)
#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c)
#define RCC_BDCR MMIO32(RCC_BASE + 0x20)
#define RCC_CSR MMIO32(RCC_BASE + 0x24)
#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /*(**)*/
#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /*(**)*/
/* --- RCC_CR values ------------------------------------------------------- */
#define RCC_CR_PLL3RDY (1 << 29) /* (**) */
#define RCC_CR_PLL3ON (1 << 28) /* (**) */
#define RCC_CR_PLL2RDY (1 << 27) /* (**) */
#define RCC_CR_PLL2ON (1 << 26) /* (**) */
#define RCC_CR_PLLRDY (1 << 25)
#define RCC_CR_PLLON (1 << 24)
#define RCC_CR_CSSON (1 << 19)
#define RCC_CR_HSEBYP (1 << 18)
#define RCC_CR_HSERDY (1 << 17)
#define RCC_CR_HSEON (1 << 16)
/* HSICAL: [15:8] */
/* HSITRIM: [7:3] */
#define RCC_CR_HSIRDY (1 << 1)
#define RCC_CR_HSION (1 << 0)
/* --- RCC_CFGR values ----------------------------------------------------- */
/* MCO: Microcontroller clock output */
/** @defgroup rcc_cfgr_co RCC_CFGR Microcontroller Clock Output Source
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_MCO_NOCLK 0x0
#define RCC_CFGR_MCO_SYSCLK 0x4
#define RCC_CFGR_MCO_HSICLK 0x5
#define RCC_CFGR_MCO_HSECLK 0x6
#define RCC_CFGR_MCO_PLLCLK_DIV2 0x7
#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */
#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */
#define RCC_CFGR_MCO_XT1 0xa /* (**) */
#define RCC_CFGR_MCO_PLL3 0xb /* (**) */
/**@}*/
/* USBPRE: USB prescaler (RCC_CFGR[22]) */
/** @defgroup rcc_cfgr_usbpre RCC_CFGR USB prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0
#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1
/**@}*/
/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1
/* PLLMUL: PLL multiplication factor */
/** @defgroup rcc_cfgr_pmf RCC_CFGR PLL Multiplication Factor
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn.
line */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */
/* #define PLLMUL_PLL_CLK_MUL16 0xf */ /* (XX) */ /* Errata? 17? */
/**@}*/
/* TODO: conn. line differs. */
/* PLLXTPRE: HSE divider for PLL entry */
/** @defgroup rcc_cfgr_hsepre RCC_CFGR HSE Divider for PLL
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0
#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1
/**@}*/
/* PLLSRC: PLL entry clock source */
/** @defgroup rcc_cfgr_pcs RCC_CFGR PLL Clock Source
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0
#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */
/**@}*/
/* ADCPRE: ADC prescaler */
/****************************************************************************/
/** @defgroup rcc_cfgr_adcpre RCC ADC clock prescaler enable values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
/**@}*/
/* PPRE2: APB high-speed prescaler (APB2) */
/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
/**@}*/
/* PPRE1: APB low-speed prescaler (APB1) */
/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
/**@}*/
/* HPRE: AHB prescaler */
/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
/**@}*/
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0
#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1
#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2
/* SW: System clock switch */
/** @defgroup rcc_cfgr_scs RCC_CFGR System Clock Selection
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0
#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1
#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2
/**@}*/
/* --- RCC_CIR values ------------------------------------------------------ */
/* Clock security system interrupt clear bit */
#define RCC_CIR_CSSC (1 << 23)
/* OSC ready interrupt clear bits */
#define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */
#define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */
#define RCC_CIR_PLLRDYC (1 << 20)
#define RCC_CIR_HSERDYC (1 << 19)
#define RCC_CIR_HSIRDYC (1 << 18)
#define RCC_CIR_LSERDYC (1 << 17)
#define RCC_CIR_LSIRDYC (1 << 16)
/* OSC ready interrupt enable bits */
#define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */
#define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */
#define RCC_CIR_PLLRDYIE (1 << 12)
#define RCC_CIR_HSERDYIE (1 << 11)
#define RCC_CIR_HSIRDYIE (1 << 10)
#define RCC_CIR_LSERDYIE (1 << 9)
#define RCC_CIR_LSIRDYIE (1 << 8)
/* Clock security system interrupt flag bit */
#define RCC_CIR_CSSF (1 << 7)
/* OSC ready interrupt flag bits */
#define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */
#define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */
#define RCC_CIR_PLLRDYF (1 << 4)
#define RCC_CIR_HSERDYF (1 << 3)
#define RCC_CIR_HSIRDYF (1 << 2)
#define RCC_CIR_LSERDYF (1 << 1)
#define RCC_CIR_LSIRDYF (1 << 0)
/* --- RCC_APB2RSTR values ------------------------------------------------- */
/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */
#define RCC_APB2RSTR_USART1RST (1 << 14)
#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */
#define RCC_APB2RSTR_SPI1RST (1 << 12)
#define RCC_APB2RSTR_TIM1RST (1 << 11)
#define RCC_APB2RSTR_ADC2RST (1 << 10)
#define RCC_APB2RSTR_ADC1RST (1 << 9)
#define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */
#define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */
#define RCC_APB2RSTR_IOPERST (1 << 6)
#define RCC_APB2RSTR_IOPDRST (1 << 5)
#define RCC_APB2RSTR_IOPCRST (1 << 4)
#define RCC_APB2RSTR_IOPBRST (1 << 3)
#define RCC_APB2RSTR_IOPARST (1 << 2)
#define RCC_APB2RSTR_AFIORST (1 << 0)
/**@}*/
/* --- RCC_APB1RSTR values ------------------------------------------------- */
/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_APB1RSTR_DACRST (1 << 29)
#define RCC_APB1RSTR_PWRRST (1 << 28)
#define RCC_APB1RSTR_BKPRST (1 << 27)
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */
#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for
CAN1RST */
#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */
#define RCC_APB1RSTR_I2C2RST (1 << 22)
#define RCC_APB1RSTR_I2C1RST (1 << 21)
#define RCC_APB1RSTR_UART5RST (1 << 20)
#define RCC_APB1RSTR_UART4RST (1 << 19)
#define RCC_APB1RSTR_USART3RST (1 << 18)
#define RCC_APB1RSTR_USART2RST (1 << 17)
#define RCC_APB1RSTR_SPI3RST (1 << 15)
#define RCC_APB1RSTR_SPI2RST (1 << 14)
#define RCC_APB1RSTR_WWDGRST (1 << 11)
#define RCC_APB1RSTR_TIM7RST (1 << 5)
#define RCC_APB1RSTR_TIM6RST (1 << 4)
#define RCC_APB1RSTR_TIM5RST (1 << 3)
#define RCC_APB1RSTR_TIM4RST (1 << 2)
#define RCC_APB1RSTR_TIM3RST (1 << 1)
#define RCC_APB1RSTR_TIM2RST (1 << 0)
/**@}*/
/* --- RCC_AHBENR values --------------------------------------------------- */
/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_AHBENR_ETHMACENRX (1 << 16)
#define RCC_AHBENR_ETHMACENTX (1 << 15)
#define RCC_AHBENR_ETHMACEN (1 << 14)
#define RCC_AHBENR_OTGFSEN (1 << 12)
#define RCC_AHBENR_SDIOEN (1 << 10)
#define RCC_AHBENR_FSMCEN (1 << 8)
#define RCC_AHBENR_CRCEN (1 << 6)
#define RCC_AHBENR_FLITFEN (1 << 4)
#define RCC_AHBENR_SRAMEN (1 << 2)
#define RCC_AHBENR_DMA2EN (1 << 1)
#define RCC_AHBENR_DMA1EN (1 << 0)
/**@}*/
/* --- RCC_APB2ENR values -------------------------------------------------- */
/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */
#define RCC_APB2ENR_USART1EN (1 << 14)
#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */
#define RCC_APB2ENR_SPI1EN (1 << 12)
#define RCC_APB2ENR_TIM1EN (1 << 11)
#define RCC_APB2ENR_ADC2EN (1 << 10)
#define RCC_APB2ENR_ADC1EN (1 << 9)
#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */
#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */
#define RCC_APB2ENR_IOPEEN (1 << 6)
#define RCC_APB2ENR_IOPDEN (1 << 5)
#define RCC_APB2ENR_IOPCEN (1 << 4)
#define RCC_APB2ENR_IOPBEN (1 << 3)
#define RCC_APB2ENR_IOPAEN (1 << 2)
#define RCC_APB2ENR_AFIOEN (1 << 0)
/**@}*/
/* --- RCC_APB1ENR values -------------------------------------------------- */
/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_APB1ENR_DACEN (1 << 29)
#define RCC_APB1ENR_PWREN (1 << 28)
#define RCC_APB1ENR_BKPEN (1 << 27)
#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */
#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */
#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for
CAN1EN */
#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */
#define RCC_APB1ENR_I2C2EN (1 << 22)
#define RCC_APB1ENR_I2C1EN (1 << 21)
#define RCC_APB1ENR_UART5EN (1 << 20)
#define RCC_APB1ENR_UART4EN (1 << 19)
#define RCC_APB1ENR_USART3EN (1 << 18)
#define RCC_APB1ENR_USART2EN (1 << 17)
#define RCC_APB1ENR_SPI3EN (1 << 15)
#define RCC_APB1ENR_SPI2EN (1 << 14)
#define RCC_APB1ENR_WWDGEN (1 << 11)
#define RCC_APB1ENR_TIM7EN (1 << 5)
#define RCC_APB1ENR_TIM6EN (1 << 4)
#define RCC_APB1ENR_TIM5EN (1 << 3)
#define RCC_APB1ENR_TIM4EN (1 << 2)
#define RCC_APB1ENR_TIM3EN (1 << 1)
#define RCC_APB1ENR_TIM2EN (1 << 0)
/**@}*/
/* --- RCC_BDCR values ----------------------------------------------------- */
#define RCC_BDCR_BDRST (1 << 16)
#define RCC_BDCR_RTCEN (1 << 15)
/* RCC_BDCR[9:8]: RTCSEL */
#define RCC_BDCR_LSEBYP (1 << 2)
#define RCC_BDCR_LSERDY (1 << 1)
#define RCC_BDCR_LSEON (1 << 0)
/* --- RCC_CSR values ------------------------------------------------------ */
#define RCC_CSR_LPWRRSTF (1 << 31)
#define RCC_CSR_WWDGRSTF (1 << 30)
#define RCC_CSR_IWDGRSTF (1 << 29)
#define RCC_CSR_SFTRSTF (1 << 28)
#define RCC_CSR_PORRSTF (1 << 27)
#define RCC_CSR_PINRSTF (1 << 26)
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
/* --- RCC_AHBRSTR values -------------------------------------------------- */
/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_AHBRSTR_ETHMACRST (1 << 14)
#define RCC_AHBRSTR_OTGFSRST (1 << 12)
/**@}*/
/* --- RCC_CFGR2 values ---------------------------------------------------- */
/* I2S3SRC: I2S3 clock source */
#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0
#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1
/* I2S2SRC: I2S2 clock source */
#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0
#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1
/* PREDIV1SRC: PREDIV1 entry clock source */
#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0
#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1
#define RCC_CFGR2_PLL2MUL (1 << 0)
#define RCC_CFGR2_PREDIV2 (1 << 0)
#define RCC_CFGR2_PREDIV1 (1 << 0)
/* PLL3MUL: PLL3 multiplication factor */
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe
#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf
/* PLL2MUL: PLL2 multiplication factor */
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe
#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf
/* PREDIV: PREDIV division factor */
#define RCC_CFGR2_PREDIV_NODIV 0x0
#define RCC_CFGR2_PREDIV_DIV2 0x1
#define RCC_CFGR2_PREDIV_DIV3 0x2
#define RCC_CFGR2_PREDIV_DIV4 0x3
#define RCC_CFGR2_PREDIV_DIV5 0x4
#define RCC_CFGR2_PREDIV_DIV6 0x5
#define RCC_CFGR2_PREDIV_DIV7 0x6
#define RCC_CFGR2_PREDIV_DIV8 0x7
#define RCC_CFGR2_PREDIV_DIV9 0x8
#define RCC_CFGR2_PREDIV_DIV10 0x9
#define RCC_CFGR2_PREDIV_DIV11 0xa
#define RCC_CFGR2_PREDIV_DIV12 0xb
#define RCC_CFGR2_PREDIV_DIV13 0xc
#define RCC_CFGR2_PREDIV_DIV14 0xd
#define RCC_CFGR2_PREDIV_DIV15 0xe
#define RCC_CFGR2_PREDIV_DIV16 0xf
/* PREDIV2: PREDIV2 division factor */
#define RCC_CFGR2_PREDIV2_NODIV 0x0
#define RCC_CFGR2_PREDIV2_DIV2 0x1
#define RCC_CFGR2_PREDIV2_DIV3 0x2
#define RCC_CFGR2_PREDIV2_DIV4 0x3
#define RCC_CFGR2_PREDIV2_DIV5 0x4
#define RCC_CFGR2_PREDIV2_DIV6 0x5
#define RCC_CFGR2_PREDIV2_DIV7 0x6
#define RCC_CFGR2_PREDIV2_DIV8 0x7
#define RCC_CFGR2_PREDIV2_DIV9 0x8
#define RCC_CFGR2_PREDIV2_DIV10 0x9
#define RCC_CFGR2_PREDIV2_DIV11 0xa
#define RCC_CFGR2_PREDIV2_DIV12 0xb
#define RCC_CFGR2_PREDIV2_DIV13 0xc
#define RCC_CFGR2_PREDIV2_DIV14 0xd
#define RCC_CFGR2_PREDIV2_DIV15 0xe
#define RCC_CFGR2_PREDIV2_DIV16 0xf
/* --- Variable definitions ------------------------------------------------ */
extern uint32_t rcc_ppre1_frequency;
extern uint32_t rcc_ppre2_frequency;
/* --- Function prototypes ------------------------------------------------- */
typedef enum {
PLL, PLL2, PLL3, HSE, HSI, LSE, LSI
} osc_t;
BEGIN_DECLS
void rcc_osc_ready_int_clear(osc_t osc);
void rcc_osc_ready_int_enable(osc_t osc);
void rcc_osc_ready_int_disable(osc_t osc);
int rcc_osc_ready_int_flag(osc_t osc);
void rcc_css_int_clear(void);
int rcc_css_int_flag(void);
void rcc_wait_for_osc_ready(osc_t osc);
void rcc_osc_on(osc_t osc);
void rcc_osc_off(osc_t osc);
void rcc_css_enable(void);
void rcc_css_disable(void);
void rcc_set_mco(uint32_t mcosrc);
void rcc_osc_bypass_enable(osc_t osc);
void rcc_osc_bypass_disable(osc_t osc);
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
void rcc_set_sysclk_source(uint32_t clk);
void rcc_set_pll_multiplication_factor(uint32_t mul);
void rcc_set_pll2_multiplication_factor(uint32_t mul);
void rcc_set_pll3_multiplication_factor(uint32_t mul);
void rcc_set_pll_source(uint32_t pllsrc);
void rcc_set_pllxtpre(uint32_t pllxtpre);
void rcc_set_adcpre(uint32_t adcpre);
void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_usbpre(uint32_t usbpre);
void rcc_set_prediv1(uint32_t prediv);
void rcc_set_prediv2(uint32_t prediv);
void rcc_set_prediv1_source(uint32_t rccsrc);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_in_hsi_out_64mhz(void);
void rcc_clock_setup_in_hsi_out_48mhz(void);
void rcc_clock_setup_in_hsi_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_12mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
void rcc_clock_setup_in_hse_25mhz_out_72mhz(void);
void rcc_backupdomain_reset(void);
END_DECLS
#endif
/**@}*/

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/** @defgroup rtc_defines RTC Defines
@brief <b>Defined Constants and Types for the STM32F1xx Real Time Clock</b>
@ingroup STM32F1xx_defines
@author @htmlonly &copy; @endhtmlonly 2010 Uwe Hermann <uwe@hermann-uwe.de>
@version 1.0.0
@date 4 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* The F1 RTC is a straight time stamp, a completely different peripheral to
* that found in the F2, F3, F4, L1 and F0.
*/
#ifndef LIBOPENCM3_RTC_H
#define LIBOPENCM3_RTC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/pwr.h>
#include <libopencm3/stm32/f1/rcc.h>
/* --- RTC registers ------------------------------------------------------- */
/* RTC control register high (RTC_CRH) */
#define RTC_CRH MMIO32(RTC_BASE + 0x00)
/* RTC control register low (RTC_CRL) */
#define RTC_CRL MMIO32(RTC_BASE + 0x04)
/* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */
#define RTC_PRLH MMIO32(RTC_BASE + 0x08)
#define RTC_PRLL MMIO32(RTC_BASE + 0x0c)
/* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */
#define RTC_DIVH MMIO32(RTC_BASE + 0x10)
#define RTC_DIVL MMIO32(RTC_BASE + 0x14)
/* RTC counter register (RTC_CNTH / RTC_CNTL) */
#define RTC_CNTH MMIO32(RTC_BASE + 0x18)
#define RTC_CNTL MMIO32(RTC_BASE + 0x1c)
/* RTC alarm register high (RTC_ALRH / RTC_ALRL) */
#define RTC_ALRH MMIO32(RTC_BASE + 0x20)
#define RTC_ALRL MMIO32(RTC_BASE + 0x24)
/* --- RTC_CRH values -------------------------------------------------------*/
/* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */
/* OWIE: Overflow interrupt enable */
#define RTC_CRH_OWIE (1 << 2)
/* ALRIE: Alarm interrupt enable */
#define RTC_CRH_ALRIE (1 << 1)
/* SECIE: Second interrupt enable */
#define RTC_CRH_SECIE (1 << 0)
/* --- RTC_CRL values -------------------------------------------------------*/
/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
/* RTOFF: RTC operation OFF */
#define RTC_CRL_RTOFF (1 << 5)
/* CNF: Configuration flag */
#define RTC_CRL_CNF (1 << 4)
/* RSF: Registers synchronized flag */
#define RTC_CRL_RSF (1 << 3)
/* OWF: Overflow flag */
#define RTC_CRL_OWF (1 << 2)
/* ALRF: Alarm flag */
#define RTC_CRL_ALRF (1 << 1)
/* SECF: Second flag */
#define RTC_CRL_SECF (1 << 0)
/* --- RTC_PRLH values ------------------------------------------------------*/
/* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */
/* TODO */
/* --- RTC_PRLL values ------------------------------------------------------*/
/* TODO */
/* --- RTC_DIVH values ------------------------------------------------------*/
/* Bits [15:4] are reserved. */
/* TODO */
/* --- RTC_DIVL values ------------------------------------------------------*/
/* TODO */
/* --- RTC_CNTH values ------------------------------------------------------*/
/* TODO */
/* --- RTC_CNTL values ------------------------------------------------------*/
/* TODO */
/* --- RTC_ALRH values ------------------------------------------------------*/
/* TODO */
/* --- RTC_ALRL values ------------------------------------------------------*/
/* TODO */
/* --- Function prototypes --------------------------------------------------*/
typedef enum {
RTC_SEC, RTC_ALR, RTC_OW,
} rtcflag_t;
BEGIN_DECLS
void rtc_awake_from_off(osc_t clock_source);
void rtc_enter_config_mode(void);
void rtc_exit_config_mode(void);
void rtc_set_alarm_time(uint32_t alarm_time);
void rtc_enable_alarm(void);
void rtc_disable_alarm(void);
void rtc_set_prescale_val(uint32_t prescale_val);
uint32_t rtc_get_counter_val(void);
uint32_t rtc_get_prescale_div_val(void);
uint32_t rtc_get_alarm_val(void);
void rtc_set_counter_val(uint32_t counter_val);
void rtc_interrupt_enable(rtcflag_t flag_val);
void rtc_interrupt_disable(rtcflag_t flag_val);
void rtc_clear_flag(rtcflag_t flag_val);
uint32_t rtc_check_flag(rtcflag_t flag_val);
void rtc_awake_from_standby(void);
void rtc_auto_awake(osc_t clock_source, uint32_t prescale_val);
END_DECLS
#endif

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/** @defgroup spi_defines SPI Defines
@brief <b>Defined Constants and Types for the STM32F1xx SPI</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@date 5 December 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_SPI_H
#define LIBOPENCM3_SPI_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/spi_common_f124.h>
#endif

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/** @defgroup timer_defines Timer Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx Timers</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@date 8 March 2013
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_TIMER_H
#define LIBOPENCM3_TIMER_H
#include <libopencm3/stm32/common/timer_common_all.h>
/** Input Capture input polarity */
enum tim_ic_pol {
TIM_IC_RISING,
TIM_IC_FALLING,
};
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void timer_ic_set_polarity(uint32_t timer,
enum tim_ic_id ic,
enum tim_ic_pol pol);
END_DECLS
#endif

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/** @defgroup usart_defines USART Defines
@brief <b>Defined Constants and Types for the STM32F1xx USART</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@date 5 December 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_USART_H
#define LIBOPENCM3_USART_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/usart_common_f124.h>
#endif

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/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F2xx CRC
Generator </b>
@ingroup STM32F2xx_defines
@version 1.0.0
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CRC_H
#define LIBOPENCM3_CRC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/crc_common_all.h>
#endif

38
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/** @defgroup crypto_defines CRYPTO Defines
*
* @brief <b>Defined Constants and Types for the STM32F2xx CRYP Controller</b>
*
* @ingroup STM32F2xx_defines
*
* @version 1.0.0
*
* @date 17 Jun 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CRYPTO_H
#define LIBOPENCM3_CRYPTO_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/common/crypto_common_f24.h>
#endif

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/** @defgroup dac_defines DAC Defines
@brief <b>Defined Constants and Types for the STM32F2xx DAC</b>
@ingroup STM32F2xx_defines
@version 1.0.0
@date 5 December 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_DAC_H
#define LIBOPENCM3_DAC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/dac_common_all.h>
#endif

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/** @defgroup dma_defines DMA Defines
@ingroup STM32F2xx_defines
@brief Defined Constants and Types for the STM32F2xx DMA Controller
@version 1.0.0
@date 18 October 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/dma_common_f24.h>
#endif

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/** @mainpage libopencm3 STM32F2
@version 1.0.0
@date 14 September 2012
API documentation for ST Microelectronics STM32F2 Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F2xx STM32F2xx
Libraries for ST Microelectronics STM32F2xx series.
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F2xx_defines STM32F2xx Defines
@brief Defined Constants and Types for the STM32F2xx series
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Piotr Esden-Tempski <piotr@esden.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_EXTI_H
#define LIBOPENCM3_EXTI_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/exti_common_l1f24.h>
#endif

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/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_FLASH_H
#define LIBOPENCM3_FLASH_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/flash_common_f24.h>
#endif

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/** @defgroup gpio_defines GPIO Defines
@brief <b>Defined Constants and Types for the STM32F2xx General Purpose I/O</b>
@ingroup STM32F2xx_defines
@version 1.0.0
@date 1 July 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/gpio_common_f24.h>
#endif

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/** @defgroup hash_defines HASH Defines
@ingroup STM32F2xx_defines
@brief Defined Constants and Types for the STM32F2xx HASH Controller
@version 1.0.0
@date 31 May 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_HASH_H
#define LIBOPENCM3_HASH_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/hash_common_f24.h>
#endif

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/** @defgroup i2c_defines I2C Defines
@brief <b>Defined Constants and Types for the STM32F2xx I2C </b>
@ingroup STM32F2xx_defines
@version 1.0.0
@date 12 October 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_I2C_H
#define LIBOPENCM3_I2C_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/i2c_common_f24.h>
#endif

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includeguard: LIBOPENCM3_STM32_F2_NVIC_H
partname_humanreadable: STM32 F2 series
partname_doxygen: STM32F2
irqs:
- nvic_wwdg
- pvd
- tamp_stamp
- rtc_wkup
- flash
- rcc
- exti0
- exti1
- exti2
- exti3
- exti4
- dma1_stream0
- dma1_stream1
- dma1_stream2
- dma1_stream3
- dma1_stream4
- dma1_stream5
- dma1_stream6
- adc
- can1_tx
- can1_rx0
- can1_rx1
- can1_sce
- exti9_5
- tim1_brk_tim9
- tim1_up_tim10
- tim1_trg_com_tim11
- tim1_cc
- tim2
- tim3
- tim4
- i2c1_ev
- i2c1_er
- i2c2_ev
- i2c2_er
- spi1
- spi2
- usart1
- usart2
- usart3
- exti15_10
- rtc_alarm
- usb_fs_wkup
- tim8_brk_tim12
- tim8_up_tim13
- tim8_trg_com_tim14
- tim8_cc
- dma1_stream7
- fsmc
- sdio
- tim5
- spi3
- uart4
- uart5
- tim6_dac
- tim7
- dma2_stream0
- dma2_stream1
- dma2_stream2
- dma2_stream3
- dma2_stream4
- eth
- eth_wkup
- can2_tx
- can2_rx0
- can2_rx1
- can2_sce
- otg_fs
- dma2_stream5
- dma2_stream6
- dma2_stream7
- usart6
- i2c3_ev
- i2c3_er
- otg_hs_ep1_out
- otg_hs_ep1_in
- otg_hs_wkup
- otg_hs
- dcmi
- cryp
- hash_rng

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/** @defgroup iwdg_defines IWDG Defines
@brief <b>Defined Constants and Types for the STM32F2xx Independent Watchdog
Timer</b>
@ingroup STM32F2xx_defines
@version 1.0.0
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_IWDG_H
#define LIBOPENCM3_IWDG_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/iwdg_common_all.h>
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_MEMORYMAP_H
#define LIBOPENCM3_MEMORYMAP_H
#include <libopencm3/cm3/memorymap.h>
/* --- STM32F20x specific peripheral definitions --------------------------- */
/* Memory map for all busses */
#define PERIPH_BASE 0x40000000
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
#define PERIPH_BASE_AHB2 0x50000000
#define PERIPH_BASE_AHB3 0x60000000
/* Register boundary addresses */
/* APB1 */
#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)
#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)
#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */
#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800)
#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00)
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)
/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */
#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */
/* APB2 */
#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000)
#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)
/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */
#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000)
#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)
#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000)
#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000)
/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00)
/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
/* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */
#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)
#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)
#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)
#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)
#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)
/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */
/* AHB1 */
#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)
#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)
#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)
#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)
#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)
#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)
#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)
#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)
#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)
/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */
#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */
#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)
#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)
/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */
#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)
#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)
/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */
#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)
/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */
#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)
/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */
/* AHB2 */
#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000)
/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */
#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)
/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */
#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)
#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)
#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)
/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */
/* AHB3 */
#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000)
/* PPIB */
#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
#endif

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/** @defgroup pwr_defines PWR Defines
@brief <b>Defined Constants and Types for the STM32F2xx PWR Control</b>
@ingroup STM32F2xx_defines
@version 1.0.0
@date 4 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_PWR_F2_H
#define LIBOPENCM3_PWR_F2_H
#include <libopencm3/stm32/pwr.h>
/*
* This file extends the common STM32 version with definitions only
* applicable to the STM32F2 series of devices.
*/
/* --- PWR_CR values ------------------------------------------------------- */
/* Bits [31:10]: Reserved, always read as 0. */
/* FPDS: Flash power down in stop mode */
#define PWR_CR_FPDS (1 << 9)
/* --- PWR_CSR values ------------------------------------------------------ */
/* Bits [31:10]: Reserved, always read as 0. */
/* BRE: Backup regulator enable */
#define PWR_CSR_BRE (1 << 9)
/* Bits [7:4]: Reserved, always read as 0. */
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_RCC_H
#define LIBOPENCM3_RCC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- RCC registers ------------------------------------------------------- */
#define RCC_CR MMIO32(RCC_BASE + 0x00)
#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04)
#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
#define RCC_CIR MMIO32(RCC_BASE + 0x0c)
#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10)
#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14)
#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18)
/* RCC_BASE + 0x1c Reserved */
#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20)
#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24)
/* RCC_BASE + 0x28 Reserved */
/* RCC_BASE + 0x2c Reserved */
#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30)
#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34)
#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38)
/* RCC_BASE + 0x3c Reserved */
#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40)
#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44)
/* RCC_BASE + 0x48 Reserved */
/* RCC_BASE + 0x4c Reserved */
#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50)
#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54)
#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58)
/* RCC_BASE + 0x5c Reserved */
#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60)
#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64)
/* RCC_BASE + 0x68 Reserved */
/* RCC_BASE + 0x6c Reserved */
#define RCC_BDCR MMIO32(RCC_BASE + 0x70)
#define RCC_CSR MMIO32(RCC_BASE + 0x74)
/* RCC_BASE + 0x78 Reserved */
/* RCC_BASE + 0x7c Reserved */
#define RCC_SSCGR MMIO32(RCC_BASE + 0x80)
#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84)
/* --- RCC_CR values ------------------------------------------------------- */
#define RCC_CR_PLLI2SRDY (1 << 27)
#define RCC_CR_PLLI2SON (1 << 26)
#define RCC_CR_PLLRDY (1 << 25)
#define RCC_CR_PLLON (1 << 24)
#define RCC_CR_CSSON (1 << 19)
#define RCC_CR_HSEBYP (1 << 18)
#define RCC_CR_HSERDY (1 << 17)
#define RCC_CR_HSEON (1 << 16)
/* HSICAL: [15:8] */
/* HSITRIM: [7:3] */
#define RCC_CR_HSIRDY (1 << 1)
#define RCC_CR_HSION (1 << 0)
/* --- RCC_PLLCFGR values -------------------------------------------------- */
/* PLLQ: [27:24] */
#define RCC_PLLCFGR_PLLQ_SHIFT 24
#define RCC_PLLCFGR_PLLSRC (1 << 22)
/* PLLP: [17:16] */
#define RCC_PLLCFGR_PLLP_SHIFT 16
/* PLLN: [14:6] */
#define RCC_PLLCFGR_PLLN_SHIFT 6
/* PLLM: [5:0] */
#define RCC_PLLCFGR_PLLM_SHIFT 0
/* --- RCC_CFGR values ----------------------------------------------------- */
/* MCO2: Microcontroller clock output 2 */
#define RCC_CFGR_MCO2_SHIFT 30
#define RCC_CFGR_MCO2_SYSCLK 0x0
#define RCC_CFGR_MCO2_PLLI2S 0x1
#define RCC_CFGR_MCO2_HSE 0x2
#define RCC_CFGR_MCO2_PLL 0x3
/* MCO1/2PRE: MCO Prescalers */
#define RCC_CFGR_MCO2PRE_SHIFT 27
#define RCC_CFGR_MCO1PRE_SHIFT 24
#define RCC_CFGR_MCOPRE_DIV_NONE 0x0
#define RCC_CFGR_MCOPRE_DIV_2 0x4
#define RCC_CFGR_MCOPRE_DIV_3 0x5
#define RCC_CFGR_MCOPRE_DIV_4 0x6
#define RCC_CFGR_MCOPRE_DIV_5 0x7
/* I2SSRC: I2S clock selection */
#define RCC_CFGR_I2SSRC (1 << 23)
/* MCO1: Microcontroller clock output 1 */
#define RCC_CFGR_MCO1_SHIFT 21
#define RCC_CFGR_MCO1_HSI 0x0
#define RCC_CFGR_MCO1_LSE 0x1
#define RCC_CFGR_MCO1_HSE 0x2
#define RCC_CFGR_MCO1_PLL 0x3
/* RTCPRE: HSE division factor for RTC clock */
#define RCC_CFGR_RTCPRE_SHIFT 21
/* PPRE1/2: APB high-speed prescalers */
#define RCC_CFGR_PPRE2_SHIFT 13
#define RCC_CFGR_PPRE1_SHIFT 10
#define RCC_CFGR_PPRE_DIV_NONE 0x0
#define RCC_CFGR_PPRE_DIV_2 0x4
#define RCC_CFGR_PPRE_DIV_4 0x5
#define RCC_CFGR_PPRE_DIV_8 0x6
#define RCC_CFGR_PPRE_DIV_16 0x7
/* HPRE: AHB high-speed prescaler */
#define RCC_CFGR_HPRE_SHIFT 4
#define RCC_CFGR_HPRE_DIV_NONE 0x0
#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0)
#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1)
#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2)
#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3)
#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4)
#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5)
#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6)
#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7)
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SHIFT 2
#define RCC_CFGR_SWS_HSI 0x0
#define RCC_CFGR_SWS_HSE 0x1
#define RCC_CFGR_SWS_PLL 0x2
/* SW: System clock switch */
#define RCC_CFGR_SW_SHIFT 0
#define RCC_CFGR_SW_HSI 0x0
#define RCC_CFGR_SW_HSE 0x1
#define RCC_CFGR_SW_PLL 0x2
/* --- RCC_CIR values ------------------------------------------------------ */
/* Clock security system interrupt clear bit */
#define RCC_CIR_CSSC (1 << 23)
/* OSC ready interrupt clear bits */
#define RCC_CIR_PLLI2SRDYC (1 << 21)
#define RCC_CIR_PLLRDYC (1 << 20)
#define RCC_CIR_HSERDYC (1 << 19)
#define RCC_CIR_HSIRDYC (1 << 18)
#define RCC_CIR_LSERDYC (1 << 17)
#define RCC_CIR_LSIRDYC (1 << 16)
/* OSC ready interrupt enable bits */
#define RCC_CIR_PLLI2SRDYIE (1 << 13)
#define RCC_CIR_PLLRDYIE (1 << 12)
#define RCC_CIR_HSERDYIE (1 << 11)
#define RCC_CIR_HSIRDYIE (1 << 10)
#define RCC_CIR_LSERDYIE (1 << 9)
#define RCC_CIR_LSIRDYIE (1 << 8)
/* Clock security system interrupt flag bit */
#define RCC_CIR_CSSF (1 << 7)
/* OSC ready interrupt flag bits */
#define RCC_CIR_PLLI2SRDYF (1 << 5)
#define RCC_CIR_PLLRDYF (1 << 4)
#define RCC_CIR_HSERDYF (1 << 3)
#define RCC_CIR_HSIRDYF (1 << 2)
#define RCC_CIR_LSERDYF (1 << 1)
#define RCC_CIR_LSIRDYF (1 << 0)
/* --- RCC_AHB1RSTR values ------------------------------------------------- */
#define RCC_AHB1RSTR_OTGHSRST (1 << 29)
#define RCC_AHB1RSTR_ETHMACRST (1 << 25)
#define RCC_AHB1RSTR_DMA2RST (1 << 22)
#define RCC_AHB1RSTR_DMA1RST (1 << 21)
#define RCC_AHB1RSTR_CRCRST (1 << 12)
#define RCC_AHB1RSTR_IOPIRST (1 << 8)
#define RCC_AHB1RSTR_IOPHRST (1 << 7)
#define RCC_AHB1RSTR_IOPGRST (1 << 6)
#define RCC_AHB1RSTR_IOPFRST (1 << 5)
#define RCC_AHB1RSTR_IOPERST (1 << 4)
#define RCC_AHB1RSTR_IOPDRST (1 << 3)
#define RCC_AHB1RSTR_IOPCRST (1 << 2)
#define RCC_AHB1RSTR_IOPBRST (1 << 1)
#define RCC_AHB1RSTR_IOPARST (1 << 0)
/* --- RCC_AHB2RSTR values ------------------------------------------------- */
#define RCC_AHB2RSTR_OTGFSRST (1 << 7)
#define RCC_AHB2RSTR_RNGRST (1 << 6)
#define RCC_AHB2RSTR_HASHRST (1 << 5)
#define RCC_AHB2RSTR_CRYPRST (1 << 4)
#define RCC_AHB2RSTR_DCMIRST (1 << 0)
/* --- RCC_AHB3RSTR values ------------------------------------------------- */
#define RCC_AHB3RSTR_FSMCRST (1 << 0)
/* --- RCC_APB1RSTR values ------------------------------------------------- */
#define RCC_APB1RSTR_DACRST (1 << 29)
#define RCC_APB1RSTR_PWRRST (1 << 28)
#define RCC_APB1RSTR_CAN2RST (1 << 26)
#define RCC_APB1RSTR_CAN1RST (1 << 25)
#define RCC_APB1RSTR_I2C3RST (1 << 23)
#define RCC_APB1RSTR_I2C2RST (1 << 22)
#define RCC_APB1RSTR_I2C1RST (1 << 21)
#define RCC_APB1RSTR_UART5RST (1 << 20)
#define RCC_APB1RSTR_UART4RST (1 << 19)
#define RCC_APB1RSTR_USART3RST (1 << 18)
#define RCC_APB1RSTR_USART2RST (1 << 17)
#define RCC_APB1RSTR_SPI3RST (1 << 15)
#define RCC_APB1RSTR_SPI2RST (1 << 14)
#define RCC_APB1RSTR_WWDGRST (1 << 11)
#define RCC_APB1RSTR_TIM14RST (1 << 8)
#define RCC_APB1RSTR_TIM13RST (1 << 7)
#define RCC_APB1RSTR_TIM12RST (1 << 6)
#define RCC_APB1RSTR_TIM7RST (1 << 5)
#define RCC_APB1RSTR_TIM6RST (1 << 4)
#define RCC_APB1RSTR_TIM5RST (1 << 3)
#define RCC_APB1RSTR_TIM4RST (1 << 2)
#define RCC_APB1RSTR_TIM3RST (1 << 1)
#define RCC_APB1RSTR_TIM2RST (1 << 0)
/* --- RCC_APB2RSTR values ------------------------------------------------- */
#define RCC_APB2RSTR_TIM11RST (1 << 18)
#define RCC_APB2RSTR_TIM10RST (1 << 17)
#define RCC_APB2RSTR_TIM9RST (1 << 16)
#define RCC_APB2RSTR_SYSCFGRST (1 << 14)
#define RCC_APB2RSTR_SPI1RST (1 << 12)
#define RCC_APB2RSTR_SDIORST (1 << 11)
#define RCC_APB2RSTR_ADCRST (1 << 8)
#define RCC_APB2RSTR_USART6RST (1 << 5)
#define RCC_APB2RSTR_USART1RST (1 << 4)
#define RCC_APB2RSTR_TIM8RST (1 << 1)
#define RCC_APB2RSTR_TIM1RST (1 << 0)
/* --- RCC_AHB1ENR values ------------------------------------------------- */
#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30)
#define RCC_AHB1ENR_OTGHSEN (1 << 29)
#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28)
#define RCC_AHB1ENR_ETHMACRXEN (1 << 27)
#define RCC_AHB1ENR_ETHMACTXEN (1 << 26)
#define RCC_AHB1ENR_ETHMACEN (1 << 25)
#define RCC_AHB1ENR_DMA2EN (1 << 22)
#define RCC_AHB1ENR_DMA1EN (1 << 21)
#define RCC_AHB1ENR_BKPSRAMEN (1 << 18)
#define RCC_AHB1ENR_CRCEN (1 << 12)
#define RCC_AHB1ENR_IOPIEN (1 << 8)
#define RCC_AHB1ENR_IOPHEN (1 << 7)
#define RCC_AHB1ENR_IOPGEN (1 << 6)
#define RCC_AHB1ENR_IOPFEN (1 << 5)
#define RCC_AHB1ENR_IOPEEN (1 << 4)
#define RCC_AHB1ENR_IOPDEN (1 << 3)
#define RCC_AHB1ENR_IOPCEN (1 << 2)
#define RCC_AHB1ENR_IOPBEN (1 << 1)
#define RCC_AHB1ENR_IOPAEN (1 << 0)
/* --- RCC_AHB2ENR values ------------------------------------------------- */
#define RCC_AHB2ENR_OTGFSEN (1 << 7)
#define RCC_AHB2ENR_RNGEN (1 << 6)
#define RCC_AHB2ENR_HASHEN (1 << 5)
#define RCC_AHB2ENR_CRYPEN (1 << 4)
#define RCC_AHB2ENR_DCMIEN (1 << 0)
/* --- RCC_AHB3ENR values ------------------------------------------------- */
#define RCC_AHB3ENR_FSMCEN (1 << 0)
/* --- RCC_APB1ENR values ------------------------------------------------- */
#define RCC_APB1ENR_DACEN (1 << 29)
#define RCC_APB1ENR_PWREN (1 << 28)
#define RCC_APB1ENR_CAN2EN (1 << 26)
#define RCC_APB1ENR_CAN1EN (1 << 25)
#define RCC_APB1ENR_I2C3EN (1 << 23)
#define RCC_APB1ENR_I2C2EN (1 << 22)
#define RCC_APB1ENR_I2C1EN (1 << 21)
#define RCC_APB1ENR_UART5EN (1 << 20)
#define RCC_APB1ENR_UART4EN (1 << 19)
#define RCC_APB1ENR_USART3EN (1 << 18)
#define RCC_APB1ENR_USART2EN (1 << 17)
#define RCC_APB1ENR_SPI3EN (1 << 15)
#define RCC_APB1ENR_SPI2EN (1 << 14)
#define RCC_APB1ENR_WWDGEN (1 << 11)
#define RCC_APB1ENR_TIM14EN (1 << 8)
#define RCC_APB1ENR_TIM13EN (1 << 7)
#define RCC_APB1ENR_TIM12EN (1 << 6)
#define RCC_APB1ENR_TIM7EN (1 << 5)
#define RCC_APB1ENR_TIM6EN (1 << 4)
#define RCC_APB1ENR_TIM5EN (1 << 3)
#define RCC_APB1ENR_TIM4EN (1 << 2)
#define RCC_APB1ENR_TIM3EN (1 << 1)
#define RCC_APB1ENR_TIM2EN (1 << 0)
/* --- RCC_APB2ENR values ------------------------------------------------- */
#define RCC_APB2ENR_TIM11EN (1 << 18)
#define RCC_APB2ENR_TIM10EN (1 << 17)
#define RCC_APB2ENR_TIM9EN (1 << 16)
#define RCC_APB2ENR_SYSCFGEN (1 << 14)
#define RCC_APB2ENR_SPI1EN (1 << 12)
#define RCC_APB2ENR_SDIOEN (1 << 11)
#define RCC_APB2ENR_ADC3EN (1 << 10)
#define RCC_APB2ENR_ADC2EN (1 << 9)
#define RCC_APB2ENR_ADC1EN (1 << 8)
#define RCC_APB2ENR_USART6EN (1 << 5)
#define RCC_APB2ENR_USART1EN (1 << 4)
#define RCC_APB2ENR_TIM8EN (1 << 1)
#define RCC_APB2ENR_TIM1EN (1 << 0)
/* --- RCC_AHB1LPENR values ------------------------------------------------- */
#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30)
#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29)
#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28)
#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27)
#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26)
#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25)
#define RCC_AHB1LPENR_DMA2LPEN (1 << 22)
#define RCC_AHB1LPENR_DMA1LPEN (1 << 21)
#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18)
#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17)
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16)
#define RCC_AHB1LPENR_FLITFLPEN (1 << 15)
#define RCC_AHB1LPENR_CRCLPEN (1 << 12)
#define RCC_AHB1LPENR_IOPILPEN (1 << 8)
#define RCC_AHB1LPENR_IOPHLPEN (1 << 7)
#define RCC_AHB1LPENR_IOPGLPEN (1 << 6)
#define RCC_AHB1LPENR_IOPFLPEN (1 << 5)
#define RCC_AHB1LPENR_IOPELPEN (1 << 4)
#define RCC_AHB1LPENR_IOPDLPEN (1 << 3)
#define RCC_AHB1LPENR_IOPCLPEN (1 << 2)
#define RCC_AHB1LPENR_IOPBLPEN (1 << 1)
#define RCC_AHB1LPENR_IOPALPEN (1 << 0)
/* --- RCC_AHB2LPENR values ------------------------------------------------- */
#define RCC_AHB2LPENR_OTGFSLPEN (1 << 7)
#define RCC_AHB2LPENR_RNGLPEN (1 << 6)
#define RCC_AHB2LPENR_HASHLPEN (1 << 5)
#define RCC_AHB2LPENR_CRYPLPEN (1 << 4)
#define RCC_AHB2LPENR_DCMILPEN (1 << 0)
/* --- RCC_AHB3LPENR values ------------------------------------------------- */
#define RCC_AHB3LPENR_FSMCLPEN (1 << 0)
/* --- RCC_APB1LPENR values ------------------------------------------------- */
#define RCC_APB1LPENR_DACLPEN (1 << 29)
#define RCC_APB1LPENR_PWRLPEN (1 << 28)
#define RCC_APB1LPENR_CAN2LPEN (1 << 26)
#define RCC_APB1LPENR_CAN1LPEN (1 << 25)
#define RCC_APB1LPENR_I2C3LPEN (1 << 23)
#define RCC_APB1LPENR_I2C2LPEN (1 << 22)
#define RCC_APB1LPENR_I2C1LPEN (1 << 21)
#define RCC_APB1LPENR_UART5LPEN (1 << 20)
#define RCC_APB1LPENR_UART4LPEN (1 << 19)
#define RCC_APB1LPENR_USART3LPEN (1 << 18)
#define RCC_APB1LPENR_USART2LPEN (1 << 17)
#define RCC_APB1LPENR_SPI3LPEN (1 << 15)
#define RCC_APB1LPENR_SPI2LPEN (1 << 14)
#define RCC_APB1LPENR_WWDGLPEN (1 << 11)
#define RCC_APB1LPENR_TIM14LPEN (1 << 8)
#define RCC_APB1LPENR_TIM13LPEN (1 << 7)
#define RCC_APB1LPENR_TIM12LPEN (1 << 6)
#define RCC_APB1LPENR_TIM7LPEN (1 << 5)
#define RCC_APB1LPENR_TIM6LPEN (1 << 4)
#define RCC_APB1LPENR_TIM5LPEN (1 << 3)
#define RCC_APB1LPENR_TIM4LPEN (1 << 2)
#define RCC_APB1LPENR_TIM3LPEN (1 << 1)
#define RCC_APB1LPENR_TIM2LPEN (1 << 0)
/* --- RCC_APB2LPENR values ------------------------------------------------- */
#define RCC_APB2LPENR_TIM11LPEN (1 << 18)
#define RCC_APB2LPENR_TIM10LPEN (1 << 17)
#define RCC_APB2LPENR_TIM9LPEN (1 << 16)
#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14)
#define RCC_APB2LPENR_SPI1LPEN (1 << 12)
#define RCC_APB2LPENR_SDIOLPEN (1 << 11)
#define RCC_APB2LPENR_ADC3LPEN (1 << 10)
#define RCC_APB2LPENR_ADC2LPEN (1 << 9)
#define RCC_APB2LPENR_ADC1LPEN (1 << 8)
#define RCC_APB2LPENR_USART6LPEN (1 << 5)
#define RCC_APB2LPENR_USART1LPEN (1 << 4)
#define RCC_APB2LPENR_TIM8LPEN (1 << 1)
#define RCC_APB2LPENR_TIM1LPEN (1 << 0)
/* --- RCC_BDCR values ----------------------------------------------------- */
#define RCC_BDCR_BDRST (1 << 16)
#define RCC_BDCR_RTCEN (1 << 15)
/* RCC_BDCR[9:8]: RTCSEL */
#define RCC_BDCR_LSEBYP (1 << 2)
#define RCC_BDCR_LSERDY (1 << 1)
#define RCC_BDCR_LSEON (1 << 0)
/* --- RCC_CSR values ------------------------------------------------------ */
#define RCC_CSR_LPWRRSTF (1 << 31)
#define RCC_CSR_WWDGRSTF (1 << 30)
#define RCC_CSR_IWDGRSTF (1 << 29)
#define RCC_CSR_SFTRSTF (1 << 28)
#define RCC_CSR_PORRSTF (1 << 27)
#define RCC_CSR_PINRSTF (1 << 26)
#define RCC_CSR_BORRSTF (1 << 25)
#define RCC_CSR_RMVF (1 << 24)
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
/* --- RCC_SSCGR values ---------------------------------------------------- */
/* PLL spread spectrum clock generation documented in Datasheet. */
#define RCC_SSCGR_SSCGEN (1 << 31)
#define RCC_SSCGR_SPREADSEL (1 << 30)
/* RCC_SSCGR[27:16]: INCSTEP */
#define RCC_SSCGR_INCSTEP_SHIFT 16
/* RCC_SSCGR[15:0]: MODPER */
#define RCC_SSCGR_MODPER_SHIFT 15
/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */
/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */
#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28
/* RCC_PLLI2SCFGR[14:6]: PLLI2SN */
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6
/* --- Variable definitions ------------------------------------------------ */
extern uint32_t rcc_ppre1_frequency;
extern uint32_t rcc_ppre2_frequency;
/* --- Function prototypes ------------------------------------------------- */
typedef enum {
CLOCK_3V3_120MHZ,
CLOCK_3V3_END
} clock_3v3_t;
typedef struct {
uint8_t pllm;
uint16_t plln;
uint8_t pllp;
uint8_t pllq;
uint32_t flash_config;
uint8_t hpre;
uint8_t ppre1;
uint8_t ppre2;
uint32_t apb1_frequency;
uint32_t apb2_frequency;
} clock_scale_t;
extern const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END];
typedef enum {
PLL, HSE, HSI, LSE, LSI
} osc_t;
BEGIN_DECLS
void rcc_osc_ready_int_clear(osc_t osc);
void rcc_osc_ready_int_enable(osc_t osc);
void rcc_osc_ready_int_disable(osc_t osc);
int rcc_osc_ready_int_flag(osc_t osc);
void rcc_css_int_clear(void);
int rcc_css_int_flag(void);
void rcc_wait_for_osc_ready(osc_t osc);
void rcc_wait_for_sysclk_status(osc_t osc);
void rcc_osc_on(osc_t osc);
void rcc_osc_off(osc_t osc);
void rcc_css_enable(void);
void rcc_css_disable(void);
void rcc_osc_bypass_enable(osc_t osc);
void rcc_osc_bypass_disable(osc_t osc);
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
void rcc_set_sysclk_source(uint32_t clk);
void rcc_set_pll_source(uint32_t pllsrc);
void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_rtcpre(uint32_t rtcpre);
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq);
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);
END_DECLS
#endif

24
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/f2/rng.h Normal file
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@@ -0,0 +1,24 @@
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_RNG_H
#define LIBOPENCM3_RNG_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/rng_common_f24.h>
#endif

37
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/f2/rtc.h Normal file
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/** @defgroup rtc_defines RTC Defines
@brief <b>Defined Constants and Types for the STM32F2xx RTC</b>
@ingroup STM32F2xx_defines
@version 1.0.0
@date 5 December 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_RTC_H
#define LIBOPENCM3_RTC_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/rtc_common_l1f024.h>
#endif

38
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/f2/spi.h Normal file
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/** @defgroup spi_defines SPI Defines
@brief <b>Defined Constants and Types for the STM32F2xx SPI</b>
@ingroup STM32F2xx_defines
@version 1.0.0
@date 5 December 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_SPI_H
#define LIBOPENCM3_SPI_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/spi_common_f24.h>
#endif

26
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/stm32/f2/syscfg.h Normal file
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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_SYSCFG_H
#define LIBOPENCM3_SYSCFG_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/syscfg_common_l1f234.h>
#endif

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