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This commit is contained in:
RocketGod
2022-09-22 09:26:57 -07:00
parent fee0ab05fd
commit 957ea3d712
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137
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/** @defgroup debugging Debugging
@brief Macros and functions to aid in debugging
@version 1.0.0
@date 25 September 2012
Two preprocessor defines control the behavior of assertion check macros in
this module. They allow the choice between generated code size and ease of
debugging.
If NDEBUG is defined, all assertion checks are disabled and macros do not
generate any code.
If CM3_ASSERT_VERBOSE is defined, information regarding the position of
assertion checks will be stored in the binary, allowing for more
informative error messages, but also significantly increased code size. As
default assertion checks do not use this information it is only useful if
the application linked with libopencm3 defines its own
cm3_assert_failed_verbose() implementation.
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Tomaz Solc <tomaz.solc@tablix.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_CM3_ASSERT_H
#define LIBOPENCM3_CM3_ASSERT_H
#include <libopencm3/cm3/common.h>
#define CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1))
#ifdef NDEBUG
# define cm3_assert(expr) (void)0
# define cm3_assert_not_reached() do { } while (1)
#else
# ifdef CM3_ASSERT_VERBOSE
# define cm3_assert(expr) do { \
if (CM3_LIKELY(expr)) { \
(void)0; \
} else { \
cm3_assert_failed_verbose( \
__FILE__, __LINE__, \
__func__, #expr); \
} \
} while (0)
# define cm3_assert_not_reached() \
cm3_assert_failed_verbose( \
__FILE__, __LINE__, \
__func__, 0)
# else
/** @brief Check if assertion is true.
*
* If NDEBUG macro is defined, this macro generates no code. Otherwise
* cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion
* is false.
*
* The purpose of this macro is to aid in debugging libopencm3 and
* applications using it. It can be used for example to check if function
* arguments are within expected ranges and stop execution in case an
* unexpected state is reached.
*
* @param expr expression to check */
# define cm3_assert(expr) do { \
if (CM3_LIKELY(expr)) { \
(void)0; \
} else { \
cm3_assert_failed(); \
} \
} while (0)
/** @brief Check if unreachable code is reached.
*
* If NDEBUG macro is defined, this macro generates code for an infinite loop.
* Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if
* the macro is ever reached.
*
* The purpose of this macro is to aid in debugging libopencm3 and
* applications using it. It can be used for example to stop execution if an
* unreachable portion of code is reached. */
# define cm3_assert_not_reached() cm3_assert_failed()
# endif
#endif
BEGIN_DECLS
/** @brief Called on a failed assertion.
*
* Halts execution in an infinite loop. This function never returns.
*
* Defined as a weak symbol, so applications can define their own
* implementation. Usually, a custom implementation of this function should
* report an error in some way (print a message to a debug console, display,
* LED, ...) and halt execution or reboot the device. */
void cm3_assert_failed(void) __attribute__((__noreturn__));
/** @brief Called on a failed assertion with verbose messages enabled.
*
* Halts execution in an infinite loop. This function never returns.
*
* Defined as a weak symbol, so applications can define their own
* implementation. Usually, a custom implementation of this function should
* report an error in some way (print a message to a debug console, display,
* LED, ...) and halt execution or reboot the device.
*
* @param file File name where the failed assertion occurred
* @param line Line number where the failed assertion occurred
* @param func Name of the function where the failed assertion occurred
* @param assert_expr Expression that evaluated to false (can be NULL) */
void cm3_assert_failed_verbose(const char *file, int line, const char *func,
const char *assert_expr) __attribute__((__noreturn__));
END_DECLS
#endif
/**@}*/

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_COMMON_H
#define LIBOPENCM3_CM3_COMMON_H
#include <stdint.h>
#include <stdbool.h>
/* This must be placed around external function declaration for C++
* support. */
#ifdef __cplusplus
# define BEGIN_DECLS extern "C" {
# define END_DECLS }
#else
# define BEGIN_DECLS
# define END_DECLS
#endif
/* Full-featured deprecation attribute with fallback for older compilers. */
#ifdef __GNUC__
# if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 4)
# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))
# else
# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated))
# endif
#else
# define LIBOPENCM3_DEPRECATED(x)
#endif
/* Generic memory-mapped I/O accessor functions */
#define MMIO8(addr) (*(volatile uint8_t *)(addr))
#define MMIO16(addr) (*(volatile uint16_t *)(addr))
#define MMIO32(addr) (*(volatile uint32_t *)(addr))
#define MMIO64(addr) (*(volatile uint64_t *)(addr))
/* Generic bit-band I/O accessor functions */
#define BBIO_SRAM(addr, bit) \
MMIO8(((addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)
#define BBIO_PERIPH(addr, bit) \
MMIO8(((addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)
/* Generic bit definition */
#define BIT0 (1<<0)
#define BIT1 (1<<1)
#define BIT2 (1<<2)
#define BIT3 (1<<3)
#define BIT4 (1<<4)
#define BIT5 (1<<5)
#define BIT6 (1<<6)
#define BIT7 (1<<7)
#define BIT8 (1<<8)
#define BIT9 (1<<9)
#define BIT10 (1<<10)
#define BIT11 (1<<11)
#define BIT12 (1<<12)
#define BIT13 (1<<13)
#define BIT14 (1<<14)
#define BIT15 (1<<15)
#define BIT16 (1<<16)
#define BIT17 (1<<17)
#define BIT18 (1<<18)
#define BIT19 (1<<19)
#define BIT20 (1<<20)
#define BIT21 (1<<21)
#define BIT22 (1<<22)
#define BIT23 (1<<23)
#define BIT24 (1<<24)
#define BIT25 (1<<25)
#define BIT26 (1<<26)
#define BIT27 (1<<27)
#define BIT28 (1<<28)
#define BIT29 (1<<29)
#define BIT30 (1<<30)
#define BIT31 (1<<31)
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Ben Gamari <bgamari@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CORTEX_H
#define LIBOPENCM3_CORTEX_H
static inline void cm_enable_interrupts(void)
{
__asm__("CPSIE I\n");
}
static inline void cm_disable_interrupts(void)
{
__asm__("CPSID I\n");
}
#endif

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/** @mainpage libopencm3 Core CM3
@version 1.0.0
@date 14 September 2012
API documentation for Cortex M3 core features.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup CM3_defines CM3 Defines
@brief Defined Constants and Types for Cortex M3 core features
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_FPB_H
#define LIBOPENCM3_CM3_FPB_H
/* Cortex-M3 Flash Patch and Breakpoint (FPB) unit */
/* Those defined only on ARMv7 and above */
#if !defined(__ARM_ARCH_7M__) || !defined(__ARM_ARCH_7EM__)
#error "Flash Patch and Breakpoint not available in CM0"
#endif
/* Note: We always use "FPB" as abbreviation, docs sometimes use only "FP". */
/* --- FPB registers ------------------------------------------------------- */
/* Flash Patch Control (FPB_CTRL) */
#define FPB_CTRL MMIO32(FPB_BASE + 0)
/* Flash Patch Remap (FPB_REMAP) */
#define FPB_REMAP MMIO32(FPB_BASE + 4)
/* Flash Patch Comparator (FPB_COMPx) */
#define FPB_COMP (&MMIO32(FPB_BASE + 8))
/* TODO: PID, CID */
/* --- FPB_CTRL values ----------------------------------------------------- */
/* Bits [31:15]: Reserved, read as zero, writes ignored */
#define FPB_CTRL_NUM_CODE2_MASK (0x7 << 12)
#define FPB_CTRL_NUM_LIT_MASK (0xf << 8)
#define FPB_CTRL_NUM_CODE1_MASK (0xf << 4)
/* Bits [3:2]: Reserved */
#define FPB_CTRL_KEY (1 << 1)
#define FPB_CTRL_ENABLE (1 << 0)
/* --- FPB_REMAP values ---------------------------------------------------- */
/* TODO */
/* --- FPB_COMPx values ---------------------------------------------------- */
#define FPB_COMP_REPLACE_REMAP (0x0 << 30)
#define FPB_COMP_REPLACE_BREAK_LOWER (0x1 << 30)
#define FPB_COMP_REPLACE_BREAK_UPPER (0x2 << 30)
#define FPB_COMP_REPLACE_BREAK_BOTH (0x3 << 30)
#define FPB_COMP_REPLACE_MASK (0x3 << 30)
/* Bit 29: Reserved */
/* TODO */
/* Bit 1: Reserved */
#define FPB_COMP_ENABLE (1 << 0)
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_ITM_H
#define LIBOPENCM3_CM3_ITM_H
/* Cortex-M3 Instrumentation Trace Macrocell (ITM) */
/* Those defined only on ARMv7 and above */
#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
#error "Instrumentation Trace Macrocell not available in CM0"
#endif
/* --- ITM registers ------------------------------------------------------- */
/* Stimulus Port x (ITM_STIM[x]) */
#define ITM_STIM (&MMIO32(ITM_BASE))
/* Trace Enable ports (ITM_TER[x]) */
#define ITM_TER (&MMIO32(ITM_BASE + 0xE00))
/* Trace Privilege (ITM_TPR) */
#define ITM_TPR MMIO32(ITM_BASE + 0xE40)
/* Trace Control (ITM_TCR) */
#define ITM_TCR MMIO32(ITM_BASE + 0xE80)
/* TODO: PID, CID */
/* --- ITM_STIM values ----------------------------------------------------- */
/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */
/* Bits 31:1 - RAZ */
#define ITM_STIM_FIFOREADY (1 << 0)
/* --- ITM_TER values ------------------------------------------------------ */
/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */
/* --- ITM_TPR values ------------------------------------------------------ */
/*
* Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7
* 0: User access allowed to stimulus ports
* 1: Privileged access only to stimulus ports
*/
/* --- ITM_TCR values ------------------------------------------------------ */
/* Bits 31:24 - Reserved */
#define ITM_TCR_BUSY (1 << 23)
#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16)
/* Bits 15:10 - Reserved */
#define ITM_TCR_TSPRESCALE_NONE (0 << 8)
#define ITM_TCR_TSPRESCALE_DIV4 (1 << 8)
#define ITM_TCR_TSPRESCALE_DIV16 (2 << 8)
#define ITM_TCR_TSPRESCALE_DIV64 (3 << 8)
#define ITM_TCR_TSPRESCALE_MASK (3 << 8)
/* Bits 7:5 - Reserved */
#define ITM_TCR_SWOENA (1 << 4)
#define ITM_TCR_TXENA (1 << 3)
#define ITM_TCR_SYNCENA (1 << 2)
#define ITM_TCR_TSENA (1 << 1)
#define ITM_TCR_ITMENA (1 << 0)
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_MEMORYMAP_H
#define LIBOPENCM3_CM3_MEMORYMAP_H
/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */
/* Private peripheral bus - Internal */
#define PPBI_BASE 0xE0000000
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* ITM: Instrumentation Trace Macrocell */
#define ITM_BASE (PPBI_BASE + 0x0000)
/* DWT: Data Watchpoint and Trace unit */
#define DWT_BASE (PPBI_BASE + 0x1000)
/* FPB: Flash Patch and Breakpoint unit */
#define FPB_BASE (PPBI_BASE + 0x2000)
#endif
/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
#define SCS_BASE (PPBI_BASE + 0xE000)
/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
#define TPIU_BASE (PPBI_BASE + 0x40000)
#endif
/* --- ITM: Instrumentation Trace Macrocell --- */
/* TODO */
/* --- DWT: Data Watchpoint and Trace unit --- */
/* TODO */
/* --- FPB: Flash Patch and Breakpoint unit --- */
/* TODO */
/* --- SCS: System Control Space --- */
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* ITR: Interrupt Type Register */
#define ITR_BASE (SCS_BASE + 0x0000)
#endif
/* SYS_TICK: System Timer */
#define SYS_TICK_BASE (SCS_BASE + 0x0010)
/* NVIC: Nested Vector Interrupt Controller */
#define NVIC_BASE (SCS_BASE + 0x0100)
/* SCB: System Control Block */
#define SCB_BASE (SCS_BASE + 0x0D00)
#ifdef CM0_PLUS
/* MPU: Memory protection unit */
#define MPU_BASE (SCS_BASE + 0x0D90)
#endif
/* Those defined only on CM0*/
#if defined(__ARM_ARCH_6M__)
/* DEBUG: Debug control and configuration */
#define DEBUG_BASE (SCS_BASE + 0x0DF0)
#endif
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* STE: Software Trigger Interrupt Register */
#define STIR_BASE (SCS_BASE + 0x0F00)
/* ID: ID space */
#define ID_BASE (SCS_BASE + 0x0FD0)
#endif
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM0_MPU_H
#define LIBOPENCM3_CM0_MPU_H
#ifndef CM0_PLUS
#error "mpu is supported only on CM0+ architecture"
#else
#include <libopencm3/cm0/memorymap.h>
#include <libopencm3/cm0/common.h>
/* --- SCB: Registers ------------------------------------------------------ */
#define MPU_TYPE MMIO32(MPU_BASE + 0x00)
#define MPU_CTRL MMIO32(MPU_BASE + 0x04)
#define MPU_RNR MMIO32(MPU_BASE + 0x08)
#define MPU_RBAR MMIO32(MPU_BASE + 0x0C)
#define MPU_RASR MMIO32(MPU_BASE + 0x10)
/* --- MPU values ---------------------------------------------------------- */
/* --- MPU_TYPE values ----------------------------------------------------- */
#define MPU_TYPE_IREGION_LSB 16
#define MPU_TYPE_IREGION (0xFF << MPU_TYPE_IREGION_LSB)
#define MPU_TYPE_DREGION_LSB 8
#define MPU_TYPE_DREGION (0xFF << MPU_TYPE_DREGION_LSB)
#define MPU_TYPE_SEPARATE (1<<0)
/* --- MPU_CTRL values ----------------------------------------------------- */
#define MPU_CTRL_PRIVDEFENA (1<<2)
#define MPU_CTRL_HFNMIENA (1<<1)
#define MPU_CTRL_ENABLE (1<<0)
/* --- MPU_RNR values ------------------------------------------------------ */
#define MPU_RNR_REGION_LSB 0
#define MPU_RNR_REGION (0xFF << MPU_RNR_REGION_LSB)
/* --- MPU_RBAR values ----------------------------------------------------- */
#define MPU_RBAR_ADDR_LSB 8
#define MPU_RBAR_ADDR (0x00FFFFFF << MPU_RBAR_REGION_LSB)
#define MPU_RBAR_VALID (1<<4)
#define MPU_RBAR_REGION_LSB 0
#define MPU_RBAR_REGION (0xF << MPU_RBAR_REGION_LSB)
/* --- MPU_RASR values ----------------------------------------------------- */
#define MPU_RASR_ATTRS_LSB 16
#define MPU_RASR_ATTRS (0xFFFF << MPU_RASR_ATTRS_LSB)
#define MPU_RASR_SRD_LSB 8
#define MPU_RASR_SRD (0xFF << MPU_RASR_SRD_LSB)
#define MPU_RASR_SIZE_LSB 1
#define MPU_RASR_SIZE (0x1F << MPU_RASR_SIZE_LSB)
#define MPU_RASR_ENABLE (1 << 0)
#define MPU_RASR_ATTR_XN (1 << 28)
#define MPU_RASR_ATTR_AP (7 << 24)
#define MPU_RASR_ATTR_AP_PNO_UNO (0 << 24)
#define MPU_RASR_ATTR_AP_PRW_UNO (1 << 24)
#define MPU_RASR_ATTR_AP_PRW_URO (2 << 24)
#define MPU_RASR_ATTR_AP_PRW_URW (3 << 24)
#define MPU_RASR_ATTR_AP_PRO_UNO (5 << 24)
#define MPU_RASR_ATTR_AP_PRO_URO (6 << 24)
#define MPU_RASR_ATTR_AP_PRO_URO (7 << 24)
#define MPU_RASR_ATTR_TEX (7 << 19)
#define MPU_RASR_ATTR_S (1 << 18)
#define MPU_RASR_ATTR_C (1 << 17)
#define MPU_RASR_ATTR_B (1 << 16)
#define MPU_RASR_ATTR_SCB (7 << 16)
#define MPU_RASR_ATTR_SCB_SH_STRONG (0 << 16)
#define MPU_RASR_ATTR_SCB_SH_DEVICE (1 << 16)
#define MPU_RASR_ATTR_SCB_NSH_WT (2 << 16)
#define MPU_RASR_ATTR_SCB_NSH_WB (3 << 16)
#define MPU_RASR_ATTR_SCB_SH_STRONG (4 << 16)
#define MPU_RASR_ATTR_SCB_SH_DEVICE (5 << 16)
#define MPU_RASR_ATTR_SCB_SH_WT (6 << 16)
#define MPU_RASR_ATTR_SCB_SH_WB (7 << 16)
/* --- MPU functions ------------------------------------------------------- */
BEGIN_DECLS
END_DECLS
#endif /* CM0_PLUS */
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_SCB_H
#define LIBOPENCM3_SCB_H
#include <libopencm3/cm3/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- SCB: Registers ------------------------------------------------------ */
/* CPUID: CPUID base register */
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
/* ICSR: Interrupt Control State Register */
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
/* VTOR: Vector Table Offset Register */
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
/* AIRCR: Application Interrupt and Reset Control Register */
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
/* SCR: System Control Register */
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
/* CCR: Configuration Control Register */
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
/* SHP: System Handler Priority Registers */
/* Note: 12 8bit registers */
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
#define SCB_SHPR1 MMIO32(SCB_BASE + 0x18)
#define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C)
#define SCB_SHPR3 MMIO32(SCB_BASE + 0x20)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* SHCSR: System Handler Control and State Register */
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
/* CFSR: Configurable Fault Status Registers */
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
/* HFSR: Hard Fault Status Register */
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
/* DFSR: Debug Fault Status Register */
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
/* MMFAR: Memory Manage Fault Address Register */
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
/* BFAR: Bus Fault Address Register */
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
/* AFSR: Auxiliary Fault Status Register */
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
/* ID_PFR0: Processor Feature Register 0 */
#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
/* ID_PFR1: Processor Feature Register 1 */
#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
/* ID_DFR0: Debug Features Register 0 */
#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
/* ID_AFR0: Auxiliary Features Register 0 */
#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
/* ID_MMFR0: Memory Model Feature Register 0 */
#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
/* ID_MMFR1: Memory Model Feature Register 1 */
#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
/* ID_MMFR2: Memory Model Feature Register 2 */
#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
/* ID_MMFR3: Memory Model Feature Register 3 */
#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
/* ID_ISAR0: Instruction Set Attributes Register 0 */
#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
/* ID_ISAR1: Instruction Set Attributes Register 1 */
#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
/* ID_ISAR2: Instruction Set Attributes Register 2 */
#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
/* ID_ISAR3: Instruction Set Attributes Register 3 */
#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
/* ID_ISAR4: Instruction Set Attributes Register 4 */
#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
/* CPACR: Coprocessor Access Control Register */
#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
/* FPCCR: Floating-Point Context Control Register */
#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
/* FPCAR: Floating-Point Context Address Register */
#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
/* FPDSCR: Floating-Point Default Status Control Register */
#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
/* MVFR0: Media and Floating-Point Feature Register 0 */
#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
/* MVFR1: Media and Floating-Point Feature Register 1 */
#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
#endif
/* --- SCB values ---------------------------------------------------------- */
/* --- SCB_CPUID values ---------------------------------------------------- */
/* Implementer[31:24]: Implementer code */
#define SCB_CPUID_IMPLEMENTER_LSB 24
#define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)
/* Variant[23:20]: Variant number */
#define SCB_CPUID_VARIANT_LSB 20
#define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)
/* Constant[19:16]: Reads as 0xF (ARMv7-M) M3, M4 */
/* Constant[19:16]: Reads as 0xC (ARMv6-M) M0, M0+ */
#define SCB_CPUID_CONSTANT_LSB 16
#define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)
#define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)
#define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)
/* PartNo[15:4]: Part number of the processor */
#define SCB_CPUID_PARTNO_LSB 4
#define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)
/* Revision[3:0]: Revision number */
#define SCB_CPUID_REVISION_LSB 0
#define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)
/* --- SCB_ICSR values ----------------------------------------------------- */
/* NMIPENDSET: NMI set-pending bit */
#define SCB_ICSR_NMIPENDSET (1 << 31)
/* Bits [30:29]: reserved - must be kept cleared */
/* PENDSVSET: PendSV set-pending bit */
#define SCB_ICSR_PENDSVSET (1 << 28)
/* PENDSVCLR: PendSV clear-pending bit */
#define SCB_ICSR_PENDSVCLR (1 << 27)
/* PENDSTSET: SysTick exception set-pending bit */
#define SCB_ICSR_PENDSTSET (1 << 26)
/* PENDSTCLR: SysTick exception clear-pending bit */
#define SCB_ICSR_PENDSTCLR (1 << 25)
/* Bit 24: reserved - must be kept cleared */
/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
#define SCB_ICSR_ISRPREEMPT (1 << 23)
/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
#define SCB_ICSR_ISRPENDING (1 << 22)
/* VECTPENDING[21:12] Pending vector */
#define SCB_ICSR_VECTPENDING_LSB 12
#define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)
/* RETOBASE: Return to base level */
#define SCB_ICSR_RETOBASE (1 << 11)
/* Bits [10:9]: reserved - must be kept cleared */
/* VECTACTIVE[8:0] Active vector */
#define SCB_ICSR_VECTACTIVE_LSB 0
#define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)
/* --- SCB_VTOR values ----------------------------------------------------- */
/* IMPLEMENTATION DEFINED */
#if defined(__ARM_ARCH_6M__)
#define SCB_VTOR_TBLOFF_LSB 7
#define SCB_VTOR_TBLOFF (0x1FFFFFF << SCB_VTOR_TBLOFF_LSB)
#elif defined(CM1)
/* VTOR not defined there */
#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* Bits [31:30]: reserved - must be kept cleared */
/* TBLOFF[29:9]: Vector table base offset field */
/* inconsistent datasheet - LSB could be 11 */
/* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */
#define SCB_VTOR_TBLOFF_LSB 9
#define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB)
#endif
/* --- SCB_AIRCR values ---------------------------------------------------- */
/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
#define SCB_AIRCR_VECTKEYSTAT_LSB 16
#define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)
#define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)
/* ENDIANESS Data endianness bit */
#define SCB_AIRCR_ENDIANESS (1 << 15)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* Bits [14:11]: reserved - must be kept cleared */
/* PRIGROUP[10:8]: Interrupt priority grouping field */
#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
#define SCB_AIRCR_PRIGROUP_SHIFT 8
/* Bits [7:3]: reserved - must be kept cleared */
#endif
/* SYSRESETREQ System reset request */
#define SCB_AIRCR_SYSRESETREQ (1 << 2)
/* VECTCLRACTIVE */
#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* VECTRESET */
#define SCB_AIRCR_VECTRESET (1 << 0)
#endif
/* --- SCB_SCR values ------------------------------------------------------ */
/* Bits [31:5]: reserved - must be kept cleared */
/* SEVEONPEND Send Event on Pending bit */
#define SCB_SCR_SEVEONPEND (1 << 4)
/* Bit 3: reserved - must be kept cleared */
/* SLEEPDEEP */
#define SCB_SCR_SLEEPDEEP (1 << 2)
/* SLEEPONEXIT */
#define SCB_SCR_SLEEPONEXIT (1 << 1)
/* Bit 0: reserved - must be kept cleared */
/* --- SCB_CCR values ------------------------------------------------------ */
/* Bits [31:10]: reserved - must be kept cleared */
/* STKALIGN */
#define SCB_CCR_STKALIGN (1 << 9)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* BFHFNMIGN */
#define SCB_CCR_BFHFNMIGN (1 << 8)
/* Bits [7:5]: reserved - must be kept cleared */
/* DIV_0_TRP */
#define SCB_CCR_DIV_0_TRP (1 << 4)
#endif
/* UNALIGN_TRP */
#define SCB_CCR_UNALIGN_TRP (1 << 3)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* Bit 2: reserved - must be kept cleared */
/* USERSETMPEND */
#define SCB_CCR_USERSETMPEND (1 << 1)
/* NONBASETHRDENA */
#define SCB_CCR_NONBASETHRDENA (1 << 0)
#endif
/* These numbers are designed to be used with the SCB_SHPR() macro */
/* SCB_SHPR1 */
#define SCB_SHPR_PRI_4_MEMMANAGE 0
#define SCB_SHPR_PRI_5_BUSFAULT 1
#define SCB_SHPR_PRI_6_USAGEFAULT 2
#define SCB_SHPR_PRI_7_RESERVED 3
/* SCB_SHPR2 */
#define SCB_SHPR_PRI_8_RESERVED 4
#define SCB_SHPR_PRI_9_RESERVED 5
#define SCB_SHPR_PRI_10_RESERVED 6
#define SCB_SHPR_PRI_11_SVCALL 7
/* SCB_SHPR3 */
#define SCB_SHPR_PRI_12_RESERVED 8
#define SCB_SHPR_PRI_13_RESERVED 9
#define SCB_SHPR_PRI_14_PENDSV 10
#define SCB_SHPR_PRI_15_SYSTICK 11
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* --- SCB_SHCSR values ---------------------------------------------------- */
/* Bits [31:19]: reserved - must be kept cleared */
/* USGFAULTENA: Usage fault enable */
#define SCB_SHCSR_USGFAULTENA (1 << 18)
/* BUSFAULTENA: Bus fault enable */
#define SCB_SHCSR_BUSFAULTENA (1 << 17)
/* MEMFAULTENA: Memory management fault enable */
#define SCB_SHCSR_MEMFAULTENA (1 << 16)
/* SVCALLPENDED: SVC call pending */
#define SCB_SHCSR_SVCALLPENDED (1 << 15)
/* BUSFAULTPENDED: Bus fault exception pending */
#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
/* MEMFAULTPENDED: Memory management fault exception pending */
#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
/* USGFAULTPENDED: Usage fault exception pending */
#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
/* SYSTICKACT: SysTick exception active */
#define SCB_SHCSR_SYSTICKACT (1 << 11)
/* PENDSVACT: PendSV exception active */
#define SCB_SHCSR_PENDSVACT (1 << 10)
/* Bit 9: reserved - must be kept cleared */
/* MONITORACT: Debug monitor active */
#define SCB_SHCSR_MONITORACT (1 << 8)
/* SVCALLACT: SVC call active */
#define SCB_SHCSR_SVCALLACT (1 << 7)
/* Bits [6:4]: reserved - must be kept cleared */
/* USGFAULTACT: Usage fault exception active */
#define SCB_SHCSR_USGFAULTACT (1 << 3)
/* Bit 2: reserved - must be kept cleared */
/* BUSFAULTACT: Bus fault exception active */
#define SCB_SHCSR_BUSFAULTACT (1 << 1)
/* MEMFAULTACT: Memory management fault exception active */
#define SCB_SHCSR_MEMFAULTACT (1 << 0)
/* --- SCB_CFSR values ----------------------------------------------------- */
/* Bits [31:26]: reserved - must be kept cleared */
/* DIVBYZERO: Divide by zero usage fault */
#define SCB_CFSR_DIVBYZERO (1 << 25)
/* UNALIGNED: Unaligned access usage fault */
#define SCB_CFSR_UNALIGNED (1 << 24)
/* Bits [23:20]: reserved - must be kept cleared */
/* NOCP: No coprocessor usage fault */
#define SCB_CFSR_NOCP (1 << 19)
/* INVPC: Invalid PC load usage fault */
#define SCB_CFSR_INVPC (1 << 18)
/* INVSTATE: Invalid state usage fault */
#define SCB_CFSR_INVSTATE (1 << 17)
/* UNDEFINSTR: Undefined instruction usage fault */
#define SCB_CFSR_UNDEFINSTR (1 << 16)
/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
#define SCB_CFSR_BFARVALID (1 << 15)
/* Bits [14:13]: reserved - must be kept cleared */
/* STKERR: Bus fault on stacking for exception entry */
#define SCB_CFSR_STKERR (1 << 12)
/* UNSTKERR: Bus fault on unstacking for a return from exception */
#define SCB_CFSR_UNSTKERR (1 << 11)
/* IMPRECISERR: Imprecise data bus error */
#define SCB_CFSR_IMPRECISERR (1 << 10)
/* PRECISERR: Precise data bus error */
#define SCB_CFSR_PRECISERR (1 << 9)
/* IBUSERR: Instruction bus error */
#define SCB_CFSR_IBUSERR (1 << 8)
/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
#define SCB_CFSR_MMARVALID (1 << 7)
/* Bits [6:5]: reserved - must be kept cleared */
/* MSTKERR: Memory manager fault on stacking for exception entry */
#define SCB_CFSR_MSTKERR (1 << 4)
/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
#define SCB_CFSR_MUNSTKERR (1 << 3)
/* Bit 2: reserved - must be kept cleared */
/* DACCVIOL: Data access violation flag */
#define SCB_CFSR_DACCVIOL (1 << 1)
/* IACCVIOL: Instruction access violation flag */
#define SCB_CFSR_IACCVIOL (1 << 0)
/* --- SCB_HFSR values ----------------------------------------------------- */
/* DEBUG_VT: reserved for debug use */
#define SCB_HFSR_DEBUG_VT (1 << 31)
/* FORCED: Forced hard fault */
#define SCB_HFSR_FORCED (1 << 30)
/* Bits [29:2]: reserved - must be kept cleared */
/* VECTTBL: Vector table hard fault */
#define SCB_HFSR_VECTTBL (1 << 1)
/* Bit 0: reserved - must be kept cleared */
/* --- SCB_MMFAR values ---------------------------------------------------- */
/* MMFAR [31:0]: Memory management fault address */
/* --- SCB_BFAR values ----------------------------------------------------- */
/* BFAR [31:0]: Bus fault address */
/* --- SCB_CPACR values ---------------------------------------------------- */
/* CPACR CPn: Access privileges values */
#define SCB_CPACR_NONE 0 /* Access denied */
#define SCB_CPACR_PRIV 1 /* Privileged access only */
#define SCB_CPACR_FULL 3 /* Full access */
/* CPACR [20:21]: Access privileges for coprocessor 10 */
#define SCB_CPACR_CP10 (1 << 20)
/* CPACR [22:23]: Access privileges for coprocessor 11 */
#define SCB_CPACR_CP11 (1 << 22)
#endif
/* --- SCB functions ------------------------------------------------------- */
BEGIN_DECLS
struct scb_exception_stack_frame {
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r12;
uint32_t lr;
uint32_t pc;
uint32_t xpsr;
} __attribute__((packed));
#define SCB_GET_EXCEPTION_STACK_FRAME(f) \
do { \
asm volatile ("mov %[frameptr], sp" \
: [frameptr]"=r" (f)); \
} while (0)
void scb_reset_system(void) __attribute__((noreturn, naked));
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
void scb_reset_core(void) __attribute__((noreturn, naked));
void scb_set_priority_grouping(uint32_t prigroup);
#endif
END_DECLS
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_SCS_H
#define LIBOPENCM3_CM3_SCS_H
/*
* All the definition hereafter are generic for CortexMx ARMv7-M
* See ARM document "ARMv7-M Architecture Reference Manual" for more details.
* See also ARM document "ARM Compiler toolchain Developing Software for ARM
* Processors" for details on System Timer/SysTick.
*/
/*
* The System Control Space (SCS) is a memory-mapped 4KB address space that
* provides 32-bit registers for configuration, status reporting and control.
* The SCS registers divide into the following groups:
* - system control and identification
* - the CPUID processor identification space
* - system configuration and status
* - fault reporting
* - a system timer, SysTick
* - a Nested Vectored Interrupt Controller (NVIC)
* - a Protected Memory System Architecture (PMSA)
* - system debug.
*/
/* System Handler Priority 8 bits Registers, SHPR1/2/3 */
/* Note: 12 8bit Registers */
#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id)
/*
* Debug Halting Control and Status Register (DHCSR).
*
* Purpose Controls halting debug.
* Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when
* the system is running with halting debug enabled is UNPREDICTABLE.
* Halting debug is enabled when C_DEBUGEN is set to 1. The system is running
* when S_HALT is set to 0.
* - When C_DEBUGEN is set to 0, the processor ignores the values of all other
* bits in this register.
* - For more information about the use of DHCSR see Debug stepping on page
* C1-824.
* Configurations Always implemented.
*/
/* SCS_DHCSR register */
#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)
/*
* Debug Core Register Selector Register (DCRSR).
*
* Purpose With the DCRDR, the DCRSR provides debug access to the ARM core
* registers, special-purpose registers, and Floating-point extension
* registers. A write to DCRSR specifies the register to transfer, whether the
* transfer is a read or a write, and starts the transfer.
* Usage constraints: Only accessible in Debug state.
* Configurations Always implemented.
*
*/
/* SCS_DCRS register */
#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)
/*
* Debug Core Register Data Register (DCRDR)
*
* Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR
* provides debug access to the ARM core registers, special-purpose registers,
* and Floating-point extension registers. The DCRDR is the data register for
* these accesses.
* - Used on its own, the DCRDR provides a message passing resource between an
* external debugger and a debug agent running on the processor.
* Note:
* The architecture does not define any handshaking mechanism for this use of
* DCRDR.
* Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to
* particular transfers using the DCRSR and DCRDR.
* Configurations Always implemented.
*
*/
/* SCS_DCRDR register */
#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)
/*
* Debug Exception and Monitor Control Register (DEMCR).
*
* Purpose Manages vector catch behavior and DebugMonitor handling when
* debugging.
* Usage constraints:
* - Bits [23:16] provide DebugMonitor exception control.
* - Bits [15:0] provide Debug state, halting debug, control.
* Configurations Always implemented.
*
*/
/* SCS_DEMCR register */
#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)
/* Debug Halting Control and Status Register (DHCSR) */
#define SCS_DHCSR_DBGKEY 0xA05F0000
#define SCS_DHCSR_C_DEBUGEN 0x00000001
#define SCS_DHCSR_C_HALT 0x00000002
#define SCS_DHCSR_C_STEP 0x00000004
#define SCS_DHCSR_C_MASKINTS 0x00000008
#define SCS_DHCSR_C_SNAPSTALL 0x00000020
#define SCS_DHCSR_S_REGRDY 0x00010000
#define SCS_DHCSR_S_HALT 0x00020000
#define SCS_DHCSR_S_SLEEP 0x00040000
#define SCS_DHCSR_S_LOCKUP 0x00080000
#define SCS_DHCSR_S_RETIRE_ST 0x01000000
#define SCS_DHCSR_S_RESET_ST 0x02000000
/* Debug Core Register Selector Register (DCRSR) */
#define SCS_DCRSR_REGSEL_MASK 0x0000001F
#define SCS_DCRSR_REGSEL_XPSR 0x00000010
#define SCS_DCRSR_REGSEL_MSP 0x00000011
#define SCS_DCRSR_REGSEL_PSP 0x00000012
/* Debug Exception and Monitor Control Register (DEMCR) */
/* Bits 31:25 - Reserved */
#define SCS_DEMCR_TRCENA (1 << 24)
/* Bits 23:20 - Reserved */
#define SCS_DEMCR_MON_REQ (1 << 19)
#define SCS_DEMCR_MON_STEP (1 << 18)
#define SCS_DEMCR_VC_MON_PEND (1 << 17)
#define SCS_DEMCR_VC_MON_EN (1 << 16)
/* Bits 15:11 - Reserved */
#define SCS_DEMCR_VC_HARDERR (1 << 10)
#define SCS_DEMCR_VC_INTERR (1 << 9)
#define SCS_DEMCR_VC_BUSERR (1 << 8)
#define SCS_DEMCR_VC_STATERR (1 << 7)
#define SCS_DEMCR_VC_CHKERR (1 << 6)
#define SCS_DEMCR_VC_NOCPERR (1 << 5)
#define SCS_DEMCR_VC_MMERR (1 << 4)
/* Bits 3:1 - Reserved */
#define SCS_DEMCR_VC_CORERESET (1 << 0)
/*
* System Control Space (SCS) => System timer register support in the SCS.
* To configure SysTick, load the interval required between SysTick events to
* the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in
* the SysTick Control and Status register, is activated on the transition from
* 1 to 0, therefore it activates every n+1 clock ticks. If you require a
* period of 100, write 99 to the SysTick Reload Value register. The SysTick
* Reload Value register supports values between 0x1 and 0x00FFFFFF.
*
* If you want to use SysTick to generate an event at a timed interval, for
* example 1ms, you can use the SysTick Calibration Value Register to scale
* your value for the Reload register. The SysTick Calibration Value Register
* is a read-only register that contains the number of pulses for a period of
* 10ms, in the TENMS field, bits[23:0].
*
* This register also has a SKEW bit. Bit[30] == 1 indicates that the
* calibration for 10ms in the TENMS section is not exactly 10ms due to clock
* frequency. Bit[31] == 1 indicates that the reference clock is not provided.
*/
/*
* SysTick Control and Status Register (CSR).
* Purpose Controls the system timer and provides status data.
* Usage constraints: There are no usage constraints.
* Configurations Always implemented.
*/
#define SCS_SYST_CSR MMIO32(SCS_BASE + 0x10)
/* SysTick Reload Value Register (CVR).
* Purpose Reads or clears the current counter value.
* Usage constraints:
* - Any write to the register clears the register to zero.
* - The counter does not provide read-modify-write protection.
* - Unsupported bits are read as zero
* Configurations Always implemented.
*/
#define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14)
/* SysTick Current Value Register (RVR).
* Purpose Holds the reload value of the SYST_CVR.
* Usage constraints There are no usage constraints.
* Configurations Always implemented.
*/
#define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18)
/*
* SysTick Calibration value Register(Read Only) (CALIB)
* Purpose Reads the calibration value and parameters for SysTick.
* Usage constraints: There are no usage constraints.
* Configurations Always implemented.
*/
#define CM_SCS_SYST_CALIB MMIO32(SCS_BASE + 0x1C)
/* --- SCS_SYST_CSR values ----------------------------------------------- */
/* Counter is operating. */
#define SCS_SYST_CSR_ENABLE (BIT0)
/* Count to 0 changes the SysTick exception status to pending. */
#define SCS_SYST_CSR_TICKINT (BIT1)
/* SysTick uses the processor clock. */
#define SCS_SYST_CSR_CLKSOURCE (BIT2)
/*
* Indicates whether the counter has counted to 0 since the last read of this
* register:
* 0 = Timer has not counted to 0
* 1 = Timer has counted to 0.
*/
#define SCS_SYST_CSR_COUNTFLAG (BIT16)
/* --- CM_SCS_SYST_RVR values ---------------------------------------------- */
/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter
* reaches 0.
*/
/* Bit 24 to 31 are Reserved */
/* --- CM_SCS_SYST_CVR values ---------------------------------------------- */
/* Bit0 to 31 => Reads or clears the current counter value. */
/* --- CM_SCS_SYST_CALIB values -------------------------------------------- */
/*
* Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms
* (100Hz) timing, subject to system clock skew errors. If this field is zero,
* the calibration value is not known.
*/
#define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1)
/*
* Bit30 => SKEW Indicates whether the 10ms calibration value is exact:
* 0 = 10ms calibration value is exact.
* 1 = 10ms calibration value is inexact, because of the clock frequency
*/
#define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30)
/*
* Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock
* is implemented:
* 0 = The reference clock is implemented.
* 1 = The reference clock is not implemented.
* When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to
* 1 and cannot be cleared to 0.
*/
#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31)
/*
* System Control Space (SCS) => Data Watchpoint and Trace (DWT).
* See "ARMv7-M Architecture Reference Manual"
* (https://github.com/libopencm3/libopencm3-archive/blob/master/arm/
* ARMv7-M_ARM.pdf)
* The DWT is an optional debug unit that provides watchpoints, data tracing,
* and system profiling for the processor.
*/
/*
* DWT Control register
* Purpose Provides configuration and status information for the DWT block, and
* used to control features of the block
* Usage constraints: There are no usage constraints.
* Configurations Always implemented.
*/
#define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00)
/*
* DWT_CYCCNT register
* Cycle Count Register (Shows or sets the value of the processor cycle
* counter, CYCCNT)
* When enabled, CYCCNT increments on each processor clock cycle. On overflow,
* CYCCNT wraps to zero.
*
* Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
* Usage constraints: The DWT unit suspends CYCCNT counting when the processor
* is in Debug state.
* Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control
* register, DWT_CTRL.
* When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this
* register is UNK/SBZP.
*/
#define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
/* DWT_CPICNT register
* Purpose Counts additional cycles required to execute multi-cycle
* instructions and instruction fetch stalls.
* Usage constraints: The counter initializes to 0 when software enables its
* counter overflow event by
* setting the DWT_CTRL.CPIEVTENA bit to 1.
* Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control
* register, DWT_CTRL.
* If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
* include the profiling counters, this register is UNK/SBZP.
*/
#define SCS_DWT_CPICNT MMIO32(DWT_BASE + 0x08)
/* DWT_EXCCNT register */
#define SCS_DWT_EXCCNT MMIO32(DWT_BASE + 0x0C)
/* DWT_EXCCNT register */
#define SCS_DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10)
/* DWT_EXCCNT register */
#define SCS_DWT_LSUCNT MMIO32(DWT_BASE + 0x14)
/* DWT_EXCCNT register */
#define SCS_DWT_FOLDCNT MMIO32(DWT_BASE + 0x18)
/* DWT_PCSR register */
#define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18)
/* --- SCS_DWT_CTRL values ------------------------------------------------- */
/*
* Enables CYCCNT:
* 0 = Disabled, 1 = Enabled
* This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
*/
#define SCS_DWT_CTRL_CYCCNTENA (BIT0)
/* TODO bit definition values for other DWT_XXX register */
/* Macro to be called at startup to enable SCS & Cycle Counter */
#define SCS_DWT_CYCLE_COUNTER_ENABLED() ((SCS_DEMCR |= SCS_DEMCR_TRCENA)\
(SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA))
#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR = 0)
/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not
* enabled)
*/
#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \
SCS_SYST_CSR_CLKSOURCE))
/* Macro to be called at startup to Enable CortexMx SysTick and IRQ */
#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \
SCS_SYST_CSR_CLKSOURCE | \
SCS_SYST_CSR_TICKINT))
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_SYNC_H
#define LIBOPENCM3_CM3_SYNC_H
#include "common.h"
#ifdef __cplusplus
extern "C" {
#endif
void __dmb(void);
/* Implements synchronisation primitives as discussed in the ARM document
* DHT0008A (ID081709) "ARM Synchronization Primitives" and the ARM v7-M
* Architecture Reference Manual.
*/
/* --- Exclusive load and store instructions ------------------------------- */
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
uint32_t __ldrex(volatile uint32_t *addr);
uint32_t __strex(uint32_t val, volatile uint32_t *addr);
/* --- Convenience functions ----------------------------------------------- */
/* Here we implement some simple synchronisation primitives. */
typedef uint32_t mutex_t;
#define MUTEX_UNLOCKED 0
#define MUTEX_LOCKED 1
void mutex_lock(mutex_t *m);
void mutex_unlock(mutex_t *m);
#endif
#ifdef __cplusplus
}
#endif
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup CM3_systick_defines SysTick Defines
*
* @brief <b>libopencm3 Defined Constants and Types for the Cortex SysTick </b>
*
* @ingroup CM3_defines
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
*
* @date 19 August 2012
*
* LGPL License Terms @ref lgpl_license
*/
/**
* @note this file has been not following the register naming scheme, the
* correct names defined, and the old ones stay there for compatibility with
* old software (will be deprecated in the future)
*/
/**@{*/
#ifndef LIBOPENCM3_SYSTICK_H
#define LIBOPENCM3_SYSTICK_H
#include <libopencm3/cm3/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- SYSTICK registers --------------------------------------------------- */
/* Control and status register (STK_CTRL) */
#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00)
#define STK_CSR MMIO32(SYS_TICK_BASE + 0x00)
/* reload value register (STK_LOAD) */
#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04)
#define STK_RVR MMIO32(SYS_TICK_BASE + 0x04)
/* current value register (STK_VAL) */
#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08)
#define STK_CVR MMIO32(SYS_TICK_BASE + 0x08)
/* calibration value register (STK_CALIB) */
#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
/* --- STK_CSR values ------------------------------------------------------ */
/* Bits [31:17] Reserved, must be kept cleared. */
/* COUNTFLAG: */
#define STK_CTRL_COUNTFLAG (1 << 16)
#define STK_CSR_COUNTFLAG (1 << 16)
/* Bits [15:3] Reserved, must be kept cleared. */
/* CLKSOURCE: Clock source selection */
#define STK_CTRL_CLKSOURCE_LSB 2
#define STK_CTRL_CLKSOURCE (1 << STK_CTRL_CLKSOURCE_LSB)
#define STK_CSR_CLKSOURCE_LSB 2
#define STK_CSR_CLKSOURCE (1 << STK_CSR_CLKSOURCE_LSB)
/** @defgroup systick_clksource Clock source selection
@ingroup CM3_systick_defines
@{*/
#if defined(__ARM_ARCH_6M__)
#define STK_CSR_CLKSOURCE_EXT (0 << STK_CSR_CLKSOURCE_LSB)
#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB)
#else
#define STK_CTRL_CLKSOURCE_AHB_DIV8 (0 << STK_CTRL_CLKSOURCE_LSB)
#define STK_CTRL_CLKSOURCE_AHB (1 << STK_CTRL_CLKSOURCE_LSB)
#endif
/**@}*/
/* TICKINT: SysTick exception request enable */
#define STK_CTRL_TICKINT (1 << 1)
#define STK_CSR_TICKINT (1 << 1)
/* ENABLE: Counter enable */
#define STK_CTRL_ENABLE (1 << 0)
#define STK_CSR_ENABLE (1 << 0)
/* --- STK_RVR values ------------------------------------------------------ */
/* Bits [31:24] Reserved, must be kept cleared. */
/* RELOAD[23:0]: RELOAD value */
#define STK_RVR_RELOAD 0x00FFFFFF
/* --- STK_CVR values ------------------------------------------------------ */
/* Bits [31:24] Reserved, must be kept cleared. */
/* CURRENT[23:0]: Current counter value */
#define STK_CVR_CURRENT 0x00FFFFFF
/* --- STK_CALIB values ---------------------------------------------------- */
/* NOREF: NOREF flag */
#define STK_CALIB_NOREF (1 << 31)
/* SKEW: SKEW flag */
#define STK_CALIB_SKEW (1 << 30)
/* Bits [29:24] Reserved, must be kept cleared. */
/* TENMS[23:0]: Calibration value */
#define STK_CALIB_TENMS 0x00FFFFFF
/* --- Function Prototypes ------------------------------------------------- */
BEGIN_DECLS
void systick_set_reload(uint32_t value);
uint32_t systick_get_reload(void);
uint32_t systick_get_value(void);
void systick_set_clocksource(uint8_t clocksource);
void systick_interrupt_enable(void);
void systick_interrupt_disable(void);
void systick_counter_enable(void);
void systick_counter_disable(void);
uint8_t systick_get_countflag(void);
uint32_t systick_get_calib(void);
END_DECLS
#endif
/**@}*/

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CM3_TPIU_H
#define LIBOPENCM3_CM3_TPIU_H
/* Cortex-M3 Trace Port Interface Unit (TPIU) */
/* Those defined only on ARMv7 and above */
#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
#error "Trace Port Interface Unit not available in CM0"
#endif
/* --- TPIU registers ------------------------------------------------------ */
/* Supported Synchronous Port Size (TPIU_SSPSR) */
#define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000)
/* Current Synchronous Port Size (TPIU_CSPSR) */
#define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004)
/* Asynchronous Clock Prescaler (TPIU_ACPR) */
#define TPIU_ACPR MMIO32(TPIU_BASE + 0x010)
/* Selected Pin Protocol (TPIU_SPPR) */
#define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0)
/* Formatter and Flush Status Register (TPIU_FFSR) */
#define TPIU_FFSR MMIO32(TPIU_BASE + 0x300)
/* Formatter and Flush Control Register (TPIU_FFCR) */
#define TPIU_FFCR MMIO32(TPIU_BASE + 0x304)
/* (TPIU_DEVID) */
#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8)
/* TODO: PID, CID */
/* --- TPIU_SSPSR values --------------------------------------------------- */
/*
* bit[N] == 0, trace port width of (N+1) not supported
* bit[N] == 1, trace port width of (N+1) supported
*/
#define TPIU_SSPSR_BYTE (1 << 0)
#define TPIU_SSPSR_HALFWORD (1 << 1)
#define TPIU_SSPSR_WORD (1 << 3)
/* --- TPIU_SSPSR values --------------------------------------------------- */
/* Same format as TPIU_SSPSR, except only one is set */
#define TPIU_CSPSR_BYTE (1 << 0)
#define TPIU_CSPSR_HALFWORD (1 << 1)
#define TPIU_CSPSR_WORD (1 << 3)
/* --- TPIU_ACPR values ---------------------------------------------------- */
/* Bits 31:16 - Reserved */
/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */
/* --- TPIU_SPPR values ---------------------------------------------------- */
/* Bits 31:2 - Reserved */
#define TPIU_SPPR_SYNC (0x0)
#define TPIU_SPPR_ASYNC_MANCHESTER (0x1)
#define TPIU_SPPR_ASYNC_NRZ (0x2)
/* --- TPIU_FFSR values ---------------------------------------------------- */
/* Bits 31:4 - Reserved */
#define TPIU_FFSR_FTNONSTOP (1 << 3)
#define TPIU_FFSR_TCPRESENT (1 << 2)
#define TPIU_FFSR_FTSTOPPED (1 << 1)
#define TPIU_FFSR_FLINPROG (1 << 0)
/* --- TPIU_FFCR values ---------------------------------------------------- */
/* Bits 31:9 - Reserved */
#define TPIU_FFCR_TRIGIN (1 << 8)
/* Bits 7:2 - Reserved */
#define TPIU_FFCR_ENFCONT (1 << 1)
/* Bit 0 - Reserved */
/* --- TPIU_DEVID values ---------------------------------------------------- */
/* Bits 31:16 - Reserved */
/* Bits 15:12 - Implementation defined */
#define TPUI_DEVID_NRZ_SUPPORTED (1 << 11)
#define TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10)
/* Bit 9 - RAZ, indicated that trace data and clock are supported */
#define TPUI_DEVID_FIFO_SIZE_MASK (7 << 6)
/* Bits 5:0 - Implementation defined */
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
*
* Definitions for handling vector tables.
*
* This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2
* (from the EFM32 documentation at
* http://www.energymicro.com/downloads/datasheets), and was seen analogously
* in other ARM implementations' libopencm3 files.
*
* The structure of the vector table is implemented independently of the system
* vector table starting at memory position 0x0, as it can be relocated to
* other memory locations too.
*
* The exact size of a vector interrupt table depends on the number of
* interrupts IRQ_COUNT, which is defined per family.
*/
#ifndef LIBOPENCM3_VECTOR_H
#define LIBOPENCM3_VECTOR_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/nvic.h>
/** Type of an interrupt function. Only used to avoid hard-to-read function
* pointers in the efm32_vector_table_t struct. */
typedef void (*vector_table_entry_t)(void);
typedef struct {
unsigned int *initial_sp_value; /**< Initial stack pointer value. */
vector_table_entry_t reset;
vector_table_entry_t nmi;
vector_table_entry_t hard_fault;
vector_table_entry_t memory_manage_fault; /* not in CM0 */
vector_table_entry_t bus_fault; /* not in CM0 */
vector_table_entry_t usage_fault; /* not in CM0 */
vector_table_entry_t reserved_x001c[4];
vector_table_entry_t sv_call;
vector_table_entry_t debug_monitor; /* not in CM0 */
vector_table_entry_t reserved_x0034;
vector_table_entry_t pend_sv;
vector_table_entry_t systick;
vector_table_entry_t irq[NVIC_IRQ_COUNT];
} vector_table_t;
extern vector_table_t vector_table;
#endif

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/** @mainpage libopencm3 Developer Documentation
@version 1.0.0
@date 7 September 2012
* The libopencm3 project (previously known as libopenstm32) aims to create
* a free/libre/open-source (GPL v3, or later) firmware library for various
* ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03,
* Atmel SAM3U, NXP LPC1000 and others.
*
* @par ""
*
* See the <a href="http://www.libopencm3.org">libopencm3 wiki</a> for
* more information.
LGPL License Terms @ref lgpl_license
*/

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/** @mainpage libopencm3 EFM32 Gecko
@version 1.0.0
@date 11 November 2012
API documentation for Energy Micro EFM32 Gecko Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup EFM32G EFM32 Gecko
Libraries for Energy Micro EFM32 Gecko series.
@version 1.0.0
@date 11 November 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup EFM32G_defines EFM32 Gecko Defines
@brief Defined Constants and Types for the Energy Micro EFM32 Gecko series
@version 1.0.0
@date 11 November 2012
LGPL License Terms @ref lgpl_license
*/

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includeguard: LIBOPENCM3_EFM32G_NVIC_H
partname_humanreadable: EFM32 Gecko series
partname_doxygen: EFM32G
# The names and sequence are taken from d0001_efm32g_reference_manual.pdf table 4.1.
irqs:
- dma
- gpio_even
- timer0
- usart0_rx
- usart0_tx
- acmp01
- adc0
- dac0
- i2c0
- gpio_odd
- timer1
- timer2
- usart1_rx
- usart1_tx
- usart2_rx
- usart2_tx
- uart0_rx
- uart0_tx
- leuart0
- leuart1
- letimer0
- pcnt0
- pcnt1
- pcnt2
- rtc
- cmu
- vcmp
- lcd
- msc
- aes

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/** @mainpage libopencm3 EFM32 Giant Gecko
@version 1.0.0
@date 11 November 2012
API documentation for Energy Micro EFM32 Giant Gecko Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup EFM32GG EFM32 Giant Gecko
Libraries for Energy Micro EFM32 Giant Gecko series.
@version 1.0.0
@date 11 November 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup EFM32GG_defines EFM32 Giant Gecko Defines
@brief Defined Constants and Types for the Energy Micro EFM32 Giant Gecko series
@version 1.0.0
@date 11 November 2012
LGPL License Terms @ref lgpl_license
*/

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includeguard: LIBOPENCM3_EFM32GG_NVIC_H
partname_humanreadable: EFM32 Giant Gecko series
partname_doxygen: EFM32GG
# The names and sequence are taken from d0053_efm32gg_refreence_manual.pdf table 4.1.
irqs:
- dma
- gpio_even
- timer0
- usart0_rx
- usart0_tx
- usb
- acmp01
- adc0
- dac0
- i2c0
- i2c1
- gpio_odd
- timer1
- timer2
- timer3
- usart1_rx
- usart1_tx
- lesense
- usart2_rx
- usart2_tx
- uart0_rx
- uart0_tx
- uart1_rx
- uart1_tx
- leuart0
- leuart1
- letimer0
- pcnt0
- pcnt1
- pcnt2
- rtc
- burtc
- cmu
- vcmp
- lcd
- msc
- aes
- ebi

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/** @mainpage libopencm3 EFM32 Leopard Gecko
@version 1.0.0
@date 4 March 2013
API documentation for Energy Micro EFM32 Leopard Gecko Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup EFM32LG EFM32 LeopardGecko
Libraries for Energy Micro EFM32 Leopard Gecko series.
@version 1.0.0
@date 4 March 2013
LGPL License Terms @ref lgpl_license
*/
/** @defgroup EFM32LG_defines EFM32 Leopard Gecko Defines
@brief Defined Constants and Types for the Energy Micro EFM32 Leopard Gecko
series
@version 1.0.0
@date 4 March 2013
LGPL License Terms @ref lgpl_license
*/

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includeguard: LIBOPENCM3_EFM32LG_NVIC_H
partname_humanreadable: EFM32 Leopard Gecko series
partname_doxygen: EFM32LG
# The names and sequence are taken from d0183_efm32lg_reference_manual.pdf table 4.1.
irqs:
- dma
- gpio_even
- timer0
- usart0_rx
- usart0_tx
- usb
- acmp01
- adc0
- dac0
- i2c0
- i2c1
- gpio_odd
- timer1
- timer2
- timer3
- usart1_rx
- usart1_tx
- lesense
- usart2_rx
- usart2_tx
- uart0_rx
- uart0_tx
- uart1_rx
- uart1_tx
- leuart0
- leuart1
- letimer0
- pcnt0
- pcnt1
- pcnt2
- rtc
- burtc
- cmu
- vcmp
- lcd
- msc
- aes
- ebi

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/** @mainpage libopencm3 EFM32 Tiny Gecko
@version 1.0.0
@date 4 March 2013
API documentation for Energy Micro EFM32 Tiny Gecko Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup EFM32TG EFM32 TinyGecko
Libraries for Energy Micro EFM32 Tiny Gecko series.
@version 1.0.0
@date 4 March 2013
LGPL License Terms @ref lgpl_license
*/
/** @defgroup EFM32TG_defines EFM32 Tiny Gecko Defines
@brief Defined Constants and Types for the Energy Micro EFM32 Tiny Gecko series
@version 1.0.0
@date 4 March 2013
LGPL License Terms @ref lgpl_license
*/

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includeguard: LIBOPENCM3_EFM32TG_NVIC_H
partname_humanreadable: EFM32 Tiny Gecko series
partname_doxygen: EFM32TG
# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
irqs:
- dma
- gpio_even
- timer0
- usart0_rx
- usart0_tx
- acmp01
- adc0
- dac0
- i2c0
- gpio_odd
- timer1
- usart1_rx
- usart1_tx
- lesense
- leuart0
- letimer0
- pcnt0
- rtc
- cmu
- vcmp
- lcd
- msc
- aes

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
*
* Layout of the system address space of Tiny Gecko devices.
*
* This reflects d0034_efm32tg_reference_manual.pdf figure 5.2.
*/
/* The common cortex-m3 definitions were verified from
* d0034_efm32tg_reference_manual.pdf figure 5.2. The CM3 ROM Table seems to be
* missing there. The details (everything based on SCS_BASE) was verified from
* d0002_efm32_cortex-m3_reference_manual.pdf table 4.1, and seems to fit, but
* there are discrepancies. */
#include <libopencm3/cm3/memorymap.h>
#define CODE_BASE 0x00000000
#define SRAM_BASE 0x20000000
#define SRAM_BASE_BITBAND 0x22000000
#define PERIPH_BASE 0x40000000
#define PERIPH_BASE_BITBAND 0x42000000
/* Details of the "Code" section */
#define FLASH_BASE (CODE_BASE + 0x00000000)
#define USERDATA_BASE (CODE_BASE + 0x0fe00000)
#define LOCKBITS_BASE (CODE_BASE + 0x0fe04000)
#define CHIPCONFIG_BASE (CODE_BASE + 0x0fe08000)
#define CODESPACESRAM_BASE (CODE_BASE + 0x10000000)
/* Tiny Gecko peripherial definitions */
#define VCMP_BASE (PERIPH_BASE + 0x00000000)
#define ACMP0_BASE (PERIPH_BASE + 0x00001000)
#define ACMP1_BASE (PERIPH_BASE + 0x00001400)
#define ADC_BASE (PERIPH_BASE + 0x00002000)
#define DAC0_BASE (PERIPH_BASE + 0x00004000)
#define GPIO_BASE (PERIPH_BASE + 0x00006000) /**< @see gpio.h */
#define I2C0_BASE (PERIPH_BASE + 0x0000a000)
#define USART0_BASE (PERIPH_BASE + 0x0000c000)
#define USART1_BASE (PERIPH_BASE + 0x0000c400)
#define TIMER0_BASE (PERIPH_BASE + 0x00010000)
#define TIMER1_BASE (PERIPH_BASE + 0x00010400)
#define RTC_BASE (PERIPH_BASE + 0x00080000)
#define LETIMER0_BASE (PERIPH_BASE + 0x00082000)
#define LEUART0_BASE (PERIPH_BASE + 0x00084000)
#define PCNT0_BASE (PERIPH_BASE + 0x00086000)
#define WDOG_BASE (PERIPH_BASE + 0x00088000)
#define LCD_BASE (PERIPH_BASE + 0x0008a000)
#define LESENSE_BASE (PERIPH_BASE + 0x0008c000)
#define MSC_BASE (PERIPH_BASE + 0x000c0000)
#define DMA_BASE (PERIPH_BASE + 0x000c2000)
#define EMU_BASE (PERIPH_BASE + 0x000c6000)
#define CMU_BASE (PERIPH_BASE + 0x000c8000) /**< @see cmu.h */
#define RMU_BASE (PERIPH_BASE + 0x000ca000)
#define PRS_BASE (PERIPH_BASE + 0x000cc000)
#define AES_BASE (PERIPH_BASE + 0x000e0000)

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @file
*
* Dispatcher for the base address definitions, depending on the particular
* Gecko family.
*
* @see tinygecko/memorymap.h
*/
#ifndef LIBOPENCM3_EFM32_MEMORYMAP_H
#define LIBOPENCM3_EFM32_MEMORYMAP_H
#ifdef TINYGECKO
# include <libopencm3/efm32/tinygecko/memorymap.h>
#else
# error "efm32 family not defined."
#endif
#endif

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/** @page lgpl_license libopencm3 License
libopencm3 is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option) any
later version.
libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License along with this
program. If not, see <http://www.gnu.org/licenses/>.
*/

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/** @mainpage libopencm3 LM3S
@version 1.0.0
@date 14 September 2012
API documentation for TI Stellaris LM3S Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LM3Sxx LM3S
Libraries for TI Stellaris LM3S series.
@version 1.0.0
@date 7 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LM3Sxx_defines LM3S Defines
@brief Defined Constants and Types for the LM3S series
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

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/** @defgroup gpio_defines General Purpose I/O Defines
@brief <b>Defined Constants and Types for the LM3S General Purpose I/O</b>
@ingroup LM3Sxx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2011
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LM3S_GPIO_H
#define LM3S_GPIO_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lm3s/memorymap.h>
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
#define GPIOA GPIOA_APB_BASE
#define GPIOB GPIOB_APB_BASE
#define GPIOC GPIOC_APB_BASE
#define GPIOD GPIOD_APB_BASE
#define GPIOE GPIOE_APB_BASE
#define GPIOF GPIOF_APB_BASE
#define GPIOG GPIOG_APB_BASE
#define GPIOH GPIOH_APB_BASE
/* GPIO number definitions (for convenience) */
#define GPIO0 (1 << 0)
#define GPIO1 (1 << 1)
#define GPIO2 (1 << 2)
#define GPIO3 (1 << 3)
#define GPIO4 (1 << 4)
#define GPIO5 (1 << 5)
#define GPIO6 (1 << 6)
#define GPIO7 (1 << 7)
/* --- GPIO registers ------------------------------------------------------ */
#define GPIO_DATA(port) (&MMIO32(port + 0x000))
#define GPIO_DIR(port) MMIO32(port + 0x400)
#define GPIO_IS(port) MMIO32(port + 0x404)
#define GPIO_IBE(port) MMIO32(port + 0x408)
#define GPIO_IEV(port) MMIO32(port + 0x40c)
#define GPIO_IM(port) MMIO32(port + 0x410)
#define GPIO_RIS(port) MMIO32(port + 0x414)
#define GPIO_MIS(port) MMIO32(port + 0x418)
#define GPIO_ICR(port) MMIO32(port + 0x41c)
#define GPIO_AFSEL(port) MMIO32(port + 0x420)
#define GPIO_DR2R(port) MMIO32(port + 0x500)
#define GPIO_DR4R(port) MMIO32(port + 0x504)
#define GPIO_DR8R(port) MMIO32(port + 0x508)
#define GPIO_ODR(port) MMIO32(port + 0x50c)
#define GPIO_PUR(port) MMIO32(port + 0x510)
#define GPIO_PDR(port) MMIO32(port + 0x514)
#define GPIO_SLR(port) MMIO32(port + 0x518)
#define GPIO_DEN(port) MMIO32(port + 0x51c)
#define GPIO_LOCK(port) MMIO32(port + 0x520)
#define GPIO_CR(port) MMIO32(port + 0x524)
#define GPIO_AMSEL(port) MMIO32(port + 0x528)
BEGIN_DECLS
void gpio_set(uint32_t gpioport, uint8_t gpios);
void gpio_clear(uint32_t gpioport, uint8_t gpios);
END_DECLS
/**@}*/
#endif

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# Although this says LM3S, the interrupt table applies to the LM4F as well
# Some interrupt vectores marked as reserved in LM3S are used in LM4F, and some
# vectors in LM3S are marked reserved for LM4F. However, the common vectors are
# identical, and we can safely use the same interrupt table. Reserved vectors
# will never be triggered, so having them is perfectly safe.
includeguard: LIBOPENCM3_LM3S_NVIC_H
partname_humanreadable: LM3S series
partname_doxygen: LM3S
irqs:
0: GPIOA
1: GPIOB
2: GPIOC
3: GPIOD
4: GPIOE
5: UART0
6: UART1
7: SSI0
8: I2C0
9: PWM0_FAULT
10: PWM0_0
11: PWM0_1
12: PWM0_2
13: QEI0
14: ADC0SS0
15: ADC0SS1
16: ADC0SS2
17: ADC0SS3
18: WATCHDOG
19: TIMER0A
20: TIMER0B
21: TIMER1A
22: TIMER1B
23: TIMER2A
24: TIMER2B
25: COMP0
26: COMP1
27: COMP2
28: SYSCTL
29: FLASH
30: GPIOF
31: GPIOG
32: GPIOH
33: UART2
34: SSI1
35: TIMER3A
36: TIMER3B
37: I2C1
38: QEI1
39: CAN0
40: CAN1
41: CAN2
42: ETH
43: HIBERNATE
44: USB0
45: PWM0_3
46: UDMA
47: UDMAERR
48: ADC1SS0
49: ADC1SS1
50: ADC1SS2
51: ADC1SS3
52: I2S0
53: EPI0
54: GPIOJ
55: GPIOK
56: GPIOL
57: SSI2
58: SSI3
59: UART3
60: UART4
61: UART5
62: UART6
63: UART7
# undefined: slot 64 - 67
68: I2C2
69: I2C3
70: TIMER4A
71: TIMER4B
# undefined: slot 72 - 91
92: TIMER5A
93: TIMER5B
94: WTIMER0A
95: WTIMER0B
96: WTIMER1A
97: WTIMER1B
98: WTIMER2A
99: WTIMER2B
100: WTIMER3A
101: WTIMER3B
102: WTIMER4A
103: WTIMER4B
104: WTIMER5A
105: WTIMER5B
106: SYSEXC
107: PECI0
108: LPC0
109: I2C4
110: I2C5
111: GPIOM
112: GPION
# undefined: slot 113
114: FAN0
# undefined: slot 115
116: GPIOP0
117: GPIOP1
118: GPIOP2
119: GPIOP3
120: GPIOP4
121: GPIOP5
122: GPIOP6
123: GPIOP7
124: GPIOQ0
125: GPIOQ1
126: GPIOQ2
127: GPIOQ3
128: GPIOQ4
129: GPIOQ5
130: GPIOQ6
131: GPIOQ7
# undefined: slot 132 - 133
134: PWM1_0
135: PWM1_1
136: PWM1_2
137: PWM1_3
138: PWM1_FAULT

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LM3S_MEMORYMAP_H
#define LM3S_MEMORYMAP_H
#include <libopencm3/cm3/common.h>
/* --- LM3S specific peripheral definitions ----------------------------- */
#define GPIOA_APB_BASE (0x40004000)
#define GPIOB_APB_BASE (0x40005000)
#define GPIOC_APB_BASE (0x40006000)
#define GPIOD_APB_BASE (0x40007000)
#define GPIOE_APB_BASE (0x40024000)
#define GPIOF_APB_BASE (0x40025000)
#define GPIOG_APB_BASE (0x40026000)
#define GPIOH_APB_BASE (0x40027000)
#define GPIOA_BASE (0x40058000)
#define GPIOB_BASE (0x40059000)
#define GPIOC_BASE (0x4005A000)
#define GPIOD_BASE (0x4005B000)
#define GPIOE_BASE (0x4005C000)
#define GPIOF_BASE (0x4005D000)
#define GPIOG_BASE (0x4005E000)
#define GPIOH_BASE (0x4005F000)
#define SYSTEMCONTROL_BASE (0x400FE000)
#endif

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/** @defgroup systemcontrol_defines System Control
@brief <b>Defined Constants and Types for the LM3S System Control</b>
@ingroup LM3Sxx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2011
Gareth McMullin <gareth@blacksphere.co.nz>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LM3S_SYSTEMCONTROL_H
#define LM3S_SYSTEMCONTROL_H
/**@{*/
#include <libopencm3/cm3/common.h>
#define SYSTEMCONTROL_DID0 MMIO32(SYSTEMCONTROL_BASE + 0x000)
#define SYSTEMCONTROL_DID1 MMIO32(SYSTEMCONTROL_BASE + 0x004)
#define SYSTEMCONTROL_DC0 MMIO32(SYSTEMCONTROL_BASE + 0x008)
#define SYSTEMCONTROL_DC1 MMIO32(SYSTEMCONTROL_BASE + 0x010)
#define SYSTEMCONTROL_DC2 MMIO32(SYSTEMCONTROL_BASE + 0x014)
#define SYSTEMCONTROL_DC3 MMIO32(SYSTEMCONTROL_BASE + 0x018)
#define SYSTEMCONTROL_DC4 MMIO32(SYSTEMCONTROL_BASE + 0x01C)
#define SYSTEMCONTROL_DC5 MMIO32(SYSTEMCONTROL_BASE + 0x020)
#define SYSTEMCONTROL_DC6 MMIO32(SYSTEMCONTROL_BASE + 0x024)
#define SYSTEMCONTROL_DC7 MMIO32(SYSTEMCONTROL_BASE + 0x028)
#define SYSTEMCONTROL_PBORCTL MMIO32(SYSTEMCONTROL_BASE + 0x030)
#define SYSTEMCONTROL_LDORCTL MMIO32(SYSTEMCONTROL_BASE + 0x034)
#define SYSTEMCONTROL_SRCR0 MMIO32(SYSTEMCONTROL_BASE + 0x040)
#define SYSTEMCONTROL_SRCR1 MMIO32(SYSTEMCONTROL_BASE + 0x044)
#define SYSTEMCONTROL_SRCR2 MMIO32(SYSTEMCONTROL_BASE + 0x048)
#define SYSTEMCONTROL_RIS MMIO32(SYSTEMCONTROL_BASE + 0x050)
#define SYSTEMCONTROL_IMC MMIO32(SYSTEMCONTROL_BASE + 0x054)
#define SYSTEMCONTROL_MISC MMIO32(SYSTEMCONTROL_BASE + 0x058)
#define SYSTEMCONTROL_RESC MMIO32(SYSTEMCONTROL_BASE + 0x05C)
#define SYSTEMCONTROL_RCC MMIO32(SYSTEMCONTROL_BASE + 0x060)
#define SYSTEMCONTROL_PLLCFG MMIO32(SYSTEMCONTROL_BASE + 0x064)
#define SYSTEMCONTROL_GPIOHBCTL MMIO32(SYSTEMCONTROL_BASE + 0x06C)
#define SYSTEMCONTROL_RCC2 MMIO32(SYSTEMCONTROL_BASE + 0x070)
#define SYSTEMCONTROL_MOSCCTL MMIO32(SYSTEMCONTROL_BASE + 0x07C)
#define SYSTEMCONTROL_RCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x100)
#define SYSTEMCONTROL_RCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x104)
#define SYSTEMCONTROL_RCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x108)
#define SYSTEMCONTROL_SCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x110)
#define SYSTEMCONTROL_SCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x114)
#define SYSTEMCONTROL_SCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x118)
#define SYSTEMCONTROL_DCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x120)
#define SYSTEMCONTROL_DCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x124)
#define SYSTEMCONTROL_DCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x128)
#define SYSTEMCONTROL_DSLPCLKCFG MMIO32(SYSTEMCONTROL_BASE + 0x144)
/**@}*/
#endif

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/** @mainpage libopencm3 LM4F
@version 1.0.0
@date 22 November 2012
API documentation for TI Stellaris LM4F Cortex M4F series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LM4Fxx LM4F
Libraries for TI Stellaris LM4F series.
@version 1.0.0
@date 22 November 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LM4Fxx_defines LM4F Defines
@brief Defined Constants and Types for the LM4F series
@version 1.0.0
@date 22 November 2012
LGPL License Terms @ref lgpl_license
*/

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/** @defgroup gpio_defines General Purpose I/O Defines
*
* @brief <b>Defined Constants and Types for the LM4F General Purpose I/O</b>
*
* @ingroup LM4Fxx_defines
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2011
* Gareth McMullin <gareth@blacksphere.co.nz>
* @author @htmlonly &copy; @endhtmlonly 2013
* Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* @date 16 March 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LM4F_GPIO_H
#define LM4F_GPIO_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lm4f/memorymap.h>
/* =============================================================================
* Convenience macros
* ---------------------------------------------------------------------------*/
/** @defgroup gpio_reg_base GPIO register base addresses
* @{*/
#define GPIOA GPIOA_BASE
#define GPIOB GPIOB_BASE
#define GPIOC GPIOC_BASE
#define GPIOD GPIOD_BASE
#define GPIOE GPIOE_BASE
#define GPIOF GPIOF_BASE
#define GPIOG GPIOG_BASE
#define GPIOH GPIOH_BASE
#define GPIOJ GPIOJ_BASE
#define GPIOK GPIOK_BASE
#define GPIOL GPIOL_BASE
#define GPIOM GPIOM_BASE
#define GPION GPION_BASE
#define GPIOP GPIOP_BASE
#define GPIOQ GPIOQ_BASE
/** @} */
/* =============================================================================
* GPIO number definitions (for convenience)
*
* These are usable across all GPIO registers,
* except GPIO_LOCK and GPIO_PCTL
* ---------------------------------------------------------------------------*/
/** @defgroup gpio_pin_id GPIO pin identifiers
* @{*/
#define GPIO0 (1 << 0)
#define GPIO1 (1 << 1)
#define GPIO2 (1 << 2)
#define GPIO3 (1 << 3)
#define GPIO4 (1 << 4)
#define GPIO5 (1 << 5)
#define GPIO6 (1 << 6)
#define GPIO7 (1 << 7)
#define GPIO_ALL 0xff
/** @} */
/* =============================================================================
* GPIO registers
* ---------------------------------------------------------------------------*/
/* GPIO Data */
#define GPIO_DATA(port) (&MMIO32(port + 0x000))
/* GPIO Direction */
#define GPIO_DIR(port) MMIO32(port + 0x400)
/* GPIO Interrupt Sense */
#define GPIO_IS(port) MMIO32(port + 0x404)
/* GPIO Interrupt Both Edges */
#define GPIO_IBE(port) MMIO32(port + 0x408)
/* GPIO Interrupt Event */
#define GPIO_IEV(port) MMIO32(port + 0x40c)
/* GPIO Interrupt Mask */
#define GPIO_IM(port) MMIO32(port + 0x410)
/* GPIO Raw Interrupt Status */
#define GPIO_RIS(port) MMIO32(port + 0x414)
/* GPIO Masked Interrupt Status */
#define GPIO_MIS(port) MMIO32(port + 0x418)
/* GPIO Interrupt Clear */
#define GPIO_ICR(port) MMIO32(port + 0x41c)
/* GPIO Alternate Function Select */
#define GPIO_AFSEL(port) MMIO32(port + 0x420)
/* GPIO 2-mA Drive Select */
#define GPIO_DR2R(port) MMIO32(port + 0x500)
/* GPIO 4-mA Drive Select */
#define GPIO_DR4R(port) MMIO32(port + 0x504)
/* GPIO 8-mA Drive Select */
#define GPIO_DR8R(port) MMIO32(port + 0x508)
/* GPIO Open Drain Select */
#define GPIO_ODR(port) MMIO32(port + 0x50c)
/* GPIO Pull-Up Select */
#define GPIO_PUR(port) MMIO32(port + 0x510)
/* GPIO Pull-Down Select */
#define GPIO_PDR(port) MMIO32(port + 0x514)
/* GPIO Slew Rate Control Select */
#define GPIO_SLR(port) MMIO32(port + 0x518)
/* GPIO Digital Enable */
#define GPIO_DEN(port) MMIO32(port + 0x51c)
/* GPIO Lock */
#define GPIO_LOCK(port) MMIO32(port + 0x520)
/* GPIO Commit */
#define GPIO_CR(port) MMIO32(port + 0x524)
/* GPIO Analog Mode Select */
#define GPIO_AMSEL(port) MMIO32(port + 0x528)
/* GPIO Port Control */
#define GPIO_PCTL(port) MMIO32(port + 0x52C)
/* GPIO ADC Control */
#define GPIO_ADCCTL(port) MMIO32(port + 0x530)
/* GPIO DMA Control */
#define GPIO_DMACTL(port) MMIO32(port + 0x534)
/* GPIO Peripheral Identification */
#define GPIO_PERIPH_ID4(port) MMIO32(port + 0xFD0)
#define GPIO_PERIPH_ID5(port) MMIO32(port + 0xFD4)
#define GPIO_PERIPH_ID6(port) MMIO32(port + 0xFD8)
#define GPIO_PERIPH_ID7(port) MMIO32(port + 0xFDC)
#define GPIO_PERIPH_ID0(port) MMIO32(port + 0xFE0)
#define GPIO_PERIPH_ID1(port) MMIO32(port + 0xFE4)
#define GPIO_PERIPH_ID2(port) MMIO32(port + 0xFE8)
#define GPIO_PERIPH_ID3(port) MMIO32(port + 0xFEC)
/* GPIO PrimeCell Identification */
#define GPIO_PCELL_ID0(port) MMIO32(port + 0xFF0)
#define GPIO_PCELL_ID1(port) MMIO32(port + 0xFF4)
#define GPIO_PCELL_ID2(port) MMIO32(port + 0xFF8)
#define GPIO_PCELL_ID3(port) MMIO32(port + 0xFFC)
/* =============================================================================
* Convenience enums
* ---------------------------------------------------------------------------*/
enum gpio_mode {
GPIO_MODE_OUTPUT, /**< Configure pin as output */
GPIO_MODE_INPUT, /**< Configure pin as input */
GPIO_MODE_ANALOG, /**< Configure pin as analog function */
};
enum gpio_pullup {
GPIO_PUPD_NONE, /**< Do not pull the pin high or low */
GPIO_PUPD_PULLUP, /**< Pull the pin high */
GPIO_PUPD_PULLDOWN, /**< Pull the pin low */
};
enum gpio_output_type {
GPIO_OTYPE_PP, /**< Push-pull configuration */
GPIO_OTYPE_OD, /**< Open drain configuration */
};
enum gpio_drive_strength {
GPIO_DRIVE_2MA, /**< 2mA drive */
GPIO_DRIVE_4MA, /**< 4mA drive */
GPIO_DRIVE_8MA, /**< 8mA drive */
GPIO_DRIVE_8MA_SLEW_CTL,/**< 8mA drive with slew rate control */
};
enum gpio_trigger {
GPIO_TRIG_LVL_LOW, /**< Level trigger, signal low */
GPIO_TRIG_LVL_HIGH, /**< Level trigger, signal high */
GPIO_TRIG_EDGE_FALL, /**< Falling edge trigger */
GPIO_TRIG_EDGE_RISE, /**< Rising edge trigger*/
GPIO_TRIG_EDGE_BOTH, /**< Falling and Rising edges trigger*/
};
/* =============================================================================
* Function prototypes
* ---------------------------------------------------------------------------*/
BEGIN_DECLS
void gpio_enable_ahb_aperture(void);
void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode,
enum gpio_pullup pullup, uint8_t gpios);
void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype,
enum gpio_drive_strength drive, uint8_t gpios);
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios);
void gpio_toggle(uint32_t gpioport, uint8_t gpios);
void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios);
/* Let's keep these ones inlined. GPIO control should be fast */
/** @ingroup gpio_control
* @{ */
/**
* \brief Get status of a Group of Pins (atomic)
*
* Reads the level of the given pins. Bit 0 of the returned data corresponds to
* GPIO0 level, bit 1 to GPIO1 level. and so on. Bits corresponding to masked
* pins (corresponding bit of gpios parameter set to zero) are returned as 0.
*
* This is an atomic operation.
*
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
*
* @return The level of the GPIO port. The pins not specified in gpios are
* masked to zero.
*/
static inline uint8_t gpio_read(uint32_t gpioport, uint8_t gpios)
{
return GPIO_DATA(gpioport)[gpios];
}
/**
* \brief Set level of a Group of Pins (atomic)
*
* Sets the level of the given pins. Bit 0 of the data parameter corresponds to
* GPIO0, bit 1 to GPIO1. and so on. Maskedpins (corresponding bit of gpios
* parameter set to zero) are returned not affected.
*
* This is an atomic operation.
*
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
* @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit
* 1 to GPIO1. and so on.
*/
static inline void gpio_write(uint32_t gpioport, uint8_t gpios, uint8_t data)
{
/* ipaddr[9:2] mask the bits to be set, hence the array index */
GPIO_DATA(gpioport)[gpios] = data;
}
/**
* \brief Set a Group of Pins (atomic)
*
* Set one or more pins of the given GPIO port. This is an atomic operation.
*
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
*/
static inline void gpio_set(uint32_t gpioport, uint8_t gpios)
{
gpio_write(gpioport, gpios, 0xff);
}
/**
* \brief Clear a Group of Pins (atomic)
*
* Clear one or more pins of the given GPIO port. This is an atomic operation.
*
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
*/
static inline void gpio_clear(uint32_t gpioport, uint8_t gpios)
{
gpio_write(gpioport, gpios, 0);
}
/**
* \brief Read level of all pins from a port (atomic)
*
* Read the current value of the given GPIO port. This is an atomic operation.
*
* This is functionally identical to @ref gpio_read (gpioport, GPIO_ALL).
*
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
*
* @return The level of all the pins on the GPIO port.
*/
static inline uint8_t gpio_port_read(uint32_t gpioport)
{
return gpio_read(gpioport, GPIO_ALL);
}
/**
* \brief Set level of of all pins from a port (atomic)
*
* Set the level of all pins on the given GPIO port. This is an atomic
* operation.
*
* This is functionally identical to @ref gpio_write (gpioport, GPIO_ALL, data).
*
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
* @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit
* 1 to GPIO1. and so on.
*/
static inline void gpio_port_write(uint32_t gpioport, uint8_t data)
{
gpio_write(gpioport, GPIO_ALL, data);
}
/** @} */
void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger,
uint8_t gpios);
void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios);
void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios);
/* Let's keep these ones inlined. GPIO. They are designed to be used in ISRs */
/** @ingroup gpio_irq
* @{ */
/** \brief Determine if interrupt is generated by the given pin
*
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] srcpins source pin or group of pins to check.
*/
static inline bool gpio_is_interrupt_source(uint32_t gpioport, uint8_t srcpins)
{
return GPIO_MIS(gpioport) & srcpins;
}
/**
* \brief Mark interrupt as serviced
*
* After an interrupt is services, its flag must be cleared. If the flag is not
* cleared, then execution will jump back to the start of the ISR after the ISR
* returns.
*
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
*/
static inline void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios)
{
GPIO_ICR(gpioport) |= gpios;
}
/** @} */
END_DECLS
#endif
/**@}*/

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LM4F_MEMORYMAP_H
#define LM4F_MEMORYMAP_H
#include <libopencm3/cm3/common.h>
/* --- LM4F specific peripheral definitions ----------------------------- */
#define GPIOA_APB_BASE (0x40004000)
#define GPIOB_APB_BASE (0x40005000)
#define GPIOC_APB_BASE (0x40006000)
#define GPIOD_APB_BASE (0x40007000)
#define GPIOE_APB_BASE (0x40024000)
#define GPIOF_APB_BASE (0x40025000)
#define GPIOG_APB_BASE (0x40026000)
#define GPIOH_APB_BASE (0x40027000)
#define GPIOJ_APB_BASE (0x4003D000)
#define GPIOA_BASE (0x40058000)
#define GPIOB_BASE (0x40059000)
#define GPIOC_BASE (0x4005A000)
#define GPIOD_BASE (0x4005B000)
#define GPIOE_BASE (0x4005C000)
#define GPIOF_BASE (0x4005D000)
#define GPIOG_BASE (0x4005E000)
#define GPIOH_BASE (0x4005F000)
#define GPIOJ_BASE (0x40060000)
#define GPIOK_BASE (0x40061000)
#define GPIOL_BASE (0x40062000)
#define GPIOM_BASE (0x40063000)
#define GPION_BASE (0x40064000)
#define GPIOP_BASE (0x40065000)
#define GPIOQ_BASE (0x40066000)
#define UART0_BASE (0x4000C000)
#define UART1_BASE (0x4000D000)
#define UART2_BASE (0x4000E000)
#define UART3_BASE (0x4000F000)
#define UART4_BASE (0x40010000)
#define UART5_BASE (0x40011000)
#define UART6_BASE (0x40012000)
#define UART7_BASE (0x40013000)
#define USB_BASE (0x40050000)
#define SYSCTL_BASE (0x400FE000)
#endif

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/** @defgroup rcc_defines Reset and Clock Control
@brief <b>Defined Constants and Types for the LM4F Reset and Clock Control</b>
@ingroup LM4Fxx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012
Alexandru Gagniuc <mr.nuke.me@gmail.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LM4F_RCC_H
#define LM4F_RCC_H
/**@{*/
#include <libopencm3/lm4f/systemcontrol.h>
/**
* \brief Oscillator source values
*
* Possible values of the oscillator source.
*/
enum osc_src {
OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC,
OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC,
OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4,
OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K,
OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768,
};
/**
* \brief PWM clock divisor values
*
* Possible values of the binary divisor used to predivide the system clock down
* for use as the timing reference for the PWM module.
*/
enum pwm_clkdiv {
PWMDIV_2 = SYSCTL_RCC_PWMDIV_2,
PWMDIV_4 = SYSCTL_RCC_PWMDIV_4,
PWMDIV_8 = SYSCTL_RCC_PWMDIV_8,
PWMDIV_16 = SYSCTL_RCC_PWMDIV_16,
PWMDIV_32 = SYSCTL_RCC_PWMDIV_32,
PWMDIV_64 = SYSCTL_RCC_PWMDIV_64,
};
/**
* \brief Predefined crystal values
*
* Predefined crystal values for the XTAL field in SYSCTL_RCC.
* Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and
* SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock
* of 400MHz.
*/
enum xtal_t {
XTAL_4M = SYSCTL_RCC_XTAL_4M,
XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096,
XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152,
XTAL_5M = SYSCTL_RCC_XTAL_5M,
XTAL_5M_12 = SYSCTL_RCC_XTAL_5M_12,
XTAL_6M = SYSCTL_RCC_XTAL_6M,
XTAL_6M_144 = SYSCTL_RCC_XTAL_6M_144,
XTAL_7M_3728 = SYSCTL_RCC_XTAL_7M_3728,
XTAL_8M = SYSCTL_RCC_XTAL_8M,
XTAL_8M_192 = SYSCTL_RCC_XTAL_8M_192,
XTAL_10M = SYSCTL_RCC_XTAL_10M,
XTAL_12M = SYSCTL_RCC_XTAL_12M,
XTAL_12M_288 = SYSCTL_RCC_XTAL_12M_288,
XTAL_13M_56 = SYSCTL_RCC_XTAL_13M_56,
XTAL_14M_31818 = SYSCTL_RCC_XTAL_14M_31818,
XTAL_16M = SYSCTL_RCC_XTAL_16M,
XTAL_16M_384 = SYSCTL_RCC_XTAL_16M_384,
XTAL_18M = SYSCTL_RCC_XTAL_18M,
XTAL_20M = SYSCTL_RCC_XTAL_20M,
XTAL_24M = SYSCTL_RCC_XTAL_24M,
XTAL_25M = SYSCTL_RCC_XTAL_25M,
};
/* =============================================================================
* Function prototypes
* ---------------------------------------------------------------------------*/
BEGIN_DECLS
/* Low-level clock API */
void rcc_configure_xtal(enum xtal_t xtal);
void rcc_disable_main_osc(void);
void rcc_disable_interal_osc(void);
void rcc_enable_main_osc(void);
void rcc_enable_interal_osc(void);
void rcc_enable_rcc2(void);
void rcc_pll_off(void);
void rcc_pll_on(void);
void rcc_set_osc_source(enum osc_src src);
void rcc_pll_bypass_disable(void);
void rcc_pll_bypass_enable(void);
void rcc_set_pll_divisor(uint8_t div400);
void rcc_set_pwm_divisor(enum pwm_clkdiv div);
void rcc_usb_pll_off(void);
void rcc_usb_pll_on(void);
void rcc_wait_for_pll_ready(void);
/* High-level clock API */
void rcc_change_pll_divisor(uint8_t plldiv400);
uint32_t rcc_get_system_clock_frequency(void);
void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400);
END_DECLS
/**@}*/
#endif /* LM4F_RCC_H */

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/** @defgroup systemcontrol_defines System Control
@brief <b>Defined Constants and Types for the LM4F System Control</b>
@ingroup LM4Fxx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012
Alexandru Gagniuc <mr.nuke.me@gmail.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LM4F_SYSTEMCONTROL_H
#define LM4F_SYSTEMCONTROL_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lm4f/memorymap.h>
#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000)
#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004)
#define SYSCTL_PBORCTL MMIO32(SYSCTL_BASE + 0x030)
#define SYSCTL_LDORCTL MMIO32(SYSCTL_BASE + 0x034)
#define SYSCTL_RIS MMIO32(SYSCTL_BASE + 0x050)
#define SYSCTL_IMC MMIO32(SYSCTL_BASE + 0x054)
#define SYSCTL_MISC MMIO32(SYSCTL_BASE + 0x058)
#define SYSCTL_RESC MMIO32(SYSCTL_BASE + 0x05C)
#define SYSCTL_RCC MMIO32(SYSCTL_BASE + 0x060)
#define SYSCTL_PLLCFG MMIO32(SYSCTL_BASE + 0x064)
#define SYSCTL_GPIOHBCTL MMIO32(SYSCTL_BASE + 0x06C)
#define SYSCTL_RCC2 MMIO32(SYSCTL_BASE + 0x070)
#define SYSCTL_MOSCCTL MMIO32(SYSCTL_BASE + 0x07C)
#define SYSCTL_DSLPCLKCFG MMIO32(SYSCTL_BASE + 0x144)
#define SYSCTL_SYSPROP MMIO32(SYSCTL_BASE + 0x14C)
#define SYSCTL_PIOSCCAL MMIO32(SYSCTL_BASE + 0x150)
#define SYSCTL_PIOSCSTAT MMIO32(SYSCTL_BASE + 0x154)
#define SYSCTL_PLLFREQ0 MMIO32(SYSCTL_BASE + 0x160)
#define SYSCTL_PLLFREQ1 MMIO32(SYSCTL_BASE + 0x164)
#define SYSCTL_PLLSTAT MMIO32(SYSCTL_BASE + 0x168)
/* Peripheral present */
#define SYSCTL_PPWD MMIO32(SYSCTL_BASE + 0x300)
#define SYSCTL_PPTIMER MMIO32(SYSCTL_BASE + 0x304)
#define SYSCTL_PPGPIO MMIO32(SYSCTL_BASE + 0x308)
#define SYSCTL_PPDMA MMIO32(SYSCTL_BASE + 0x30C)
#define SYSCTL_PPHIB MMIO32(SYSCTL_BASE + 0x314)
#define SYSCTL_PPUART MMIO32(SYSCTL_BASE + 0x318)
#define SYSCTL_PPSSI MMIO32(SYSCTL_BASE + 0x31C)
#define SYSCTL_PPI2C MMIO32(SYSCTL_BASE + 0x320)
#define SYSCTL_PPUSB MMIO32(SYSCTL_BASE + 0x328)
#define SYSCTL_PPCAN MMIO32(SYSCTL_BASE + 0x334)
#define SYSCTL_PPADC MMIO32(SYSCTL_BASE + 0x338)
#define SYSCTL_PPACMP MMIO32(SYSCTL_BASE + 0x33C)
#define SYSCTL_PPPWM MMIO32(SYSCTL_BASE + 0x340)
#define SYSCTL_PPQEI MMIO32(SYSCTL_BASE + 0x344)
#define SYSCTL_PPEEPROM MMIO32(SYSCTL_BASE + 0x358)
#define SYSCTL_PPWTIMER MMIO32(SYSCTL_BASE + 0x35C)
/* Peripheral software reset */
#define SYSCTL_SRWD MMIO32(SYSCTL_BASE + 0x500)
#define SYSCTL_SRTIMER MMIO32(SYSCTL_BASE + 0x504)
#define SYSCTL_SRGPIO MMIO32(SYSCTL_BASE + 0x508)
#define SYSCTL_SRDMA MMIO32(SYSCTL_BASE + 0x50C)
#define SYSCTL_SRHIB MMIO32(SYSCTL_BASE + 0x514)
#define SYSCTL_SRUART MMIO32(SYSCTL_BASE + 0x518)
#define SYSCTL_SRSSI MMIO32(SYSCTL_BASE + 0x51C)
#define SYSCTL_SRI2C MMIO32(SYSCTL_BASE + 0x520)
#define SYSCTL_SRUSB MMIO32(SYSCTL_BASE + 0x528)
#define SYSCTL_SRCAN MMIO32(SYSCTL_BASE + 0x534)
#define SYSCTL_SRADC MMIO32(SYSCTL_BASE + 0x538)
#define SYSCTL_SRACMP MMIO32(SYSCTL_BASE + 0x53C)
#define SYSCTL_SRPWM MMIO32(SYSCTL_BASE + 0x540)
#define SYSCTL_SRQEI MMIO32(SYSCTL_BASE + 0x544)
#define SYSCTL_SREEPROM MMIO32(SYSCTL_BASE + 0x558)
#define SYSCTL_SRWTIMER MMIO32(SYSCTL_BASE + 0x55C)
/* Peripheral run mode clock gating control */
#define SYSCTL_RCGCWD MMIO32(SYSCTL_BASE + 0x600)
#define SYSCTL_RCGCTIMER MMIO32(SYSCTL_BASE + 0x604)
#define SYSCTL_RCGCGPIO MMIO32(SYSCTL_BASE + 0x608)
#define SYSCTL_RCGCDMA MMIO32(SYSCTL_BASE + 0x60C)
#define SYSCTL_RCGCHIB MMIO32(SYSCTL_BASE + 0x614)
#define SYSCTL_RCGCUART MMIO32(SYSCTL_BASE + 0x618)
#define SYSCTL_RCGCSSI MMIO32(SYSCTL_BASE + 0x61C)
#define SYSCTL_RCGCI2C MMIO32(SYSCTL_BASE + 0x620)
#define SYSCTL_RCGCUSB MMIO32(SYSCTL_BASE + 0x628)
#define SYSCTL_RCGCCAN MMIO32(SYSCTL_BASE + 0x634)
#define SYSCTL_RCGCADC MMIO32(SYSCTL_BASE + 0x638)
#define SYSCTL_RCGCACMP MMIO32(SYSCTL_BASE + 0x63C)
#define SYSCTL_RCGCPWM MMIO32(SYSCTL_BASE + 0x640)
#define SYSCTL_RCGCQEI MMIO32(SYSCTL_BASE + 0x644)
#define SYSCTL_RCGCEEPROM MMIO32(SYSCTL_BASE + 0x658)
#define SYSCTL_RCGCWTIMER MMIO32(SYSCTL_BASE + 0x65C)
/* Peripheral sleep mode clock gating control */
#define SYSCTL_SCGCWD MMIO32(SYSCTL_BASE + 0x700)
#define SYSCTL_SCGCTIMER MMIO32(SYSCTL_BASE + 0x704)
#define SYSCTL_SCGCGPIO MMIO32(SYSCTL_BASE + 0x708)
#define SYSCTL_SCGCDMA MMIO32(SYSCTL_BASE + 0x70C)
#define SYSCTL_SCGCHIB MMIO32(SYSCTL_BASE + 0x714)
#define SYSCTL_SCGCUART MMIO32(SYSCTL_BASE + 0x718)
#define SYSCTL_SCGCSSI MMIO32(SYSCTL_BASE + 0x71C)
#define SYSCTL_SCGCI2C MMIO32(SYSCTL_BASE + 0x720)
#define SYSCTL_SCGCUSB MMIO32(SYSCTL_BASE + 0x728)
#define SYSCTL_SCGCCAN MMIO32(SYSCTL_BASE + 0x734)
#define SYSCTL_SCGCADC MMIO32(SYSCTL_BASE + 0x738)
#define SYSCTL_SCGCACMP MMIO32(SYSCTL_BASE + 0x73C)
#define SYSCTL_SCGCPWM MMIO32(SYSCTL_BASE + 0x740)
#define SYSCTL_SCGCQEI MMIO32(SYSCTL_BASE + 0x744)
#define SYSCTL_SCGCEEPROM MMIO32(SYSCTL_BASE + 0x758)
#define SYSCTL_SCGCWTIMER MMIO32(SYSCTL_BASE + 0x75C)
/* Peripheral deep-sleep mode clock gating control */
#define SYSCTL_DCGCWD MMIO32(SYSCTL_BASE + 0x800)
#define SYSCTL_DCGCTIMER MMIO32(SYSCTL_BASE + 0x804)
#define SYSCTL_DCGCGPIO MMIO32(SYSCTL_BASE + 0x808)
#define SYSCTL_DCGCDMA MMIO32(SYSCTL_BASE + 0x80C)
#define SYSCTL_DCGCHIB MMIO32(SYSCTL_BASE + 0x814)
#define SYSCTL_DCGCUART MMIO32(SYSCTL_BASE + 0x818)
#define SYSCTL_DCGCSSI MMIO32(SYSCTL_BASE + 0x81C)
#define SYSCTL_DCGCI2C MMIO32(SYSCTL_BASE + 0x820)
#define SYSCTL_DCGCUSB MMIO32(SYSCTL_BASE + 0x828)
#define SYSCTL_DCGCCAN MMIO32(SYSCTL_BASE + 0x834)
#define SYSCTL_DCGCADC MMIO32(SYSCTL_BASE + 0x838)
#define SYSCTL_DCGCACMP MMIO32(SYSCTL_BASE + 0x83C)
#define SYSCTL_DCGCPWM MMIO32(SYSCTL_BASE + 0x840)
#define SYSCTL_DCGCQEI MMIO32(SYSCTL_BASE + 0x844)
#define SYSCTL_DCGCEEPROM MMIO32(SYSCTL_BASE + 0x858)
#define SYSCTL_DCGCWTIMER MMIO32(SYSCTL_BASE + 0x85C)
/* Peripheral ready */
#define SYSCTL_PRWD MMIO32(SYSCTL_BASE + 0xA00)
#define SYSCTL_PRTIMER MMIO32(SYSCTL_BASE + 0xA04)
#define SYSCTL_PRGPIO MMIO32(SYSCTL_BASE + 0xA08)
#define SYSCTL_PRDMA MMIO32(SYSCTL_BASE + 0xA0C)
#define SYSCTL_PRHIB MMIO32(SYSCTL_BASE + 0xA14)
#define SYSCTL_PRUART MMIO32(SYSCTL_BASE + 0xA18)
#define SYSCTL_PRSSI MMIO32(SYSCTL_BASE + 0xA1C)
#define SYSCTL_PRI2C MMIO32(SYSCTL_BASE + 0xA20)
#define SYSCTL_PRUSB MMIO32(SYSCTL_BASE + 0xA28)
#define SYSCTL_PRCAN MMIO32(SYSCTL_BASE + 0xA34)
#define SYSCTL_PRADC MMIO32(SYSCTL_BASE + 0xA38)
#define SYSCTL_PRACMP MMIO32(SYSCTL_BASE + 0xA3C)
#define SYSCTL_PRPWM MMIO32(SYSCTL_BASE + 0xA40)
#define SYSCTL_PRQEI MMIO32(SYSCTL_BASE + 0xA44)
#define SYSCTL_PREEPROM MMIO32(SYSCTL_BASE + 0xA58)
#define SYSCTL_PRWTIMER MMIO32(SYSCTL_BASE + 0xA5C)
/* =============================================================================
* System Control Legacy Registers
* ---------------------------------------------------------------------------*/
#ifdef LM4F_LEGACY_SYSCTL
#define SYSCTL_DC0 MMIO32(SYSCTL_BASE + 0x008)
#define SYSCTL_DC1 MMIO32(SYSCTL_BASE + 0x010)
#define SYSCTL_DC2 MMIO32(SYSCTL_BASE + 0x014)
#define SYSCTL_DC3 MMIO32(SYSCTL_BASE + 0x018)
#define SYSCTL_DC4 MMIO32(SYSCTL_BASE + 0x01C)
#define SYSCTL_DC5 MMIO32(SYSCTL_BASE + 0x020)
#define SYSCTL_DC6 MMIO32(SYSCTL_BASE + 0x024)
#define SYSCTL_DC7 MMIO32(SYSCTL_BASE + 0x028)
#define SYSCTL_DC8 MMIO32(SYSCTL_BASE + 0x02C)
#define SYSCTL_SRCR0 MMIO32(SYSCTL_BASE + 0x040)
#define SYSCTL_SRCR1 MMIO32(SYSCTL_BASE + 0x044)
#define SYSCTL_SRCR2 MMIO32(SYSCTL_BASE + 0x048)
#define SYSCTL_RCGC0 MMIO32(SYSCTL_BASE + 0x100)
#define SYSCTL_RCGC1 MMIO32(SYSCTL_BASE + 0x104)
#define SYSCTL_RCGC2 MMIO32(SYSCTL_BASE + 0x108)
#define SYSCTL_SCGC0 MMIO32(SYSCTL_BASE + 0x110)
#define SYSCTL_SCGC1 MMIO32(SYSCTL_BASE + 0x114)
#define SYSCTL_SCGC2 MMIO32(SYSCTL_BASE + 0x118)
#define SYSCTL_DCGC0 MMIO32(SYSCTL_BASE + 0x120)
#define SYSCTL_DCGC1 MMIO32(SYSCTL_BASE + 0x124)
#define SYSCTL_DCGC2 MMIO32(SYSCTL_BASE + 0x128)
#define SYSCTL_DC9 MMIO32(SYSCTL_BASE + 0x190)
#define SYSCTL_NVMSTAT MMIO32(SYSCTL_BASE + 0x1A0)
#endif /* LM4F_LEGACY_SYSCTL */
/* =============================================================================
* SYSCTL_DID0 values
* ---------------------------------------------------------------------------*/
/** DID0 version */
#define SYSCTL_DID0_VER_MASK (7 << 28)
/** Device class */
#define SYSCTL_DID0_CLASS_MASK (0xFF << 16)
/** Major revision */
#define SYSCTL_DID0_MAJOR_MASK (0xFF << 8)
/** Minor revision */
#define SYSCTL_DID0_MAJOR_MASK (0xFF << 8)
/* =============================================================================
* SYSCTL_DID1 values
* ---------------------------------------------------------------------------*/
/** DID1 version */
#define SYSCTL_DID1_VER_MASK (0xF << 28)
/** Family */
#define SYSCTL_DID1_FAM_MASK (0xF << 24)
/** Part number */
#define SYSCTL_DID1_PARTNO_MASK (0xFF << 16)
/** Pin count */
#define SYSCTL_DID1_PINCOUNT_MASK (0x7 << 13)
#define SYSCTL_DID1_PINCOUNT_28P (0x0 << 13)
#define SYSCTL_DID1_PINCOUNT_48P (0x1 << 13)
#define SYSCTL_DID1_PINCOUNT_100P (0x2 << 13)
#define SYSCTL_DID1_PINCOUNT_64P (0x3 << 13)
#define SYSCTL_DID1_PINCOUNT_144P (0x4 << 13)
#define SYSCTL_DID1_PINCOUNT_157P (0x5 << 13)
/** Temperature range */
#define SYSCTL_DID1_TEMP_MASK (0x7 << 5)
#define SYSCTL_DID1_TEMP_0_70 (0x0 << 5)
#define SYSCTL_DID1_TEMP_M40_85 (0x1 << 5)
#define SYSCTL_DID1_TEMP_M40_105 (0x2 << 5)
/** Package */
#define SYSCTL_DID1_PKG_MASK (0x3 << 5)
#define SYSCTL_DID1_PKG_SOIC (0x0 << 5)
#define SYSCTL_DID1_PKG_LQFP (0x1 << 5)
#define SYSCTL_DID1_PKG_BGA (0x2 << 5)
/** ROHS compliance */
#define SYSCTL_DID1_ROHS (1 << 2)
/** Qualification status */
#define SYSCTL_DID1_QUAL_MASK (3 << 0)
/* =============================================================================
* SYSCTL_PBORCTL values
* ---------------------------------------------------------------------------*/
/** BOR interrupt or reset */
#define SYSCTL_PBORCTL_BORIOR (1 << 1)
/* =============================================================================
* SYSCTL_RIS values
* ---------------------------------------------------------------------------*/
/** MOSC Power Up Raw Interrupt Status */
#define SYSCTL_RIS_MOSCPUPRIS (1 << 8)
/** USB PLL Lock Raw Interrupt Status */
#define SYSCTL_RIS_USBPLLLRIS (1 << 7)
/** PLL Lock Raw Interrupt Status */
#define SYSCTL_RIS_PLLLRIS (1 << 6)
/** Main Oscillator Failure Raw Interrupt Status */
#define SYSCTL_RIS_MOFRIS (1 << 3)
/** Brown-Out Reset Raw Interrupt Status */
#define SYSCTL_RIS_BORRIS (1 << 1)
/* =============================================================================
* SYSCTL_IMC values
* ---------------------------------------------------------------------------*/
/** MOSC Power Up Raw Interrupt Status */
#define SYSCTL_IMC_MOSCPUPIM (1 << 8)
/** USB PLL Lock Raw Interrupt Status */
#define SYSCTL_IMC_USBPLLLIM (1 << 7)
/** PLL Lock Raw Interrupt Status */
#define SYSCTL_IMC_PLLLIM (1 << 6)
/** Main Oscillator Failure Raw Interrupt Status */
#define SYSCTL_IMC_MOFIM (1 << 3)
/** Brown-Out Reset Raw Interrupt Status */
#define SYSCTL_IMC_BORIM (1 << 1)
/* =============================================================================
* SYSCTL_MISC values
* ---------------------------------------------------------------------------*/
/** MOSC Power Up Raw Interrupt Status */
#define SYSCTL_MISC_MOSCPUPMIS (1 << 8)
/** USB PLL Lock Raw Interrupt Status */
#define SYSCTL_MISC_USBPLLLMIS (1 << 7)
/** PLL Lock Raw Interrupt Status */
#define SYSCTL_MISC_PLLLMIS (1 << 6)
/** Main Oscillator Failure Raw Interrupt Status */
#define SYSCTL_MISC_MOFMIS (1 << 3)
/** Brown-Out Reset Raw Interrupt Status */
#define SYSCTL_MISC_BORMIS (1 << 1)
/* =============================================================================
* SYSCTL_RESC values
* ---------------------------------------------------------------------------*/
/** MOSC Failure Reset */
#define SYSCTL_RESC_MOSCFAIL (1 << 18)
/** Watchdog Timer 1 Reset */
#define SYSCTL_RESC_WDT1 (1 << 5)
/** Software Reset */
#define SYSCTL_RESC_SW (1 << 4)
/** Watchdog Timer 0 Reset */
#define SYSCTL_RESC_WDT0 (1 << 3)
/** Brown-Out Reset */
#define SYSCTL_RESC_BOR (1 << 2)
/** Power-On Reset */
#define SYSCTL_RESC_POR (1 << 1)
/** External Reset */
#define SYSCTL_RESC_EXT (1 << 0)
/* =============================================================================
* SYSCTL_RCC values
* ---------------------------------------------------------------------------*/
/** Auto Clock Gating */
#define SYSCTL_RCC_ACG (1 << 27)
/** System Clock Divisor */
#define SYSCTL_RCC_SYSDIV_MASK (0xF << 23)
/** Enable System Clock Divider */
#define SYSCTL_RCC_USESYSDIV (1 << 22)
/** Enable PWM Clock Divisor */
#define SYSCTL_RCC_USEPWMDIV (1 << 20)
/** PWM Unit Clock Divisor */
#define SYSCTL_RCC_PWMDIV_MASK (0xF << 17)
#define SYSCTL_RCC_PWMDIV_2 (0x0 << 17)
#define SYSCTL_RCC_PWMDIV_4 (0x1 << 17)
#define SYSCTL_RCC_PWMDIV_8 (0x2 << 17)
#define SYSCTL_RCC_PWMDIV_16 (0x3 << 17)
#define SYSCTL_RCC_PWMDIV_32 (0x4 << 17)
#define SYSCTL_RCC_PWMDIV_64 (0x5 << 17)
/** PLL Power Down */
#define SYSCTL_RCC_PWRDN (1 << 13)
/** PLL Bypass */
#define SYSCTL_RCC_BYPASS (1 << 11)
/** Crystal Value */
#define SYSCTL_RCC_XTAL_MASK (0x1F << 6)
#define SYSCTL_RCC_XTAL_4M (0x06 << 6)
#define SYSCTL_RCC_XTAL_4M_096 (0x07 << 6)
#define SYSCTL_RCC_XTAL_4M_9152 (0x08 << 6)
#define SYSCTL_RCC_XTAL_5M (0x09 << 6)
#define SYSCTL_RCC_XTAL_5M_12 (0x0A << 6)
#define SYSCTL_RCC_XTAL_6M (0x0B << 6)
#define SYSCTL_RCC_XTAL_6M_144 (0x0C << 6)
#define SYSCTL_RCC_XTAL_7M_3728 (0x0D << 6)
#define SYSCTL_RCC_XTAL_8M (0x0E << 6)
#define SYSCTL_RCC_XTAL_8M_192 (0x0F << 6)
#define SYSCTL_RCC_XTAL_10M (0x10 << 6)
#define SYSCTL_RCC_XTAL_12M (0x11 << 6)
#define SYSCTL_RCC_XTAL_12M_288 (0x12 << 6)
#define SYSCTL_RCC_XTAL_13M_56 (0x13 << 6)
#define SYSCTL_RCC_XTAL_14M_31818 (0x14 << 6)
#define SYSCTL_RCC_XTAL_16M (0x15 << 6)
#define SYSCTL_RCC_XTAL_16M_384 (0x16 << 6)
#define SYSCTL_RCC_XTAL_18M (0x17 << 6)
#define SYSCTL_RCC_XTAL_20M (0x18 << 6)
#define SYSCTL_RCC_XTAL_24M (0x19 << 6)
#define SYSCTL_RCC_XTAL_25M (0x1A << 6)
/** Oscillator Source */
#define SYSCTL_RCC_OSCSRC_MASK (0x3 << 4)
#define SYSCTL_RCC_OSCSRC_MOSC (0x0 << 4)
#define SYSCTL_RCC_OSCSRC_PIOSC (0x1 << 4)
#define SYSCTL_RCC_OSCSRC_PIOSC_D4 (0x2 << 4)
#define SYSCTL_RCC_OSCSRC_30K (0x3 << 4)
/** Precision Internal Oscillator Disable */
#define SYSCTL_RCC_IOSCDIS (1 << 1)
/** Main Oscillator Disable */
#define SYSCTL_RCC_MOSCDIS (1 << 0)
/* =============================================================================
* SYSCTL_GPIOHBCTL values
* ---------------------------------------------------------------------------*/
#define SYSCTL_GPIOHBCTL_PORTQ (1 << 14)
#define SYSCTL_GPIOHBCTL_PORTP (1 << 13)
#define SYSCTL_GPIOHBCTL_PORTN (1 << 12)
#define SYSCTL_GPIOHBCTL_PORTM (1 << 11)
#define SYSCTL_GPIOHBCTL_PORTL (1 << 10)
#define SYSCTL_GPIOHBCTL_PORTK (1 << 9)
#define SYSCTL_GPIOHBCTL_PORTJ (1 << 8)
#define SYSCTL_GPIOHBCTL_PORTH (1 << 7)
#define SYSCTL_GPIOHBCTL_PORTG (1 << 6)
#define SYSCTL_GPIOHBCTL_PORTF (1 << 5)
#define SYSCTL_GPIOHBCTL_PORTE (1 << 4)
#define SYSCTL_GPIOHBCTL_PORTD (1 << 3)
#define SYSCTL_GPIOHBCTL_PORTC (1 << 2)
#define SYSCTL_GPIOHBCTL_PORTB (1 << 1)
#define SYSCTL_GPIOHBCTL_PORTA (1 << 0)
/* =============================================================================
* SYSCTL_RCC2 values
* ---------------------------------------------------------------------------*/
/** RCC2 overides RCC */
#define SYSCTL_RCC2_USERCC2 (1 << 31)
/** Divide PLL as 400 MHz vs. 200 MHz */
#define SYSCTL_RCC2_DIV400 (1 << 30)
/** Auto Clock Gating */
#define SYSCTL_RCC2_ACG (1 << 27)
/** System Clock Divisor 2 */
#define SYSCTL_RCC2_SYSDIV2_MASK (0x3F << 23)
/** Additional LSB for SYSDIV2 */
#define SYSCTL_RCC2_SYSDIV2LSB (1 << 22)
/** System clock divisor mask when RCC2_DIV400 is set */
#define SYSCTL_RCC2_SYSDIV400_MASK (0x7F << 22)
/** Power-Down USB PLL */
#define SYSCTL_RCC2_USBPWRDN (1 << 14)
/** PLL Power Down 2 */
#define SYSCTL_RCC2_PWRDN2 (1 << 13)
/** PLL Bypass 2 */
#define SYSCTL_RCC2_BYPASS2 (1 << 11)
/** Oscillator Source 2 */
#define SYSCTL_RCC2_OSCSRC2_MASK (0x7 << 4)
#define SYSCTL_RCC2_OSCSRC2_MOSC (0x0 << 4)
#define SYSCTL_RCC2_OSCSRC2_PIOSC (0x1 << 4)
#define SYSCTL_RCC2_OSCSRC2_PIOSC_D4 (0x2 << 4)
#define SYSCTL_RCC2_OSCSRC2_30K (0x3 << 4)
#define SYSCTL_RCC2_OSCSRC2_32K768 (0x7 << 4)
/* =============================================================================
* SYSCTL_MOSCCTL values
* ---------------------------------------------------------------------------*/
/** No Crystal Connected */
#define SYSCTL_MOSCCTL_NOXTAL (1 << 2)
/** MOSC Failure Action */
#define SYSCTL_MOSCCTL_MOSCIM (1 << 1)
/** Clock Validation for MOSC */
#define SYSCTL_MOSCCTL_CVAL (1 << 0)
/* =============================================================================
* SYSCTL_DSLPCLKCFG values
* ---------------------------------------------------------------------------*/
/*TODO*/
/* =============================================================================
* SYSCTL_SYSPROP values
* ---------------------------------------------------------------------------*/
/** FPU present */
#define SYSCTL_SYSPROP_FPU (1 << 0)
/* =============================================================================
* SYSCTL_PIOSCCAL values
* ---------------------------------------------------------------------------*/
/** Use User Trim Value */
#define SYSCTL_PIOSCCAL_UTEN (1 << 31)
/** Start calibration */
#define SYSCTL_PIOSCCAL_CAL (1 << 9)
/** Update trim */
#define SYSCTL_PIOSCCAL_UPDATE (1 << 8)
/** User Trim Value */
#define SYSCTL_PIOSCCAL_UT_MASK (0x7F << 0)
/* =============================================================================
* SYSCTL_PIOSCSTAT values
* ---------------------------------------------------------------------------*/
/** Default Trim Value */
#define SYSCTL_PIOSCSTAT_DT_MASK (0x7F << 16)
/** Calibration result */
#define SYSCTL_PIOSCSTAT_RESULT_MASK (0x3 << 8)
/** Calibration Trim Value */
#define SYSCTL_PIOSCSTAT_CT_MASK (0x7F << 0)
/* =============================================================================
* SYSCTL_PLLFREQ0 values
* ---------------------------------------------------------------------------*/
/** PLL M fractional value */
#define SYSCTL_PLLFREQ0_MFRAC_MASK (0x3FF << 10)
/** PLL M integer value */
#define SYSCTL_PLLFREQ0_MINT_MASK (0x3FF << 0)
/* =============================================================================
* SYSCTL_PLLFREQ1 values
* ---------------------------------------------------------------------------*/
/** PLL Q value */
#define SYSCTL_PLLFREQ1_Q_MASK (0x1F << 8)
/** PLL N value */
#define SYSCTL_PLLFREQ1_N_MASK (0x1F << 0)
/* =============================================================================
* SYSCTL_PLLSTAT values
* ---------------------------------------------------------------------------*/
/** PLL lock */
#define SYSCTL_PLLSTAT_LOCK (1 << 0)
/* =============================================================================
* Convenience definitions for a readable API
* ---------------------------------------------------------------------------*/
/**
* \brief Clock enable definitions
*
* The definitions are specified in the form
* 31:5 register offset from SYSCTL_BASE for the clock register
* 4:0 bit offset for the given peripheral
*
* The names have the form [clock_type]_[periph_type]_[periph_number]
* Where clock_type is
* RCC for run clock
* SCC for sleep clock
* DCC for deep-sleep clock
*/
enum lm4f_clken {
/*
* Run clock control
*/
RCC_WD0 = ((uint32_t)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5,
RCC_WD1,
RCC_TIMER0 = ((uint32_t)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5,
RCC_TIMER1,
RCC_TIMER2,
RCC_TIMER3,
RCC_TIMER4,
RCC_TIMER5,
RCC_GPIOA = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
RCC_GPIOB,
RCC_GPIOC,
RCC_GPIOD,
RCC_GPIOE,
RCC_GPIOF,
RCC_GPIOG,
RCC_GPIOH,
RCC_GPIOJ,
RCC_GPIOK,
RCC_GPIOL,
RCC_GPIOM,
RCC_GPION,
RCC_GPIOP,
RCC_GPIOQ,
RCC_DMA = ((uint32_t)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5,
RCC_HIB = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
RCC_UART0 = ((uint32_t)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5,
RCC_UART1,
RCC_UART2,
RCC_UART3,
RCC_UART4,
RCC_UART5,
RCC_UART6,
RCC_UART7,
RCC_SSI0 = ((uint32_t)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5,
RCC_SSI1,
RCC_SSI2,
RCC_SSI3,
RCC_I2C0 = ((uint32_t)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5,
RCC_I2C1,
RCC_I2C2,
RCC_I2C3,
RCC_I2C4,
RCC_I2C5,
RCC_USB0 = ((uint32_t)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5,
RCC_CAN0 = ((uint32_t)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5,
RCC_CAN1,
RCC_ADC0 = ((uint32_t)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5,
RCC_ADC1,
RCC_ACMP0 = ((uint32_t)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5,
RCC_PWM0 = ((uint32_t)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5,
RCC_PWM1,
RCC_QEI0 = ((uint32_t)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5,
RCC_QEI1,
RCC_EEPROM0 = ((uint32_t)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5,
RCC_WTIMER0 = ((uint32_t)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5,
RCC_WTIMER1,
RCC_WTIMER2,
RCC_WTIMER3,
RCC_WTIMER4,
RCC_WTIMER5,
/*
* Sleep clock control
*/
SCC_WD0 = ((uint32_t)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5,
SCC_WD1,
SCC_TIMER0 = ((uint32_t)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5,
SCC_TIMER1,
SCC_TIMER2,
SCC_TIMER3,
SCC_TIMER4,
SCC_TIMER5,
SCC_GPIOA = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
SCC_GPIOB,
SCC_GPIOC,
SCC_GPIOD,
SCC_GPIOE,
SCC_GPIOF,
SCC_GPIOG,
SCC_GPIOH,
SCC_GPIOJ,
SCC_GPIOK,
SCC_GPIOL,
SCC_GPIOM,
SCC_GPION,
SCC_GPIOP,
SCC_GPIOQ,
SCC_DMA = ((uint32_t)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5,
SCC_HIB = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
SCC_UART0 = ((uint32_t)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5,
SCC_UART1,
SCC_UART2,
SCC_UART3,
SCC_UART4,
SCC_UART5,
SCC_UART6,
SCC_UART7,
SCC_SSI0 = ((uint32_t)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5,
SCC_SSI1,
SCC_SSI2,
SCC_SSI3,
SCC_I2C0 = ((uint32_t)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5,
SCC_I2C1,
SCC_I2C2,
SCC_I2C3,
SCC_I2C4,
SCC_I2C5,
SCC_USB0 = ((uint32_t)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5,
SCC_CAN0 = ((uint32_t)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5,
SCC_CAN1,
SCC_ADC0 = ((uint32_t)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5,
SCC_ADC1,
SCC_ACMP0 = ((uint32_t)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5,
SCC_PWM0 = ((uint32_t)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5,
SCC_PWM1,
SCC_QEI0 = ((uint32_t)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5,
SCC_QEI1,
SCC_EEPROM0 = ((uint32_t)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5,
SCC_WTIMER0 = ((uint32_t)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5,
SCC_WTIMER1,
SCC_WTIMER2,
SCC_WTIMER3,
SCC_WTIMER4,
SCC_WTIMER5,
/*
* Deep-sleep clock control
*/
DCC_WD0 = ((uint32_t)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5,
DCC_WD1,
DCC_TIMER0 = ((uint32_t)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5,
DCC_TIMER1,
DCC_TIMER2,
DCC_TIMER3,
DCC_TIMER4,
DCC_TIMER5,
DCC_GPIOA = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
DCC_GPIOB,
DCC_GPIOC,
DCC_GPIOD,
DCC_GPIOE,
DCC_GPIOF,
DCC_GPIOG,
DCC_GPIOH,
DCC_GPIOJ,
DCC_GPIOK,
DCC_GPIOL,
DCC_GPIOM,
DCC_GPION,
DCC_GPIOP,
DCC_GPIOQ,
DCC_DMA = ((uint32_t)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5,
DCC_HIB = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
DCC_UART0 = ((uint32_t)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5,
DCC_UART1,
DCC_UART2,
DCC_UART3,
DCC_UART4,
DCC_UART5,
DCC_UART6,
DCC_UART7,
DCC_SSI0 = ((uint32_t)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5,
DCC_SSI1,
DCC_SSI2,
DCC_SSI3,
DCC_I2C0 = ((uint32_t)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5,
DCC_I2C1,
DCC_I2C2,
DCC_I2C3,
DCC_I2C4,
DCC_I2C5,
DCC_USB0 = ((uint32_t)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5,
DCC_CAN0 = ((uint32_t)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5,
DCC_CAN1,
DCC_ADC0 = ((uint32_t)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5,
DCC_ADC1,
DCC_ACMP0 = ((uint32_t)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5,
DCC_PWM0 = ((uint32_t)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5,
DCC_PWM1,
DCC_QEI0 = ((uint32_t)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5,
DCC_QEI1,
DCC_EEPROM0 = ((uint32_t)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5,
DCC_WTIMER0 = ((uint32_t)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5,
DCC_WTIMER1,
DCC_WTIMER2,
DCC_WTIMER3,
DCC_WTIMER4,
DCC_WTIMER5,
};
/* ============================================================================
* Function prototypes
* --------------------------------------------------------------------------*/
BEGIN_DECLS
void periph_clock_enable(enum lm4f_clken periph);
void periph_clock_disable(enum lm4f_clken periph);
END_DECLS
/**@}*/
#endif /* LM4F_SYSTEMCONTROL_H */

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/** @defgroup uart_defines UART Control
*
* @brief <b>Defined Constants and Types for the LM4F UART Control</b>
*
* @ingroup LM4Fxx_defines
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2013
* Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* @date 07 May 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_LM4F_UART_H
#define LIBOPENCM3_LM4F_UART_H
/**@{*/
#include <libopencm3/lm4f/memorymap.h>
#include <libopencm3/cm3/common.h>
/* =============================================================================
* Convenience macros
* ---------------------------------------------------------------------------*/
/** @defgroup uart_reg_base UART register base addresses
* @{*/
#define UART0 UART0_BASE
#define UART1 UART1_BASE
#define UART2 UART2_BASE
#define UART3 UART3_BASE
#define UART4 UART4_BASE
#define UART5 UART5_BASE
#define UART6 UART6_BASE
#define UART7 UART7_BASE
/** @} */
/* =============================================================================
* UART registers
* ---------------------------------------------------------------------------*/
/* UART data register */
#define UART_DR(uart_base) MMIO32(uart_base + 0x00)
/* UART Receive Status/Error Clear register */
#define UART_RSR(uart_base) MMIO32(uart_base + 0x04)
#define UART_ECR(uart_base) MMIO32(uart_base + 0x04)
/* UART Flag register */
#define UART_FR(uart_base) MMIO32(uart_base + 0x18)
/* UART IrDA Low-Power register */
#define UART_ILPR(uart_base) MMIO32(uart_base + 0x20)
/* UART Integer baudrate divisor */
#define UART_IBRD(uart_base) MMIO32(uart_base + 0x24)
/* UART Fractional baudrate divisor */
#define UART_FBRD(uart_base) MMIO32(uart_base + 0x28)
/* UART Line control */
#define UART_LCRH(uart_base) MMIO32(uart_base + 0x2C)
/* UART Control */
#define UART_CTL(uart_base) MMIO32(uart_base + 0x30)
/* UART Interrupt FIFO level select */
#define UART_IFLS(uart_base) MMIO32(uart_base + 0x34)
/* UART Interrupt mask */
#define UART_IM(uart_base) MMIO32(uart_base + 0x38)
/* UART Raw interrupt status */
#define UART_RIS(uart_base) MMIO32(uart_base + 0x3C)
/* UART Masked Interrupt status */
#define UART_MIS(uart_base) MMIO32(uart_base + 0x40)
/* UART Interrupt Clear */
#define UART_ICR(uart_base) MMIO32(uart_base + 0x44)
/* UART DMA control */
#define UART_DMACTL(uart_base) MMIO32(uart_base + 0x48)
/* UART LIN control */
#define UART_LCTL(uart_base) MMIO32(uart_base + 0x90)
/* UART LIN snap shot */
#define UART_LSS(uart_base) MMIO32(uart_base + 0x94)
/* UART LIN timer */
#define UART_LTIM(uart_base) MMIO32(uart_base + 0x98)
/* UART 9-Bit self address */
#define UART_9BITADDR(uart_base) MMIO32(uart_base + 0xA4)
/* UART 9-Bit self address mask */
#define UART_9BITAMASK(uart_base) MMIO32(uart_base + 0xA8)
/* UART Peripheral properties */
#define UART_PP(uart_base) MMIO32(uart_base + 0xFC0)
/* UART Clock configuration */
#define UART_CC(uart_base) MMIO32(uart_base + 0xFC8)
/* UART Peripheral Identification 4 */
#define UART_PERIPH_ID4(uart_base) MMIO32(uart_base + 0xFD0)
/* UART Peripheral Identification 5 */
#define UART_PERIPH_ID5(uart_base) MMIO32(uart_base + 0xFD4)
/* UART Peripheral Identification 6 */
#define UART_PERIPH_ID6(uart_base) MMIO32(uart_base + 0xFD8)
/* UART Peripheral Identification 7 */
#define UART_PERIPH_ID7(uart_base) MMIO32(uart_base + 0xFDC)
/* UART Peripheral Identification 0 */
#define UART_PERIPH_ID0(uart_base) MMIO32(uart_base + 0xFE0)
/* UART Peripheral Identification 1 */
#define UART_PERIPH_ID1(uart_base) MMIO32(uart_base + 0xFE4)
/* UART Peripheral Identification 2 */
#define UART_PERIPH_ID2(uart_base) MMIO32(uart_base + 0xFE8)
/* UART Peripheral Identification 3 */
#define UART_PERIPH_ID3(uart_base) MMIO32(uart_base + 0xFEC)
/* UART PrimeCell Identification 0 */
#define UART_PCELL_ID0(uart_base) MMIO32(uart_base + 0xFF0)
/* UART PrimeCell Identification 1 */
#define UART_PCELL_ID1(uart_base) MMIO32(uart_base + 0xFF4)
/* UART PrimeCell Identification 2 */
#define UART_PCELL_ID2(uart_base) MMIO32(uart_base + 0xFF8)
/* UART PrimeCell Identification 3 */
#define UART_PCELL_ID3(uart_base) MMIO32(uart_base + 0xFFC)
/* =============================================================================
* UART_DR values
* ---------------------------------------------------------------------------*/
/** Overrun Error */
#define UART_DR_OE (1 << 11)
/** Break Error */
#define UART_DR_BE (1 << 10)
/** Parity Error */
#define UART_DR_PE (1 << 9)
/** Framing Error */
#define UART_DR_FE (1 << 8)
/** Data transmitted or received */
#define UART_DR_DATA_MASK (0xFF << 0)
/* =============================================================================
* Readonly UART_RSR values
* ---------------------------------------------------------------------------*/
/** Overrun Error */
#define UART_RSR_OE (1 << 3)
/** Break Error */
#define UART_RSR_BE (1 << 2)
/** Parity Error */
#define UART_RSR_PE (1 << 1)
/** Framing Error */
#define UART_RSR_FE (1 << 0)
/* =============================================================================
* UART_FR values
* ---------------------------------------------------------------------------*/
/** Tx FIFO empty */
#define UART_FR_TXFE (1 << 7)
/** Rx FIFO full */
#define UART_FR_RXFF (1 << 6)
/** Tx FIFO full */
#define UART_FR_TXFF (1 << 5)
/** Rx FIFO empty */
#define UART_FR_RXFE (1 << 4)
/** UART Busy */
#define UART_FR_BUSY (1 << 3)
/** Clear To Send */
#define UART_FR_CTS (1 << 0)
/* =============================================================================
* UART_LCRH values
* ---------------------------------------------------------------------------*/
/** Stick parity select */
#define UART_LCRH_SPS (1 << 7)
/** Word length */
#define UART_LCRH_WLEN_MASK (3 << 5)
#define UART_LCRH_WLEN_5 (0 << 5)
#define UART_LCRH_WLEN_6 (1 << 5)
#define UART_LCRH_WLEN_7 (2 << 5)
#define UART_LCRH_WLEN_8 (3 << 5)
/** Enable FIFOs */
#define UART_LCRH_FEN (1 << 4)
/** Two stop bits select */
#define UART_LCRH_STP2 (1 << 3)
/** Even parity select */
#define UART_LCRH_EPS (1 << 2)
/** Parity enable */
#define UART_LCRH_PEN (1 << 1)
/** Send break */
#define UART_LCRH_BRK (1 << 0)
/* =============================================================================
* UART_CTL values
* ---------------------------------------------------------------------------*/
/** Enable Clear To Send */
#define UART_CTL_CTSEN (1 << 15)
/** Enable Request To Send */
#define UART_CTL_RTSEN (1 << 14)
/** Request To Send */
#define UART_CTL_RTS (1 << 11)
/** Data terminal ready */
#define UART_CTL_DTR (1 << 10)
/** Rx Enable */
#define UART_CTL_RXE (1 << 9)
/** Tx Enable */
#define UART_CTL_TXE (1 << 8)
/** Loop back enable */
#define UART_CTL_LBE (1 << 7)
/** LIN mode enable */
#define UART_CTL_LIN (1 << 6)
/** High speed Enable */
#define UART_CTL_HSE (1 << 5)
/** End of transmission */
#define UART_CTL_EOT (1 << 4)
/** ISO 7816 Smart Card support */
#define UART_CTL_SMART (1 << 3)
/** SIR low-power mode */
#define UART_CTL_SIRLIP (1 << 2)
/** SIR enable */
#define UART_CTL_SIREN (1 << 1)
/** UART enable */
#define UART_CTL_UARTEN (1 << 0)
/* =============================================================================
* UART_IFLS values
* ---------------------------------------------------------------------------*/
/** UART Rx interrupt FIFO level select */
#define UART_IFLS_RXIFLSEL_MASK (7 << 3)
#define UART_IFLS_RXIFLSEL_1_8 (0 << 3)
#define UART_IFLS_RXIFLSEL_1_4 (1 << 3)
#define UART_IFLS_RXIFLSEL_1_2 (2 << 3)
#define UART_IFLS_RXIFLSEL_3_4 (3 << 3)
#define UART_IFLS_RXIFLSEL_7_8 (4 << 3)
/** UART Tx interrupt FIFO level select */
#define UART_IFLS_TXIFLSEL_MASK (7 << 0)
#define UART_IFLS_TXIFLSEL_7_8 (0 << 0)
#define UART_IFLS_TXIFLSEL_3_4 (1 << 0)
#define UART_IFLS_TXIFLSEL_1_2 (2 << 0)
#define UART_IFLS_TXIFLSEL_1_4 (3 << 0)
#define UART_IFLS_TXIFLSEL_1_8 (4 << 0)
/* =============================================================================
* UART interrupt mask values
*
* These are interchangeable across UART_IM, UART_RIS, UART_MIS, and UART_ICR
* registers.
* ---------------------------------------------------------------------------*/
/** LIN mode edge 5 interrupt mask */
#define UART_IM_LME5IM (1 << 15)
/** LIN mode edge 1 interrupt mask */
#define UART_IM_LME1IM (1 << 14)
/** LIN mode sync break interrupt mask */
#define UART_IM_LMSBIM (1 << 13)
/** 9-bit mode interrupt mask */
#define UART_IM_9BITIM (1 << 12)
/** Overrun error interrupt mask */
#define UART_IM_OEIM (1 << 10)
/** Break error interrupt mask */
#define UART_IM_BEIM (1 << 9)
/** Parity error interrupt mask */
#define UART_IM_PEIM (1 << 8)
/** Framing error interrupt mask */
#define UART_IM_FEIM (1 << 7)
/** Receive time-out interrupt mask */
#define UART_IM_RTIM (1 << 6)
/** Transmit interrupt mask */
#define UART_IM_TXIM (1 << 5)
/** Receive interrupt mask */
#define UART_IM_RXIM (1 << 4)
/** Data Set Ready modem interrupt mask */
#define UART_IM_DSRIM (1 << 3)
/** Data Carrier Detect modem interrupt mask */
#define UART_IM_DCDIM (1 << 2)
/** Clear To Send modem interrupt mask */
#define UART_IM_CTSIM (1 << 1)
/** Ring Indicator modem interrupt mask */
#define UART_IM_RIIM (1 << 0)
/* =============================================================================
* UART_DMACTL values
* ---------------------------------------------------------------------------*/
/** DMA on error */
#define UART_DMACTL_DMAERR (1 << 2)
/** Transmit DMA enable */
#define UART_DMACTL_TXDMAE (1 << 1)
/** Recieve DMA enable */
#define UART_DMACTL_RXDMAE (1 << 0)
/* =============================================================================
* UART_LCTL values
* ---------------------------------------------------------------------------*/
/** Sync break length */
#define UART_LCTL_BLEN_MASK (3 << 4)
#define UART_LCTL_BLEN_16T (3 << 4)
#define UART_LCTL_BLEN_15T (2 << 4)
#define UART_LCTL_BLEN_14T (1 << 4)
#define UART_LCTL_BLEN_13T (0 << 4)
/** LIN master enable */
#define UART_LCTL_MASTER (1 << 0)
/* =============================================================================
* UART_9BITADDR values
* ---------------------------------------------------------------------------*/
/** Enable 9-bit mode */
#define UART_UART_9BITADDR_9BITEN (1 << 15)
/** Self-address for 9-bit mode */
#define UART_UART_9BITADDR_ADDR_MASK (0xFF << 0)
/* =============================================================================
* UART_PP values
* ---------------------------------------------------------------------------*/
/** 9-bit support */
#define UART_UART_PP_NB (1 << 1)
/** Smart Card support */
#define UART_UART_PP_SC (1 << 0)
/* =============================================================================
* UART_CC values
* ---------------------------------------------------------------------------*/
/** UART baud clock source */
#define UART_CC_CS_MASK (0xF << 0)
#define UART_CC_CS_SYSCLK (0x0 << 0)
#define UART_CC_CS_PIOSC (0x5 << 0)
/* =============================================================================
* Convenience enums
* ---------------------------------------------------------------------------*/
enum uart_parity {
UART_PARITY_NONE,
UART_PARITY_ODD,
UART_PARITY_EVEN,
UART_PARITY_STICK_0,
UART_PARITY_STICK_1,
};
enum uart_flowctl {
UART_FLOWCTL_NONE,
UART_FLOWCTL_RTS,
UART_FLOWCTL_CTS,
UART_FLOWCTL_RTS_CTS,
};
/**
* \brief UART interrupt masks
*
* These masks can be OR'ed together to specify more than one interrupt. For
* example, (UART_INT_TXIM | UART_INT_TXIM) specifies both Rx and Tx Interrupt.
*/
enum uart_interrupt_flag {
UART_INT_LME5 = UART_IM_LME5IM,
UART_INT_LME1 = UART_IM_LME1IM,
UART_INT_LMSB = UART_IM_LMSBIM,
UART_INT_9BIT = UART_IM_9BITIM,
UART_INT_OE = UART_IM_OEIM,
UART_INT_BE = UART_IM_BEIM,
UART_INT_PE = UART_IM_PEIM,
UART_INT_FE = UART_IM_FEIM,
UART_INT_RT = UART_IM_RTIM,
UART_INT_TX = UART_IM_TXIM,
UART_INT_RX = UART_IM_RXIM,
UART_INT_DSR = UART_IM_DSRIM,
UART_INT_DCD = UART_IM_DCDIM,
UART_INT_CTS = UART_IM_CTSIM,
UART_INT_RI = UART_IM_RIIM,
};
/**
* \brief UART RX FIFO interrupt trigger levels
*
* The levels indicate how full the FIFO should be before an interrupt is
* generated. UART_FIFO_RX_TRIG_3_4 means that an interrupt is triggered when
* the FIFO is 3/4 full. As the FIFO is 8 elements deep, 1/8 is equal to being
* triggered by a single character.
*/
enum uart_fifo_rx_trigger_level {
UART_FIFO_RX_TRIG_1_8 = UART_IFLS_RXIFLSEL_1_8,
UART_FIFO_RX_TRIG_1_4 = UART_IFLS_RXIFLSEL_1_4,
UART_FIFO_RX_TRIG_1_2 = UART_IFLS_RXIFLSEL_1_2,
UART_FIFO_RX_TRIG_3_4 = UART_IFLS_RXIFLSEL_3_4,
UART_FIFO_RX_TRIG_7_8 = UART_IFLS_RXIFLSEL_7_8
};
/**
* \brief UART TX FIFO interrupt trigger levels
*
* The levels indicate how empty the FIFO should be before an interrupt is
* generated. Note that this indicates the emptiness of the FIFO and not the
* fullness. This is somewhat confusing, but it follows the wording of the
* LM4F120H5QR datasheet.
*
* UART_FIFO_TX_TRIG_3_4 means that an interrupt is triggered when the FIFO is
* 3/4 empty. As the FIFO is 8 elements deep, 7/8 is equal to being triggered
* by a single character.
*/
enum uart_fifo_tx_trigger_level {
UART_FIFO_TX_TRIG_7_8 = UART_IFLS_TXIFLSEL_7_8,
UART_FIFO_TX_TRIG_3_4 = UART_IFLS_TXIFLSEL_3_4,
UART_FIFO_TX_TRIG_1_2 = UART_IFLS_TXIFLSEL_1_2,
UART_FIFO_TX_TRIG_1_4 = UART_IFLS_TXIFLSEL_1_4,
UART_FIFO_TX_TRIG_1_8 = UART_IFLS_TXIFLSEL_1_8
};
/* =============================================================================
* Function prototypes
* ---------------------------------------------------------------------------*/
BEGIN_DECLS
void uart_set_baudrate(uint32_t uart, uint32_t baud);
void uart_set_databits(uint32_t uart, uint8_t databits);
void uart_set_stopbits(uint32_t uart, uint8_t stopbits);
void uart_set_parity(uint32_t uart, enum uart_parity parity);
void uart_set_mode(uint32_t uart, uint32_t mode);
void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow);
void uart_enable(uint32_t uart);
void uart_disable(uint32_t uart);
void uart_clock_from_piosc(uint32_t uart);
void uart_clock_from_sysclk(uint32_t uart);
void uart_send(uint32_t uart, uint16_t data);
uint16_t uart_recv(uint32_t uart);
void uart_wait_send_ready(uint32_t uart);
void uart_wait_recv_ready(uint32_t uart);
void uart_send_blocking(uint32_t uart, uint16_t data);
uint16_t uart_recv_blocking(uint32_t uart);
void uart_enable_rx_dma(uint32_t uart);
void uart_disable_rx_dma(uint32_t uart);
void uart_enable_tx_dma(uint32_t uart);
void uart_disable_tx_dma(uint32_t uart);
void uart_enable_fifo(uint32_t uart);
void uart_disable_fifo(uint32_t uart);
void uart_set_fifo_trigger_levels(uint32_t uart,
enum uart_fifo_rx_trigger_level rx_level,
enum uart_fifo_tx_trigger_level tx_level);
/* We inline FIFO full/empty checks as they are intended to be called from ISRs
* */
/** @ingroup uart_fifo
* @{
* \brief Determine if the TX fifo is full
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_tx_fifo_full(uint32_t uart)
{
return UART_FR(uart) & UART_FR_TXFF;
}
/**
* \brief Determine if the TX fifo is empty
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_tx_fifo_empty(uint32_t uart)
{
return UART_FR(uart) & UART_FR_TXFE;
}
/**
* \brief Determine if the RX fifo is full
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_rx_fifo_full(uint32_t uart)
{
return UART_FR(uart) & UART_FR_RXFF;
}
/**
* \brief Determine if the RX fifo is empty
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
static inline
bool uart_is_rx_fifo_empty(uint32_t uart)
{
return UART_FR(uart) & UART_FR_RXFE;
}
/**@}*/
void uart_enable_interrupts(uint32_t uart, enum uart_interrupt_flag ints);
void uart_disable_interrupts(uint32_t uart, enum uart_interrupt_flag ints);
void uart_enable_rx_interrupt(uint32_t uart);
void uart_disable_rx_interrupt(uint32_t uart);
void uart_enable_tx_interrupt(uint32_t uart);
void uart_disable_tx_interrupt(uint32_t uart);
void uart_clear_interrupt_flag(uint32_t uart, enum uart_interrupt_flag ints);
/* Let's keep this one inlined. It's designed to be used in ISRs */
/** @ingroup uart_irq
* @{
* \brief Determine if interrupt is generated by the given source
*
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] source source to check.
*/
static inline
bool uart_is_interrupt_source(uint32_t uart, enum uart_interrupt_flag source)
{
return UART_MIS(uart) & source;
}
/**@}*/
END_DECLS
/**@}*/
#endif /* LIBOPENCM3_LM4F_UART_H */

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup usb_defines USB Controller
*
* @brief <b>Defined Constants and Types for the LM4F USB Controller</b>
*
* @ingroup LM4Fxx_defines
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* @date 15 May 2013
*
* LGPL License Terms @ref lgpl_license
*/
#ifndef LIBOPENCM3_LM4F_USB_H
#define LIBOPENCM3_LM4F_USB_H
/**@{*/
#include <libopencm3/lm4f/memorymap.h>
#include <libopencm3/cm3/common.h>
/* ============================================================================
* USB registers
* --------------------------------------------------------------------------*/
/* USB Device Functional Address */
#define USB_FADDR MMIO8(USB_BASE + 0x00)
/* USB Power */
#define USB_POWER MMIO8(USB_BASE + 0x01)
/* USB Transmit Interrupt Status */
#define USB_TXIS MMIO16(USB_BASE + 0x02)
/* USB Receive Interrupt Status */
#define USB_RXIS MMIO16(USB_BASE + 0x04)
/* USB Transmit Interrupt Enable */
#define USB_TXIE MMIO16(USB_BASE + 0x06)
/* USB Receive Interrupt Enable */
#define USB_RXIE MMIO16(USB_BASE + 0x08)
/* USB General Interrupt Status */
#define USB_IS MMIO8(USB_BASE + 0x0A)
/* USB Interrupt Enable */
#define USB_IE MMIO8(USB_BASE + 0x0B)
/* USB Frame Value */
#define USB_FRAME MMIO16(USB_BASE + 0x0C)
/* USB Endpoint Index */
#define USB_EPIDX MMIO8(USB_BASE + 0x0E)
/* USB Test Mode */
#define USB_TEST MMIO8(USB_BASE + 0x0F)
/* USB FIFO Endpoint [0-7] */
#define USB_FIFO8(n) MMIO8(USB_BASE + 0x20 + n*0x04)
#define USB_FIFO16(n) MMIO16(USB_BASE + 0x20 + n*0x04)
#define USB_FIFO32(n) MMIO32(USB_BASE + 0x20 + n*0x04)
/* USB Transmit Dynamic FIFO Sizing */
#define USB_TXFIFOSZ MMIO8(USB_BASE + 0x62)
/* USB Receive Dynamic FIFO Sizing */
#define USB_RXFIFOSZ MMIO8(USB_BASE + 0x63)
/* USB Transmit FIFO Start Address */
#define USB_TXFIFOADD MMIO16(USB_BASE + 0x64)
/* USB Receive FIFO Start Address */
#define USB_RXFIFOADD MMIO16(USB_BASE + 0x66)
/* USB Connect Timing */
#define USB_CONTIM MMIO8(USB_BASE + 0x7A)
/* USB Full-Speed Last Transaction to End of Frame Timing */
#define USB_FSEOF MMIO8(USB_BASE + 0x7D)
/* USB Low-Speed Last Transaction to End of Frame Timing */
#define USB_LSEOF MMIO8(USB_BASE + 0x7E)
/* USB Control and Status Endpoint 0 Low */
#define USB_CSRL0 MMIO8(USB_BASE + 0x102)
/* USB Control and Status Endpoint 0 High */
#define USB_CSRH0 MMIO8(USB_BASE + 0x103)
/* USB Receive Byte Count Endpoint 0 */
#define USB_COUNT0 MMIO8(USB_BASE + 0x108)
/* USB Maximum Transmit Data Endpoint [1-7] */
#define USB_TXMAXP(n) MMIO16(USB_BASE + 0x100 + n*0x10)
/* USB Transmit Control and Status Endpoint [1-7] Low */
#define USB_TXCSRL(n) MMIO8(USB_BASE + 0x102 + n*0x10)
/* USB Transmit Control and Status Endpoint [1-7] High */
#define USB_TXCSRH(n) MMIO8(USB_BASE + 0x103 + n*0x10)
/* USB Maximum Receive Data Endpoint [1-7] */
#define USB_RXMAXP(n) MMIO16(USB_BASE + 0x104 + n*0x10)
/* USB Receive Control and Status Endpoint [1-7] Low */
#define USB_RXCSRL(n) MMIO8(USB_BASE + 0x106 + n*0x10)
/* USB Receive Control and Status Endpoint [1-7] High */
#define USB_RXCSRH(n) MMIO8(USB_BASE + 0x107 + n*0x10)
/* USB Receive Byte Count Endpoint [1-7] */
#define USB_RXCOUNT(n) MMIO16(USB_BASE + 0x108 + n*0x10)
/* USB Receive Double Packet Buffer Disable */
#define USB_RXDPKTBUFDIS MMIO16(USB_BASE + 0x340)
/* USB Transmit Double Packet Buffer Disable */
#define USB_TXDPKTBUFDIS MMIO16(USB_BASE + 0x342)
/* USB Device RESUME Raw Interrupt Status */
#define USB_DRRIS MMIO32(USB_BASE + 0x410)
/* USB Device RESUME Interrupt Mask */
#define USB_DRIM MMIO32(USB_BASE + 0x414)
/* USB Device RESUME Interrupt Status and Clear */
#define USB_DRISC MMIO32(USB_BASE + 0x418)
/* USB DMA Select */
#define USB_DMASEL MMIO32(USB_BASE + 0x450)
/* USB Peripheral Properties */
#define USB_PP MMIO32(USB_BASE + 0xFC0)
/* =============================================================================
* USB_FADDR values
* ---------------------------------------------------------------------------*/
/** Function Address */
#define USB_FADDR_FUNCADDR_MASK (0x3f << 0)
/* =============================================================================
* USB_POWER values
* ---------------------------------------------------------------------------*/
/** Isochronous Update */
#define USB_POWER_ISOUP (1 << 7)
/** Soft Connect/Disconnect */
#define USB_POWER_SOFTCONN (1 << 6)
/** RESET signaling */
#define USB_POWER_RESET (1 << 3)
/** RESUME signaling */
#define USB_POWER_RESUME (1 << 2)
/** SUSPEND mode */
#define USB_POWER_SUSPEND (1 << 1)
/** Power down PHY */
#define USB_POWER_PWRDNPHY (1 << 0)
/* =============================================================================
* Endpoint bitmasks for interrupt status and control registers
* Applies to USB_TXIS, USB_RXIS, USB_TXIE, USB_RXIE, USB_RXDPKTBUFDIS,
* USB_TXDPKTBUFDIS
* ---------------------------------------------------------------------------*/
#define USB_EP7 (1 << 7)
#define USB_EP6 (1 << 6)
#define USB_EP5 (1 << 5)
#define USB_EP4 (1 << 4)
#define USB_EP3 (1 << 3)
#define USB_EP2 (1 << 2)
#define USB_EP1 (1 << 1)
#define USB_EP0 (1 << 0)
/* =============================================================================
* USB interrupt mask values
*
* These are interchangeable across USB_IS, and USB_IE registers.
* ---------------------------------------------------------------------------*/
/** USB disconnect interrupt */
#define USB_IM_DISCON (1 << 5)
/** Start of frame */
#define USB_IM_SOF (1 << 3)
/** RESET signaling detected */
#define USB_IM_RESET (1 << 2)
/** RESUME signaling detected */
#define USB_IM_RESUME (1 << 1)
/** SUSPEND signaling detected */
#define USB_IM_SUSPEND (1 << 0)
/* =============================================================================
* USB_FRAME values
* ---------------------------------------------------------------------------*/
/** Frame number */
#define USB_FRAME_MASK (0x03FF)
/* =============================================================================
* USB_IDX values
* ---------------------------------------------------------------------------*/
/** Endpoint Index */
#define USB_EPIDX_MASK (0x0F)
/* =============================================================================
* USB_TEST values
* ---------------------------------------------------------------------------*/
/** FIFO access */
#define USB_TEST_FIFOACC (1 << 6)
/** Force full-speed mode */
#define USB_TEST_FORCEFS (1 << 5)
/* =============================================================================
* USB_TXFIFOSZ and USB_RXFIFOSZ values
* ---------------------------------------------------------------------------*/
/** Double packet buffer support */
#define USB_FIFOSZ_DPB (1 << 4)
/* USB Transmit Dynamic FIFO Sizing */
#define USB_FIFOSZ_SIZE_MASK (0x0F << 0)
#define USB_FIFOSZ_SIZE_8 (0x00 << 0)
#define USB_FIFOSZ_SIZE_16 (0x01 << 0)
#define USB_FIFOSZ_SIZE_32 (0x02 << 0)
#define USB_FIFOSZ_SIZE_64 (0x03 << 0)
#define USB_FIFOSZ_SIZE_128 (0x04 << 0)
#define USB_FIFOSZ_SIZE_256 (0x05 << 0)
#define USB_FIFOSZ_SIZE_512 (0x06 << 0)
#define USB_FIFOSZ_SIZE_1024 (0x07 << 0)
#define USB_FIFOSZ_SIZE_2048 (0x08 << 0)
/* =============================================================================
* USB_CONTIM values
* ---------------------------------------------------------------------------*/
/** Connect wait */
#define USB_CONTIM_WTCON_MASK (0x0F << 4)
/** Wait ID */
#define USB_CONTIM_WTID_MASK (0x0F << 0)
/* =============================================================================
* USB_CSRL0 values
* ---------------------------------------------------------------------------*/
/** Setup End Clear */
#define USB_CSRL0_SETENDC (1 << 7)
/** RXRDY Clear */
#define USB_CSRL0_RXRDYC (1 << 6)
/** Send Stall */
#define USB_CSRL0_STALL (1 << 5)
/** Setup End */
#define USB_CSRL0_SETEND (1 << 4)
/** Data End */
#define USB_CSRL0_DATAEND (1 << 3)
/** Endpoint Stalled */
#define USB_CSRL0_STALLED (1 << 2)
/** Transmit Packet Ready */
#define USB_CSRL0_TXRDY (1 << 1)
/** Receive Packet Ready */
#define USB_CSRL0_RXRDY (1 << 0)
/* =============================================================================
* USB_CSRH0 values
* ---------------------------------------------------------------------------*/
/** Flush FIFO */
#define USB_CSRH0_FLUSH (1 << 0)
/* =============================================================================
* USB_TXCSRLx values
* ---------------------------------------------------------------------------*/
/** Clear data toggle */
#define USB_TXCSRL_CLRDT (1 << 6)
/** Endpoint Stalled */
#define USB_TXCSRL_STALLED (1 << 5)
/** Send Stall */
#define USB_TXCSRL_STALL (1 << 4)
/** Flush FIFO */
#define USB_TXCSRL_FLUSH (1 << 3)
/** Underrun */
#define USB_TXCSRL_UNDRN (1 << 2)
/** FIFO not empty */
#define USB_TXCSRL_FIFONE (1 << 1)
/** Transmit Packet Ready */
#define USB_TXCSRL_TXRDY (1 << 0)
/* =============================================================================
* USB_TXCSRHx values
* ---------------------------------------------------------------------------*/
/** Auto set */
#define USB_TXCSRH_AUTOSET (1 << 7)
/** Isochronous transfers */
#define USB_TXCSRH_ISO (1 << 6)
/** Mode */
#define USB_TXCSRH_MODE (1 << 5)
/** DMA request enable */
#define USB_TXCSRH_DMAEN (1 << 4)
/** Force data toggle */
#define USB_TXCSRH_FDT (1 << 3)
/** DMA request mode */
#define USB_TXCSRH_DMAMOD (1 << 2)
/* =============================================================================
* USB_RXCSRLx values
* ---------------------------------------------------------------------------*/
/** Clear data toggle */
#define USB_RXCSRL_CLRDT (1 << 7)
/** Endpoint Stalled */
#define USB_RXCSRL_STALLED (1 << 6)
/** Send Stall */
#define USB_RXCSRL_STALL (1 << 5)
/** Flush FIFO */
#define USB_RXCSRL_FLUSH (1 << 4)
/** Data error */
#define USB_RXCSRL_DATAERR (1 << 2)
/** Overrun */
#define USB_RXCSRL_OVER (1 << 2)
/** FIFO full */
#define USB_RXCSRL_FULL (1 << 1)
/** Receive Packet Ready */
#define USB_RXCSRL_RXRDY (1 << 0)
/* =============================================================================
* USB_RXCSRHx values
* ---------------------------------------------------------------------------*/
/** Auto clear */
#define USB_RXCSRH_AUTOCL (1 << 7)
/** Isochronous transfers */
#define USB_RXCSRH_ISO (1 << 6)
/** DMA request enable */
#define USB_RXCSRH_DMAEN (1 << 5)
/** Disable NYET / PID error */
#define USB_RXCSRH_PIDERR (1 << 4)
/** DMA request mode */
#define USB_RXCSRH_DMAMOD (1 << 3)
/* =============================================================================
* USB_DRRIS values
* ---------------------------------------------------------------------------*/
/** RESUME interrupt status */
#define USB_DRRIS_RESUME (1 << 0)
/* =============================================================================
* USB_DRIM values
* ---------------------------------------------------------------------------*/
/** RESUME interrupt mask */
#define USB_DRIM_RESUME (1 << 0)
/* =============================================================================
* USB_DRISC values
* ---------------------------------------------------------------------------*/
/** RESUME interrupt status and clear */
#define USB_DRISC_RESUME (1 << 0)
/* =============================================================================
* USB_PP values
* ---------------------------------------------------------------------------*/
/** Endpoint count */
#define USB_PP_ECNT_MASK (0xFF << 8)
/** USB capability */
#define USB_PP_USB_MASK (0x03 << 6)
#define USB_PP_USB_NA (0x00 << 6)
#define USB_PP_USB_DEVICE (0x01 << 6)
#define USB_PP_USB_HOST (0x02 << 6)
#define USB_PP_USB_OTG (0x03 << 6)
/** PHY present */
#define USB_PP_PHY (1 << 4)
/** Controller type */
#define USB_PP_TYPE_MASK (0x0F << 0)
/* =============================================================================
* Convenience enums
* ---------------------------------------------------------------------------*/
enum usb_interrupt {
USB_INT_DISCON = USB_IM_DISCON,
USB_INT_SOF = USB_IM_SOF,
USB_INT_RESET = USB_IM_RESET,
USB_INT_RESUME = USB_IM_RESUME,
USB_INT_SUSPEND = USB_IM_SUSPEND,
};
enum usb_ep_interrupt {
USB_EP0_INT = USB_EP0,
USB_EP1_INT = USB_EP1,
USB_EP2_INT = USB_EP2,
USB_EP3_INT = USB_EP3,
USB_EP4_INT = USB_EP4,
USB_EP5_INT = USB_EP5,
USB_EP6_INT = USB_EP6,
USB_EP7_INT = USB_EP7,
};
/* =============================================================================
* Function prototypes
* ---------------------------------------------------------------------------*/
BEGIN_DECLS
void usb_enable_interrupts(enum usb_interrupt ints,
enum usb_ep_interrupt rx_ints,
enum usb_ep_interrupt tx_ints);
void usb_disable_interrupts(enum usb_interrupt ints,
enum usb_ep_interrupt rx_ints,
enum usb_ep_interrupt tx_ints);
END_DECLS
/**@}*/
#endif /* LIBOPENCM3_LM4F_USB_H */

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/** @mainpage libopencm3 LPC13xx
@version 1.0.0
@date 14 September 2012
API documentation for NXP Semiconductors LPC13xx Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC13xx LPC13xx
Libraries for NXP Semiconductors LPC13xx series.
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC13xx_defines LPC13xx Defines
@brief Defined Constants and Types for the LPC13xx series
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

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/** @defgroup gpio_defines GPIO Defines
@brief <b>Defined Constants and Types for the LPC13xx General Purpose I/O</b>
@ingroup LPC13xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LPC13XX_GPIO_H
#define LPC13XX_GPIO_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc13xx/memorymap.h>
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
#define GPIO0 GPIO_PIO0_BASE
#define GPIO1 GPIO_PIO1_BASE
#define GPIO2 GPIO_PIO2_BASE
#define GPIO3 GPIO_PIO3_BASE
/* --- GPIO registers ------------------------------------------------------ */
/* GPIO data register (GPIOn_DATA) */
#define GPIO_DATA(port) MMIO32(port + 0x3ffc)
#define GPIO0_DATA GPIO_DATA(GPIO0)
#define GPIO1_DATA GPIO_DATA(GPIO1)
#define GPIO2_DATA GPIO_DATA(GPIO2)
#define GPIO3_DATA GPIO_DATA(GPIO3)
/* GPIO data direction register (GPIOn_DIR) */
#define GPIO_DIR(port) MMIO32(port + 0x00)
#define GPIO0_DIR GPIO_DIR(GPIO0)
#define GPIO1_DIR GPIO_DIR(GPIO1)
#define GPIO2_DIR GPIO_DIR(GPIO2)
#define GPIO3_DIR GPIO_DIR(GPIO3)
/* GPIO interrupt sense register (GPIOn_IS) */
#define GPIO_IS(port) MMIO32(port + 0x04)
#define GPIO0_IS GPIO_IS(GPIO0)
#define GPIO1_IS GPIO_IS(GPIO1)
#define GPIO2_IS GPIO_IS(GPIO2)
#define GPIO3_IS GPIO_IS(GPIO3)
/* GPIO interrupt both edges sense register (GPIOn_IBE) */
#define GPIO_IBE(port) MMIO32(port + 0x08)
#define GPIO0_IBE GPIO_IBE(GPIO0)
#define GPIO1_IBE GPIO_IBE(GPIO1)
#define GPIO2_IBE GPIO_IBE(GPIO2)
#define GPIO3_IBE GPIO_IBE(GPIO3)
/* GPIO interrupt event register (GPIOn_IEV) */
#define GPIO_IEV(port) MMIO32(port + 0x0c)
#define GPIO0_IEV GPIO_IEV(GPIO0)
#define GPIO1_IEV GPIO_IEV(GPIO1)
#define GPIO2_IEV GPIO_IEV(GPIO2)
#define GPIO3_IEV GPIO_IEV(GPIO3)
/* GPIO interrupt mask register (GPIOn_IE) */
#define GPIO_IE(port) MMIO16(port + 0x10)
#define GPIO0_IE GPIO_IE(GPIO0)
#define GPIO1_IE GPIO_IE(GPIO1)
#define GPIO2_IE GPIO_IE(GPIO2)
#define GPIO3_IE GPIO_IE(GPIO3)
/* FIXME: IRS or RIS? Datasheet is not consistent here. */
/* GPIO raw interrupt status register (GPIOn_IRS) */
#define GPIO_IRS(port) MMIO16(port + 0x14)
#define GPIO0_IRS GPIO_IRS(GPIO0)
#define GPIO1_IRS GPIO_IRS(GPIO1)
#define GPIO2_IRS GPIO_IRS(GPIO2)
#define GPIO3_IRS GPIO_IRS(GPIO3)
/* GPIO masked interrupt status register (GPIOn_MIS) */
#define GPIO_MIS(port) MMIO16(port + 0x18)
#define GPIO0_MIS GPIO_MIS(GPIO0)
#define GPIO1_MIS GPIO_MIS(GPIO1)
#define GPIO2_MIS GPIO_MIS(GPIO2)
#define GPIO3_MIS GPIO_MIS(GPIO3)
/* GPIO interrupt clear register (GPIOn_IC) */
#define GPIO_IC(port) MMIO16(port + 0x1c)
#define GPIO0_IC GPIO_IC(GPIO0)
#define GPIO1_IC GPIO_IC(GPIO1)
#define GPIO2_IC GPIO_IC(GPIO2)
#define GPIO3_IC GPIO_IC(GPIO3)
BEGIN_DECLS
void gpio_set(uint32_t gpioport, uint16_t gpios);
END_DECLS
/**@}*/
#endif

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includeguard: LIBOPENCM3_LPC13xx_NVIC_H
partname_humanreadable: LPC 13xx series
partname_doxygen: LPC13xx
irqs:
0: pio0_0
1: pio0_1
2: pio0_2
3: pio0_3
4: pio0_4
5: pio0_5
6: pio0_6
7: pio0_7
8: pio0_8
9: pio0_9
10: pio0_10
11: pio0_11
12: pio1_0
13: pio1_1
14: pio1_2
15: pio1_3
16: pio1_4
17: pio1_5
18: pio1_6
19: pio1_7
20: pio1_8
21: pio1_9
22: pio1_10
23: pio1_11
24: pio2_0
25: pio2_1
26: pio2_2
27: pio2_3
28: pio2_4
29: pio2_5
30: pio2_6
31: pio2_7
32: pio2_8
33: pio2_9
34: pio2_10
35: pio2_11
36: pio3_0
37: pio3_1
38: pio3_2
39: pio3_3
40: i2c0
41: ct16b0
42: ct16b1
43: ct32b0
44: ct32b1
45: ssp0
46: uart
47: usb
48: usb_fiq
49: adc
50: wdt
51: bod
# 52: reserved
53: pio3
54: pio2
55: pio1
56: pio0
56: ssp1

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC13XX_MEMORYMAP_H
#define LPC13XX_MEMORYMAP_H
#include <libopencm3/cm3/common.h>
/* --- LPC13XX specific peripheral definitions ----------------------------- */
/* Memory map for all busses */
#define PERIPH_BASE_APB 0x40000000
#define PERIPH_BASE_AHB 0x50000000
/* Register boundary addresses */
/* APB */
#define I2C_BASE (PERIPH_BASE_APB + 0x00000)
#define WDT_BASE (PERIPH_BASE_APB + 0x04000)
#define UART_BASE (PERIPH_BASE_APB + 0x08000)
#define TIMER0_16BIT_BASE (PERIPH_BASE_APB + 0x0c000)
#define TIMER1_16BIT_BASE (PERIPH_BASE_APB + 0x10000)
#define TIMER0_32BIT_BASE (PERIPH_BASE_APB + 0x14000)
#define TIMER1_32BIT_BASE (PERIPH_BASE_APB + 0x18000)
#define ADC_BASE (PERIPH_BASE_APB + 0x1c000)
#define USB_BASE (PERIPH_BASE_APB + 0x20000)
/* PERIPH_BASE_APB + 0x28000 (0x4002 8000 - 0x4003 7FFF): Reserved */
#define PMU_BASE (PERIPH_BASE_APB + 0x38000)
#define FLASH_BASE (PERIPH_BASE_APB + 0x3c000)
#define SSP_BASE (PERIPH_BASE_APB + 0x40000)
#define IOCONFIG_BASE (PERIPH_BASE_APB + 0x44000)
#define SYSCTRL_BASE (PERIPH_BASE_APB + 0x48000)
/* PERIPH_BASE_APB + 0x4c000 (0x4004 c000 - 0x4007 FFFF): Reserved */
/* AHB */
#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x00000)
#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x10000)
#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x20000)
#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x30000)
/* PERIPH_BASE_AHB + 0x40000 (0x5004 0000 - 0x501F FFFF): Reserved */
#endif

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/** @mainpage libopencm3 LPC17xx
@version 1.0.0
@date 14 September 2012
API documentation for NXP Semiconductors LPC17xx Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC17xx LPC17xx
Libraries for NXP Semiconductors LPC17xx series.
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC17xx_defines LPC17xx Defines
@brief Defined Constants and Types for the LPC17xx series
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

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/** @defgroup gpio_defines GPIO Defines
@brief <b>Defined Constants and Types for the LPC17xx General Purpose I/O</b>
@ingroup LPC17xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC17XX_GPIO_H
#define LPC17XX_GPIO_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc17xx/memorymap.h>
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
#define GPIO0 GPIO_PIO0_BASE
#define GPIO1 GPIO_PIO1_BASE
#define GPIO2 GPIO_PIO2_BASE
#define GPIO3 GPIO_PIO3_BASE
#define GPIO4 GPIO_PIO4_BASE
/* GPIO number definitions (for convenience) */
#define GPIOPIN0 (1 << 0)
#define GPIOPIN1 (1 << 1)
#define GPIOPIN2 (1 << 2)
#define GPIOPIN3 (1 << 3)
#define GPIOPIN4 (1 << 4)
#define GPIOPIN5 (1 << 5)
#define GPIOPIN6 (1 << 6)
#define GPIOPIN7 (1 << 7)
#define GPIOPIN8 (1 << 8)
#define GPIOPIN9 (1 << 9)
#define GPIOPIN10 (1 << 10)
#define GPIOPIN11 (1 << 11)
#define GPIOPIN12 (1 << 12)
#define GPIOPIN13 (1 << 13)
#define GPIOPIN14 (1 << 14)
#define GPIOPIN15 (1 << 15)
#define GPIOPIN16 (1 << 16)
#define GPIOPIN17 (1 << 17)
#define GPIOPIN18 (1 << 18)
#define GPIOPIN19 (1 << 19)
#define GPIOPIN20 (1 << 20)
#define GPIOPIN21 (1 << 21)
#define GPIOPIN22 (1 << 22)
#define GPIOPIN23 (1 << 23)
#define GPIOPIN24 (1 << 24)
#define GPIOPIN25 (1 << 25)
#define GPIOPIN26 (1 << 26)
#define GPIOPIN27 (1 << 27)
#define GPIOPIN28 (1 << 28)
#define GPIOPIN29 (1 << 29)
#define GPIOPIN30 (1 << 30)
#define GPIOPIN31 (1 << 31)
/* --- GPIO registers ------------------------------------------------------ */
/* GPIO data direction register (GPIOn_DIR) */
#define GPIO_DIR(port) MMIO32(port + 0x00)
#define GPIO0_DIR GPIO_DIR(GPIO0)
#define GPIO1_DIR GPIO_DIR(GPIO1)
#define GPIO2_DIR GPIO_DIR(GPIO2)
#define GPIO3_DIR GPIO_DIR(GPIO3)
#define GPIO4_DIR GPIO_DIR(GPIO4)
/* GPIO fast mask register (GPIOn_DIR) */
#define GPIO_MASK(port) MMIO32(port + 0x10)
#define GPIO0_MASK GPIO_MASK(GPIO0)
#define GPIO1_MASK GPIO_MASK(GPIO1)
#define GPIO2_MASK GPIO_MASK(GPIO2)
#define GPIO3_MASK GPIO_MASK(GPIO3)
#define GPIO4_MASK GPIO_MASK(GPIO4)
/* GPIO port pin value register (GPIOn_PIN) */
#define GPIO_PIN(port) MMIO32(port + 0x14)
#define GPIO0_PIN GPIO_PIN(GPIO0)
#define GPIO1_PIN GPIO_PIN(GPIO1)
#define GPIO2_PIN GPIO_PIN(GPIO2)
#define GPIO3_PIN GPIO_PIN(GPIO3)
#define GPIO4_PIN GPIO_PIN(GPIO4)
/* GPIO port output set register (GPIOn_SET) */
#define GPIO_SET(port) MMIO32(port + 0x18)
#define GPIO0_SET GPIO_SET(GPIO0)
#define GPIO1_SET GPIO_SET(GPIO1)
#define GPIO2_SET GPIO_SET(GPIO2)
#define GPIO3_SET GPIO_SET(GPIO3)
#define GPIO4_SET GPIO_SET(GPIO4)
/* GPIO port output clear register (GPIOn_CLR) */
#define GPIO_CLR(port) MMIO32(port + 0x1C)
#define GPIO0_CLR GPIO_CLR(GPIO0)
#define GPIO1_CLR GPIO_CLR(GPIO1)
#define GPIO2_CLR GPIO_CLR(GPIO2)
#define GPIO3_CLR GPIO_CLR(GPIO3)
#define GPIO4_CLR GPIO_CLR(GPIO4)
/* GPIO interrupt register map */
/* Interrupt enable rising edge */
#define GPIO0_IER MMIO32(GPIOINTERRUPT_BASE + 0x90)
#define GPIO2_IER MMIO32(GPIOINTERRUPT_BASE + 0xB0)
/* Interrupt enable falling edge */
#define GPIO0_IEF MMIO32(GPIOINTERRUPT_BASE + 0x94)
#define GPIO2_IEF MMIO32(GPIOINTERRUPT_BASE + 0xB4)
/* Interrupt status rising edge */
#define GPIO0_ISR MMIO32(GPIOINTERRUPT_BASE + 0x84)
#define GPIO2_ISR MMIO32(GPIOINTERRUPT_BASE + 0xA4)
/* Interrupt status falling edge */
#define GPIO0_ISF MMIO32(GPIOINTERRUPT_BASE + 0x88)
#define GPIO2_ISF MMIO32(GPIOINTERRUPT_BASE + 0xA8)
/* Interrupt clear */
#define GPIO0_IC MMIO32(GPIOINTERRUPT_BASE + 0x8C)
#define GPIO1_IC MMIO32(GPIOINTERRUPT_BASE + 0xAC)
/* Overall interrupt status */
#define GPIO_IS MMIO32(GPIOINTERRUPT_BASE + 0x80)
BEGIN_DECLS
void gpio_set(uint32_t gpioport, uint32_t gpios);
void gpio_clear(uint32_t gpioport, uint32_t gpios);
END_DECLS
/**@}*/
#endif

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includeguard: LIBOPENCM3_LPC17xx_NVIC_H
partname_humanreadable: LPC 17xx series
partname_doxygen: LPC17xx
irqs:
0: wdt
1: timer0
2: timer1
3: timer2
4: timer3
5: uart0
6: uart1
7: uart2
8: uart3
9: pwm
10: i2c0
11: i2c1
12: i2c2
13: spi
14: ssp0
15: ssp1
16: pll0
17: rtc
18: eint0
19: eint1
20: eint2
21: eint3
22: adc
23: bod
24: usb
25: can
26: gpdma
27: i2s
28: ethernet
29: rit
30: motor_pwm
31: qei
32: pll1
33: usb_act
34: can_act

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC17XX_MEMORYMAP_H
#define LPC17XX_MEMORYMAP_H
#include <libopencm3/cm3/common.h>
/* --- LPC17XX specific peripheral definitions ----------------------------- */
/* Memory map for all busses */
#define PERIPH_BASE_APB0 0x40000000
#define PERIPH_BASE_APB1 0x40080000
#define PERIPH_BASE_AHB 0x20000000
/* Register boundary addresses */
/* APB0 */
#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000)
#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000)
#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000)
#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000)
/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */
#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000)
#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000)
#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000)
#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000)
#define GPIOINTERRUPT_BASE (PERIPH_BASE_APB0 + 0x28000)
#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000)
#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000)
#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000)
#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000)
#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000)
#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000)
#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000)
#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000)
/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */
#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000)
/* PERIPH_BASE_APB0 + 0X60000 (0x6000 0000 - 0x4007 BFFF): Reserved */
/* AHB */
#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x9c000)
#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x9c020)
#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x9c040)
#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x9c060)
#define GPIO_PIO4_BASE (PERIPH_BASE_AHB + 0x9c080)
#endif

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/** @defgroup adc_defines ADC Defines
@brief <b>Defined Constants and Types for the LPC43xx A/D Converter</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_ADC_H
#define LPC43XX_ADC_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* ADC port base addresses (for convenience) */
#define ADC0 ADC0_BASE
#define ADC1 ADC1_BASE
/* --- ADC registers ------------------------------------------------------- */
/* A/D Control Register */
#define ADC_CR(port) MMIO32(port + 0x000)
#define ADC0_CR ADC_CR(ADC0)
#define ADC1_CR ADC_CR(ADC1)
/* A/D Global Data Register */
#define ADC_GDR(port) MMIO32(port + 0x004)
#define ADC0_GDR ADC_GDR(ADC0)
#define ADC1_GDR ADC_GDR(ADC1)
/* A/D Interrupt Enable Register */
#define ADC_INTEN(port) MMIO32(port + 0x00C)
#define ADC0_INTEN ADC_INTEN(ADC0)
#define ADC1_INTEN ADC_INTEN(ADC1)
/* A/D Channel 0 Data Register */
#define ADC_DR0(port) MMIO32(port + 0x010)
#define ADC0_DR0 ADC_DR0(ADC0)
#define ADC1_DR0 ADC_DR0(ADC1)
/* A/D Channel 1 Data Register */
#define ADC_DR1(port) MMIO32(port + 0x014)
#define ADC0_DR1 ADC_DR1(ADC0)
#define ADC1_DR1 ADC_DR1(ADC1)
/* A/D Channel 2 Data Register */
#define ADC_DR2(port) MMIO32(port + 0x018)
#define ADC0_DR2 ADC_DR2(ADC0)
#define ADC1_DR2 ADC_DR2(ADC1)
/* A/D Channel 3 Data Register */
#define ADC_DR3(port) MMIO32(port + 0x01C)
#define ADC0_DR3 ADC_DR3(ADC0)
#define ADC1_DR3 ADC_DR3(ADC1)
/* A/D Channel 4 Data Register */
#define ADC_DR4(port) MMIO32(port + 0x020)
#define ADC0_DR4 ADC_DR4(ADC0)
#define ADC1_DR4 ADC_DR4(ADC1)
/* A/D Channel 5 Data Register */
#define ADC_DR5(port) MMIO32(port + 0x024)
#define ADC0_DR5 ADC_DR5(ADC0)
#define ADC1_DR5 ADC_DR5(ADC1)
/* A/D Channel 6 Data Register */
#define ADC_DR6(port) MMIO32(port + 0x028)
#define ADC0_DR6 ADC_DR6(ADC0)
#define ADC1_DR6 ADC_DR6(ADC1)
/* A/D Channel 7 Data Register */
#define ADC_DR7(port) MMIO32(port + 0x02C)
#define ADC0_DR7 ADC_DR7(ADC0)
#define ADC1_DR7 ADC_DR7(ADC1)
/* A/D Status Register */
#define ADC_STAT(port) MMIO32(port + 0x030)
#define ADC0_STAT ADC_STAT(ADC0)
#define ADC1_STAT ADC_STAT(ADC1)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup atimer_defines Alarm Timer Defines
@brief <b>Defined Constants and Types for the LPC43xx Alarm Timer</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_ATIMER_H
#define LPC43XX_ATIMER_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Alarm Timer registers ----------------------------------------------- */
/* Downcounter register */
#define ATIMER_DOWNCOUNTER MMIO32(ATIMER_BASE + 0x000)
/* Preset value register */
#define ATIMER_PRESET MMIO32(ATIMER_BASE + 0x004)
/* Interrupt clear enable register */
#define ATIMER_CLR_EN MMIO32(ATIMER_BASE + 0xFD8)
/* Interrupt set enable register */
#define ATIMER_SET_EN MMIO32(ATIMER_BASE + 0xFDC)
/* Status register */
#define ATIMER_STATUS MMIO32(ATIMER_BASE + 0xFE0)
/* Enable register */
#define ATIMER_ENABLE MMIO32(ATIMER_BASE + 0xFE4)
/* Clear register */
#define ATIMER_CLR_STAT MMIO32(ATIMER_BASE + 0xFE8)
/* Set register */
#define ATIMER_SET_STAT MMIO32(ATIMER_BASE + 0xFEC)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup ccu_defines Clock Control Unit Defines
@brief <b>Defined Constants and Types for the LPC43xx Clock Control Unit</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_CCU_H
#define LPC43XX_CCU_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- CCU1 registers ------------------------------------------------------ */
/* CCU1 power mode register */
#define CCU1_PM MMIO32(CCU1_BASE + 0x000)
/* CCU1 base clock status register */
#define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004)
/* CLK_APB3_BUS clock configuration register */
#define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100)
/* CLK_APB3_BUS clock status register */
#define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104)
/* CLK_APB3_I2C1 configuration register */
#define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108)
/* CLK_APB3_I2C1 status register */
#define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C)
/* CLK_APB3_DAC configuration register */
#define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110)
/* CLK_APB3_DAC status register */
#define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114)
/* CLK_APB3_ADC0 configuration register */
#define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118)
/* CLK_APB3_ADC0 status register */
#define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C)
/* CLK_APB3_ADC1 configuration register */
#define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120)
/* CLK_APB3_ADC1 status register */
#define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124)
/* CLK_APB3_CAN0 configuration register */
#define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128)
/* CLK_APB3_CAN0 status register */
#define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C)
/* CLK_APB1_BUS configuration register */
#define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200)
/* CLK_APB1_BUS status register */
#define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204)
/* CLK_APB1_MOTOCON configuration register */
#define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208)
/* CLK_APB1_MOTOCON status register */
#define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C)
/* CLK_APB1_I2C0 configuration register */
#define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210)
/* CLK_APB1_I2C0 status register */
#define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214)
/* CLK_APB1_I2S configuration register */
#define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218)
/* CLK_APB1_I2S status register */
#define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C)
/* CLK_APB3_CAN1 configuration register */
#define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220)
/* CLK_APB3_CAN1 status register */
#define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224)
/* CLK_SPIFI configuration register */
#define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300)
/* CLK_SPIFI status register */
#define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304)
/* CLK_M4_BUS configuration register */
#define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400)
/* CLK_M4_BUS status register */
#define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404)
/* CLK_M4_SPIFI configuration register */
#define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408)
/* CLK_M4_SPIFI status register */
#define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C)
/* CLK_M4_GPIO configuration register */
#define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410)
/* CLK_M4_GPIO status register */
#define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414)
/* CLK_M4_LCD configuration register */
#define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418)
/* CLK_M4_LCD status register */
#define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C)
/* CLK_M4_ETHERNET configuration register */
#define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420)
/* CLK_M4_ETHERNET status register */
#define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424)
/* CLK_M4_USB0 configuration register */
#define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428)
/* CLK_M4_USB0 status register */
#define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C)
/* CLK_M4_EMC configuration register */
#define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430)
/* CLK_M4_EMC status register */
#define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434)
/* CLK_M4_SDIO configuration register */
#define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438)
/* CLK_M4_SDIO status register */
#define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C)
/* CLK_M4_DMA configuration register */
#define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440)
/* CLK_M4_DMA status register */
#define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444)
/* CLK_M4_M4CORE configuration register */
#define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448)
/* CLK_M4_M4CORE status register */
#define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C)
/* CLK_M4_SCT configuration register */
#define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468)
/* CLK_M4_SCT status register */
#define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C)
/* CLK_M4_USB1 configuration register */
#define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470)
/* CLK_M4_USB1 status register */
#define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474)
/* CLK_M4_EMCDIV configuration register */
#define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478)
/* CLK_M4_EMCDIV status register */
#define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C)
/* CLK_M4_M0_CFG configuration register */
#define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490)
/* CLK_M4_M0_STAT status register */
#define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494)
/* CLK_M4_VADC_CFG configuration register */
#define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498)
/* CLK_M4_VADC_STAT configuration register */
#define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C)
/* CLK_M4_WWDT configuration register */
#define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500)
/* CLK_M4_WWDT status register */
#define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504)
/* CLK_M4_UART0 configuration register */
#define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508)
/* CLK_M4_UART0 status register */
#define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C)
/* CLK_M4_UART1 configuration register */
#define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510)
/* CLK_M4_UART1 status register */
#define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514)
/* CLK_M4_SSP0 configuration register */
#define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518)
/* CLK_M4_SSP0 status register */
#define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C)
/* CLK_M4_TIMER0 configuration register */
#define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520)
/* CLK_M4_TIMER0 status register */
#define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524)
/* CLK_M4_TIMER1 configuration register */
#define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528)
/* CLK_M4_TIMER1 status register */
#define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C)
/* CLK_M4_SCU configuration register */
#define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530)
/* CLK_M4_SCU status register */
#define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534)
/* CLK_M4_CREG configuration register */
#define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538)
/* CLK_M4_CREG status register */
#define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C)
/* CLK_M4_RITIMER configuration register */
#define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600)
/* CLK_M4_RITIMER status register */
#define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604)
/* CLK_M4_UART2 configuration register */
#define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608)
/* CLK_M4_UART2 status register */
#define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C)
/* CLK_M4_UART3 configuration register */
#define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610)
/* CLK_M4_UART3 status register */
#define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614)
/* CLK_M4_TIMER2 configuration register */
#define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618)
/* CLK_M4_TIMER2 status register */
#define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C)
/* CLK_M4_TIMER3 configuration register */
#define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620)
/* CLK_M4_TIMER3 status register */
#define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624)
/* CLK_M4_SSP1 configuration register */
#define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628)
/* CLK_M4_SSP1 status register */
#define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C)
/* CLK_M4_QEI configuration register */
#define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630)
/* CLK_M4_QEI status register */
#define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634)
/* CLK_PERIPH_BUS configuration register */
#define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700)
/* CLK_PERIPH_BUS status register */
#define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704)
/* CLK_PERIPH_CORE configuration register */
#define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710)
/* CLK_PERIPH_CORE status register */
#define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714)
/* CLK_PERIPH_SGPIO configuration register */
#define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718)
/* CLK_PERIPH_SGPIO status register */
#define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C)
/* CLK_USB0 configuration register */
#define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800)
/* CLK_USB0 status register */
#define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804)
/* CLK_USB1 configuration register */
#define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900)
/* CLK_USB1 status register */
#define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904)
/* CLK_SPI configuration register */
#define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00)
/* CLK_SPI status register */
#define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04)
/* CLK_VADC configuration register */
#define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00)
/* CLK_VADC status register */
#define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04)
/* --- CCU2 registers ------------------------------------------------------ */
/* CCU2 power mode register */
#define CCU2_PM MMIO32(CCU2_BASE + 0x000)
/* CCU2 base clocks status register */
#define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004)
/* CLK_APLL configuration register */
#define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100)
/* CLK_APLL status register */
#define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104)
/* CLK_APB2_UART3 configuration register */
#define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200)
/* CLK_APB2_UART3 status register */
#define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204)
/* CLK_APB2_UART2 configuration register */
#define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300)
/* CLK_APB2_UART2 status register */
#define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304)
/* CLK_APB0_UART1 configuration register */
#define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400)
/* CLK_APB0_UART1 status register */
#define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404)
/* CLK_APB0_UART0 configuration register */
#define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500)
/* CLK_APB0_UART0 status register */
#define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504)
/* CLK_APB2_SSP1 configuration register */
#define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600)
/* CLK_APB2_SSP1 status register */
#define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604)
/* CLK_APB0_SSP0 configuration register */
#define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700)
/* CLK_APB0_SSP0 status register */
#define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704)
/* CLK_SDIO configuration register (for SD/MMC) */
#define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800)
/* CLK_SDIO status register (for SD/MMC) */
#define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup creg_defines Configuration Registers Defines
@brief <b>Defined Constants and Types for the LPC43xx Configuration
Registers</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_CREG_H
#define LPC43XX_CREG_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- CREG registers ----------------------------------------------------- */
/*
* Chip configuration register 32 kHz oscillator output and BOD control
* register
*/
#define CREG_CREG0 MMIO32(CREG_BASE + 0x004)
/* ARM Cortex-M4 memory mapping */
#define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100)
/* Chip configuration register 1 */
#define CREG_CREG1 MMIO32(CREG_BASE + 0x108)
/* Chip configuration register 2 */
#define CREG_CREG2 MMIO32(CREG_BASE + 0x10C)
/* Chip configuration register 3 */
#define CREG_CREG3 MMIO32(CREG_BASE + 0x110)
/* Chip configuration register 4 */
#define CREG_CREG4 MMIO32(CREG_BASE + 0x114)
/* Chip configuration register 5 */
#define CREG_CREG5 MMIO32(CREG_BASE + 0x118)
/* DMA muxing control */
#define CREG_DMAMUX MMIO32(CREG_BASE + 0x11C)
/* Flash accelerator configuration register for flash bank A */
#define CREG_FLASHCFGA MMIO32(CREG_BASE + 0x120)
/* Flash accelerator configuration register for flash bank B */
#define CREG_FLASHCFGB MMIO32(CREG_BASE + 0x124)
/* ETB RAM configuration */
#define CREG_ETBCFG MMIO32(CREG_BASE + 0x128)
/*
* Chip configuration register 6. Controls multiple functions: Ethernet
* interface, SCT output, I2S0/1 inputs, EMC clock.
*/
#define CREG_CREG6 MMIO32(CREG_BASE + 0x12C)
/* Cortex-M4 TXEV event clear */
#define CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130)
/* Part ID (Boundary scan ID code, read-only) */
#define CREG_CHIPID MMIO32(CREG_BASE + 0x200)
/* Cortex-M0 TXEV event clear */
#define CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400)
/* ARM Cortex-M0 memory mapping */
#define CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404)
/* USB0 frame length adjust register */
#define CREG_USB0FLADJ MMIO32(CREG_BASE + 0x500)
/* USB1 frame length adjust register */
#define CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600)
/* --- CREG_CREG0 values ---------------------------------------- */
/* EN1KHZ: Enable 1 kHz output */
#define CREG_CREG0_EN1KHZ_SHIFT (0)
#define CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT)
/* EN32KHZ: Enable 32 kHz output */
#define CREG_CREG0_EN32KHZ_SHIFT (1)
#define CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT)
/* RESET32KHZ: 32 kHz oscillator reset */
#define CREG_CREG0_RESET32KHZ_SHIFT (2)
#define CREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT)
/* PD32KHZ: 32 kHz power control */
#define CREG_CREG0_PD32KHZ_SHIFT (3)
#define CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT)
/* USB0PHY: USB0 PHY power control */
#define CREG_CREG0_USB0PHY_SHIFT (5)
#define CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT)
/* ALARMCTRL: RTC_ALARM pin output control */
#define CREG_CREG0_ALARMCTRL_SHIFT (6)
#define CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT)
#define CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT)
/* BODLVL1: BOD trip level to generate an interrupt */
#define CREG_CREG0_BODLVL1_SHIFT (8)
#define CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT)
#define CREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT)
/* BODLVL2: BOD trip level to generate a reset */
#define CREG_CREG0_BODLVL2_SHIFT (10)
#define CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT)
#define CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT)
/* SAMPLECTRL: SAMPLE pin input/output control */
#define CREG_CREG0_SAMPLECTRL_SHIFT (12)
#define CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT)
#define CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT)
/* WAKEUP0CTRL: WAKEUP0 pin input/output control */
#define CREG_CREG0_WAKEUP0CTRL_SHIFT (14)
#define CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT)
#define CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT)
/* WAKEUP1CTRL: WAKEUP1 pin input/output control */
#define CREG_CREG0_WAKEUP1CTRL_SHIFT (16)
#define CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT)
#define CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT)
/* --- CREG_M4MEMMAP values ------------------------------------- */
/* M4MAP: Shadow address when accessing memory at address 0x00000000 */
#define CREG_M4MEMMAP_M4MAP_SHIFT (12)
#define CREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT)
#define CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT)
/* --- CREG_CREG5 values ---------------------------------------- */
/* M4TAPSEL: JTAG debug select for M4 core */
#define CREG_CREG5_M4TAPSEL_SHIFT (6)
#define CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT)
/* M0APPTAPSEL: JTAG debug select for M0 co-processor */
#define CREG_CREG5_M0APPTAPSEL_SHIFT (9)
#define CREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT)
/* --- CREG_DMAMUX values --------------------------------------- */
/* DMAMUXPER0: Select DMA to peripheral connection for DMA peripheral 0 */
#define CREG_DMAMUX_DMAMUXPER0_SHIFT (0)
#define CREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT)
#define CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT)
/* DMAMUXPER1: Select DMA to peripheral connection for DMA peripheral 1 */
#define CREG_DMAMUX_DMAMUXPER1_SHIFT (2)
#define CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT)
#define CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT)
/* DMAMUXPER2: Select DMA to peripheral connection for DMA peripheral 2 */
#define CREG_DMAMUX_DMAMUXPER2_SHIFT (4)
#define CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT)
#define CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT)
/* DMAMUXPER3: Select DMA to peripheral connection for DMA peripheral 3 */
#define CREG_DMAMUX_DMAMUXPER3_SHIFT (6)
#define CREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT)
#define CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT)
/* DMAMUXPER4: Select DMA to peripheral connection for DMA peripheral 4 */
#define CREG_DMAMUX_DMAMUXPER4_SHIFT (8)
#define CREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT)
#define CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT)
/* DMAMUXPER5: Select DMA to peripheral connection for DMA peripheral 5 */
#define CREG_DMAMUX_DMAMUXPER5_SHIFT (10)
#define CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT)
#define CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT)
/* DMAMUXPER6: Select DMA to peripheral connection for DMA peripheral 6 */
#define CREG_DMAMUX_DMAMUXPER6_SHIFT (12)
#define CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT)
#define CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT)
/* DMAMUXPER7: Select DMA to peripheral connection for DMA peripheral 7 */
#define CREG_DMAMUX_DMAMUXPER7_SHIFT (14)
#define CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT)
#define CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT)
/* DMAMUXPER8: Select DMA to peripheral connection for DMA peripheral 8 */
#define CREG_DMAMUX_DMAMUXPER8_SHIFT (16)
#define CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT)
#define CREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT)
/* DMAMUXPER9: Select DMA to peripheral connection for DMA peripheral 9 */
#define CREG_DMAMUX_DMAMUXPER9_SHIFT (18)
#define CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT)
#define CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT)
/* DMAMUXPER10: Select DMA to peripheral connection for DMA peripheral 10 */
#define CREG_DMAMUX_DMAMUXPER10_SHIFT (20)
#define CREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT)
#define CREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT)
/* DMAMUXPER11: Select DMA to peripheral connection for DMA peripheral 11 */
#define CREG_DMAMUX_DMAMUXPER11_SHIFT (22)
#define CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT)
#define CREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT)
/* DMAMUXPER12: Select DMA to peripheral connection for DMA peripheral 12 */
#define CREG_DMAMUX_DMAMUXPER12_SHIFT (24)
#define CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT)
#define CREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT)
/* DMAMUXPER13: Select DMA to peripheral connection for DMA peripheral 13 */
#define CREG_DMAMUX_DMAMUXPER13_SHIFT (26)
#define CREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT)
#define CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT)
/* DMAMUXPER14: Select DMA to peripheral connection for DMA peripheral 14 */
#define CREG_DMAMUX_DMAMUXPER14_SHIFT (28)
#define CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT)
#define CREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT)
/* DMAMUXPER15: Select DMA to peripheral connection for DMA peripheral 15 */
#define CREG_DMAMUX_DMAMUXPER15_SHIFT (30)
#define CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT)
#define CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT)
/* --- CREG_FLASHCFGA values ------------------------------------ */
/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number
* of BASE_M4_CLK clocks used for a flash access */
#define CREG_FLASHCFGA_FLASHTIM_SHIFT (12)
#define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT)
#define CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT)
/* POW: Flash bank A power control */
#define CREG_FLASHCFGA_POW_SHIFT (31)
#define CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT)
/* --- CREG_FLASHCFGB values ------------------------------------ */
/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number
* of BASE_M4_CLK clocks used for a flash access */
#define CREG_FLASHCFGB_FLASHTIM_SHIFT (12)
#define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT)
#define CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT)
/* POW: Flash bank B power control */
#define CREG_FLASHCFGB_POW_SHIFT (31)
#define CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT)
/* --- CREG_ETBCFG values --------------------------------------- */
/* ETB: Select SRAM interface */
#define CREG_ETBCFG_ETB_SHIFT (0)
#define CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT)
/* --- CREG_CREG6 values ---------------------------------------- */
/* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the
* PHY interface */
#define CREG_CREG6_ETHMODE_SHIFT (0)
#define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT)
#define CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT)
/* CTOUTCTRL: Selects the functionality of the SCT outputs */
#define CREG_CREG6_CTOUTCTRL_SHIFT (4)
#define CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT)
/* I2S0_TX_SCK_IN_SEL: I2S0_TX_SCK input select */
#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12)
#define CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT)
/* I2S0_RX_SCK_IN_SEL: I2S0_RX_SCK input select */
#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13)
#define CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT)
/* I2S1_TX_SCK_IN_SEL: I2S1_TX_SCK input select */
#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14)
#define CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT)
/* I2S1_RX_SCK_IN_SEL: I2S1_RX_SCK input select */
#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15)
#define CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT)
/* EMC_CLK_SEL: EMC_CLK divided clock select */
#define CREG_CREG6_EMC_CLK_SEL_SHIFT (16)
#define CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT)
/* --- CREG_M4TXEVENT values ------------------------------------ */
/* TXEVCLR: Cortex-M4 TXEV event */
#define CREG_M4TXEVENT_TXEVCLR_SHIFT (0)
#define CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT)
/* --- CREG_M0TXEVENT values ------------------------------------ */
/* TXEVCLR: Cortex-M0 TXEV event */
#define CREG_M0TXEVENT_TXEVCLR_SHIFT (0)
#define CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT)
/* --- CREG_M0APPMEMMAP values ---------------------------------- */
/* M0APPMAP: Shadow address when accessing memory at address 0x00000000 */
#define CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12)
#define CREG_M0APPMEMMAP_M0APPMAP_MASK \
(0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)
#define CREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)
/* --- CREG_USB0FLADJ values ------------------------------------ */
/* FLTV: Frame length timing value */
#define CREG_USB0FLADJ_FLTV_SHIFT (0)
#define CREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT)
#define CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT)
/* --- CREG_USB1FLADJ values ------------------------------------ */
/* FLTV: Frame length timing value */
#define CREG_USB1FLADJ_FLTV_SHIFT (0)
#define CREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT)
#define CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @mainpage libopencm3 LPC43xx
@version 1.0.0
@date 14 September 2012
API documentation for NXP Semiconductors LPC43xx Cortex M3 series.
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC43xx LPC43xx
Libraries for NXP Semiconductors LPC43xx series.
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup LPC43xx_defines LPC43xx Defines
@brief Defined Constants and Types for the LPC43xx series
@version 1.0.0
@date 14 September 2012
LGPL License Terms @ref lgpl_license
*/

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/** @defgroup eventrouter_defines Event Router Defines
@brief <b>Defined Constants and Types for the LPC43xx Event Router</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_EVENTROUTER_H
#define LPC43XX_EVENTROUTER_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Event Router registers ---------------------------------------------- */
/* Level configuration register */
#define EVENTROUTER_HILO MMIO32(EVENTROUTER_BASE + 0x000)
/* Edge configuration */
#define EVENTROUTER_EDGE MMIO32(EVENTROUTER_BASE + 0x004)
/* Clear event enable register */
#define EVENTROUTER_CLR_EN MMIO32(EVENTROUTER_BASE + 0xFD8)
/* Set event enable register */
#define EVENTROUTER_SET_EN MMIO32(EVENTROUTER_BASE + 0xFDC)
/* Event Status register */
#define EVENTROUTER_STATUS MMIO32(EVENTROUTER_BASE + 0xFE0)
/* Event Enable register */
#define EVENTROUTER_ENABLE MMIO32(EVENTROUTER_BASE + 0xFE4)
/* Clear event status register */
#define EVENTROUTER_CLR_STAT MMIO32(EVENTROUTER_BASE + 0xFE8)
/* Set event status register */
#define EVENTROUTER_SET_STAT MMIO32(EVENTROUTER_BASE + 0xFEC)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup gima_defines Global Input Multiplexer Array Defines
@brief <b>Defined Constants and Types for the LPC43xx Global Input Multiplexer
Array</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_GIMA_H
#define LPC43XX_GIMA_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- GIMA registers ----------------------------------------------------- */
/* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
#define GIMA_CAP0_0_IN MMIO32(GIMA_BASE + 0x000)
/* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
#define GIMA_CAP0_1_IN MMIO32(GIMA_BASE + 0x004)
/* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
#define GIMA_CAP0_2_IN MMIO32(GIMA_BASE + 0x008)
/* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
#define GIMA_CAP0_3_IN MMIO32(GIMA_BASE + 0x00C)
/* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
#define GIMA_CAP1_0_IN MMIO32(GIMA_BASE + 0x010)
/* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
#define GIMA_CAP1_1_IN MMIO32(GIMA_BASE + 0x014)
/* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
#define GIMA_CAP1_2_IN MMIO32(GIMA_BASE + 0x018)
/* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
#define GIMA_CAP1_3_IN MMIO32(GIMA_BASE + 0x01C)
/* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
#define GIMA_CAP2_0_IN MMIO32(GIMA_BASE + 0x020)
/* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
#define GIMA_CAP2_1_IN MMIO32(GIMA_BASE + 0x024)
/* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
#define GIMA_CAP2_2_IN MMIO32(GIMA_BASE + 0x028)
/* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
#define GIMA_CAP2_3_IN MMIO32(GIMA_BASE + 0x02C)
/* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
#define GIMA_CAP3_0_IN MMIO32(GIMA_BASE + 0x030)
/* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
#define GIMA_CAP3_1_IN MMIO32(GIMA_BASE + 0x034)
/* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
#define GIMA_CAP3_2_IN MMIO32(GIMA_BASE + 0x038)
/* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
#define GIMA_CAP3_3_IN MMIO32(GIMA_BASE + 0x03C)
/* SCT CTIN_0 capture input multiplexer (GIMA output 16) */
#define GIMA_CTIN_0_IN MMIO32(GIMA_BASE + 0x040)
/* SCT CTIN_1 capture input multiplexer (GIMA output 17) */
#define GIMA_CTIN_1_IN MMIO32(GIMA_BASE + 0x044)
/* SCT CTIN_2 capture input multiplexer (GIMA output 18) */
#define GIMA_CTIN_2_IN MMIO32(GIMA_BASE + 0x048)
/* SCT CTIN_3 capture input multiplexer (GIMA output 19) */
#define GIMA_CTIN_3_IN MMIO32(GIMA_BASE + 0x04C)
/* SCT CTIN_4 capture input multiplexer (GIMA output 20) */
#define GIMA_CTIN_4_IN MMIO32(GIMA_BASE + 0x050)
/* SCT CTIN_5 capture input multiplexer (GIMA output 21) */
#define GIMA_CTIN_5_IN MMIO32(GIMA_BASE + 0x054)
/* SCT CTIN_6 capture input multiplexer (GIMA output 22) */
#define GIMA_CTIN_6_IN MMIO32(GIMA_BASE + 0x058)
/* SCT CTIN_7 capture input multiplexer (GIMA output 23) */
#define GIMA_CTIN_7_IN MMIO32(GIMA_BASE + 0x05C)
/* VADC trigger input multiplexer (GIMA output 24) */
#define GIMA_VADC_TRIGGER_IN MMIO32(GIMA_BASE + 0x060)
/* Event router input 13 multiplexer (GIMA output 25) */
#define GIMA_EVENTROUTER_13_IN MMIO32(GIMA_BASE + 0x064)
/* Event router input 14 multiplexer (GIMA output 26) */
#define GIMA_EVENTROUTER_14_IN MMIO32(GIMA_BASE + 0x068)
/* Event router input 16 multiplexer (GIMA output 27) */
#define GIMA_EVENTROUTER_16_IN MMIO32(GIMA_BASE + 0x06C)
/* ADC start0 input multiplexer (GIMA output 28) */
#define GIMA_ADCSTART0_IN MMIO32(GIMA_BASE + 0x070)
/* ADC start1 input multiplexer (GIMA output 29) */
#define GIMA_ADCSTART1_IN MMIO32(GIMA_BASE + 0x074)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup gpdma_defines General Purpose DMA Defines
*
* @brief <b>Defined Constants and Types for the LPC43xx General Purpose DMA</b>
*
* @ingroup LPC43xx_defines
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
*
* @date 10 March 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_GPDMA_H
#define LPC43XX_GPDMA_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct gpdma_lli_t gpdma_lli_t;
struct gpdma_lli_t {
void* csrcaddr;
void* cdestaddr;
uint32_t clli;
uint32_t ccontrol;
};
/* --- GPDMA registers ----------------------------------------------------- */
/* General registers */
/* DMA Interrupt Status Register */
#define GPDMA_INTSTAT MMIO32(GPDMA_BASE + 0x000)
/* DMA Interrupt Terminal Count Request Status Register */
#define GPDMA_INTTCSTAT MMIO32(GPDMA_BASE + 0x004)
/* DMA Interrupt Terminal Count Request Clear Register */
#define GPDMA_INTTCCLEAR MMIO32(GPDMA_BASE + 0x008)
/* DMA Interrupt Error Status Register */
#define GPDMA_INTERRSTAT MMIO32(GPDMA_BASE + 0x00C)
/* DMA Interrupt Error Clear Register */
#define GPDMA_INTERRCLR MMIO32(GPDMA_BASE + 0x010)
/* DMA Raw Interrupt Terminal Count Status Register */
#define GPDMA_RAWINTTCSTAT MMIO32(GPDMA_BASE + 0x014)
/* DMA Raw Error Interrupt Status Register */
#define GPDMA_RAWINTERRSTAT MMIO32(GPDMA_BASE + 0x018)
/* DMA Enabled Channel Register */
#define GPDMA_ENBLDCHNS MMIO32(GPDMA_BASE + 0x01C)
/* DMA Software Burst Request Register */
#define GPDMA_SOFTBREQ MMIO32(GPDMA_BASE + 0x020)
/* DMA Software Single Request Register */
#define GPDMA_SOFTSREQ MMIO32(GPDMA_BASE + 0x024)
/* DMA Software Last Burst Request Register */
#define GPDMA_SOFTLBREQ MMIO32(GPDMA_BASE + 0x028)
/* DMA Software Last Single Request Register */
#define GPDMA_SOFTLSREQ MMIO32(GPDMA_BASE + 0x02C)
/* DMA Configuration Register */
#define GPDMA_CONFIG MMIO32(GPDMA_BASE + 0x030)
/* DMA Synchronization Register */
#define GPDMA_SYNC MMIO32(GPDMA_BASE + 0x034)
/* Channel registers */
/* Source Address Register */
#define GPDMA_CSRCADDR(channel) MMIO32(GPDMA_BASE + 0x100 + \
(channel * 0x20))
#define GPDMA_C0SRCADDR GPDMA_CSRCADDR(0)
#define GPDMA_C1SRCADDR GPDMA_CSRCADDR(1)
#define GPDMA_C2SRCADDR GPDMA_CSRCADDR(2)
#define GPDMA_C3SRCADDR GPDMA_CSRCADDR(3)
#define GPDMA_C4SRCADDR GPDMA_CSRCADDR(4)
#define GPDMA_C5SRCADDR GPDMA_CSRCADDR(5)
#define GPDMA_C6SRCADDR GPDMA_CSRCADDR(6)
#define GPDMA_C7SRCADDR GPDMA_CSRCADDR(7)
/* Destination Address Register */
#define GPDMA_CDESTADDR(channel) MMIO32(GPDMA_BASE + 0x104 + \
(channel * 0x20))
#define GPDMA_C0DESTADDR GPDMA_CDESTADDR(0)
#define GPDMA_C1DESTADDR GPDMA_CDESTADDR(1)
#define GPDMA_C2DESTADDR GPDMA_CDESTADDR(2)
#define GPDMA_C3DESTADDR GPDMA_CDESTADDR(3)
#define GPDMA_C4DESTADDR GPDMA_CDESTADDR(4)
#define GPDMA_C5DESTADDR GPDMA_CDESTADDR(5)
#define GPDMA_C6DESTADDR GPDMA_CDESTADDR(6)
#define GPDMA_C7DESTADDR GPDMA_CDESTADDR(7)
/* Linked List Item Register */
#define GPDMA_CLLI(channel) MMIO32(GPDMA_BASE + 0x108 + \
(channel * 0x20))
#define GPDMA_C0LLI GPDMA_CLLI(0)
#define GPDMA_C1LLI GPDMA_CLLI(1)
#define GPDMA_C2LLI GPDMA_CLLI(2)
#define GPDMA_C3LLI GPDMA_CLLI(3)
#define GPDMA_C4LLI GPDMA_CLLI(4)
#define GPDMA_C5LLI GPDMA_CLLI(5)
#define GPDMA_C6LLI GPDMA_CLLI(6)
#define GPDMA_C7LLI GPDMA_CLLI(7)
/* Control Register */
#define GPDMA_CCONTROL(channel) MMIO32(GPDMA_BASE + 0x10C + \
(channel * 0x20))
#define GPDMA_C0CONTROL GPDMA_CCONTROL(0)
#define GPDMA_C1CONTROL GPDMA_CCONTROL(1)
#define GPDMA_C2CONTROL GPDMA_CCONTROL(2)
#define GPDMA_C3CONTROL GPDMA_CCONTROL(3)
#define GPDMA_C4CONTROL GPDMA_CCONTROL(4)
#define GPDMA_C5CONTROL GPDMA_CCONTROL(5)
#define GPDMA_C6CONTROL GPDMA_CCONTROL(6)
#define GPDMA_C7CONTROL GPDMA_CCONTROL(7)
/* Configuration Register */
#define GPDMA_CCONFIG(channel) MMIO32(GPDMA_BASE + 0x110 + \
(channel * 0x20))
#define GPDMA_C0CONFIG GPDMA_CCONFIG(0)
#define GPDMA_C1CONFIG GPDMA_CCONFIG(1)
#define GPDMA_C2CONFIG GPDMA_CCONFIG(2)
#define GPDMA_C3CONFIG GPDMA_CCONFIG(3)
#define GPDMA_C4CONFIG GPDMA_CCONFIG(4)
#define GPDMA_C5CONFIG GPDMA_CCONFIG(5)
#define GPDMA_C6CONFIG GPDMA_CCONFIG(6)
#define GPDMA_C7CONFIG GPDMA_CCONFIG(7)
/* --- Common fields -------------------------------------------- */
#define GPDMA_CSRCADDR_SRCADDR_SHIFT (0)
#define GPDMA_CSRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_CSRCADDR_SRCADDR_SHIFT)
#define GPDMA_CSRCADDR_SRCADDR(x) ((x) << GPDMA_CSRCADDR_SRCADDR_SHIFT)
#define GPDMA_CDESTADDR_DESTADDR_SHIFT (0)
#define GPDMA_CDESTADDR_DESTADDR_MASK \
(0xffffffff << GPDMA_CDESTADDR_DESTADDR_SHIFT)
#define GPDMA_CDESTADDR_DESTADDR(x) ((x) << GPDMA_CDESTADDR_DESTADDR_SHIFT)
#define GPDMA_CLLI_LM_SHIFT (0)
#define GPDMA_CLLI_LM_MASK (0x1 << GPDMA_CLLI_LM_SHIFT)
#define GPDMA_CLLI_LM(x) ((x) << GPDMA_CLLI_LM_SHIFT)
#define GPDMA_CLLI_LLI_SHIFT (2)
#define GPDMA_CLLI_LLI_MASK (0x3fffffff << GPDMA_CLLI_LLI_SHIFT)
#define GPDMA_CLLI_LLI(x) ((x) << GPDMA_CLLI_LLI_SHIFT)
#define GPDMA_CCONTROL_TRANSFERSIZE_SHIFT (0)
#define GPDMA_CCONTROL_TRANSFERSIZE_MASK \
(0xfff << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT)
#define GPDMA_CCONTROL_TRANSFERSIZE(x) \
((x) << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT)
#define GPDMA_CCONTROL_SBSIZE_SHIFT (12)
#define GPDMA_CCONTROL_SBSIZE_MASK (0x7 << GPDMA_CCONTROL_SBSIZE_SHIFT)
#define GPDMA_CCONTROL_SBSIZE(x) ((x) << GPDMA_CCONTROL_SBSIZE_SHIFT)
#define GPDMA_CCONTROL_DBSIZE_SHIFT (15)
#define GPDMA_CCONTROL_DBSIZE_MASK (0x7 << GPDMA_CCONTROL_DBSIZE_SHIFT)
#define GPDMA_CCONTROL_DBSIZE(x) ((x) << GPDMA_CCONTROL_DBSIZE_SHIFT)
#define GPDMA_CCONTROL_SWIDTH_SHIFT (18)
#define GPDMA_CCONTROL_SWIDTH_MASK (0x7 << GPDMA_CCONTROL_SWIDTH_SHIFT)
#define GPDMA_CCONTROL_SWIDTH(x) ((x) << GPDMA_CCONTROL_SWIDTH_SHIFT)
#define GPDMA_CCONTROL_DWIDTH_SHIFT (21)
#define GPDMA_CCONTROL_DWIDTH_MASK (0x7 << GPDMA_CCONTROL_DWIDTH_SHIFT)
#define GPDMA_CCONTROL_DWIDTH(x) ((x) << GPDMA_CCONTROL_DWIDTH_SHIFT)
#define GPDMA_CCONTROL_S_SHIFT (24)
#define GPDMA_CCONTROL_S_MASK (0x1 << GPDMA_CCONTROL_S_SHIFT)
#define GPDMA_CCONTROL_S(x) ((x) << GPDMA_CCONTROL_S_SHIFT)
#define GPDMA_CCONTROL_D_SHIFT (25)
#define GPDMA_CCONTROL_D_MASK (0x1 << GPDMA_CCONTROL_D_SHIFT)
#define GPDMA_CCONTROL_D(x) ((x) << GPDMA_CCONTROL_D_SHIFT)
#define GPDMA_CCONTROL_SI_SHIFT (26)
#define GPDMA_CCONTROL_SI_MASK (0x1 << GPDMA_CCONTROL_SI_SHIFT)
#define GPDMA_CCONTROL_SI(x) ((x) << GPDMA_CCONTROL_SI_SHIFT)
#define GPDMA_CCONTROL_DI_SHIFT (27)
#define GPDMA_CCONTROL_DI_MASK (0x1 << GPDMA_CCONTROL_DI_SHIFT)
#define GPDMA_CCONTROL_DI(x) ((x) << GPDMA_CCONTROL_DI_SHIFT)
#define GPDMA_CCONTROL_PROT1_SHIFT (28)
#define GPDMA_CCONTROL_PROT1_MASK (0x1 << GPDMA_CCONTROL_PROT1_SHIFT)
#define GPDMA_CCONTROL_PROT1(x) ((x) << GPDMA_CCONTROL_PROT1_SHIFT)
#define GPDMA_CCONTROL_PROT2_SHIFT (29)
#define GPDMA_CCONTROL_PROT2_MASK (0x1 << GPDMA_CCONTROL_PROT2_SHIFT)
#define GPDMA_CCONTROL_PROT2(x) ((x) << GPDMA_CCONTROL_PROT2_SHIFT)
#define GPDMA_CCONTROL_PROT3_SHIFT (30)
#define GPDMA_CCONTROL_PROT3_MASK (0x1 << GPDMA_CCONTROL_PROT3_SHIFT)
#define GPDMA_CCONTROL_PROT3(x) ((x) << GPDMA_CCONTROL_PROT3_SHIFT)
#define GPDMA_CCONTROL_I_SHIFT (31)
#define GPDMA_CCONTROL_I_MASK (0x1 << GPDMA_CCONTROL_I_SHIFT)
#define GPDMA_CCONTROL_I(x) ((x) << GPDMA_CCONTROL_I_SHIFT)
#define GPDMA_CCONFIG_E_SHIFT (0)
#define GPDMA_CCONFIG_E_MASK (0x1 << GPDMA_CCONFIG_E_SHIFT)
#define GPDMA_CCONFIG_E(x) ((x) << GPDMA_CCONFIG_E_SHIFT)
#define GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT (1)
#define GPDMA_CCONFIG_SRCPERIPHERAL_MASK \
(0x1f << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT)
#define GPDMA_CCONFIG_SRCPERIPHERAL(x) \
((x) << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT)
#define GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT (6)
#define GPDMA_CCONFIG_DESTPERIPHERAL_MASK \
(0x1f << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT)
#define GPDMA_CCONFIG_DESTPERIPHERAL(x) \
((x) << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT)
#define GPDMA_CCONFIG_FLOWCNTRL_SHIFT (11)
#define GPDMA_CCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CCONFIG_FLOWCNTRL_SHIFT)
#define GPDMA_CCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CCONFIG_FLOWCNTRL_SHIFT)
#define GPDMA_CCONFIG_IE_SHIFT (14)
#define GPDMA_CCONFIG_IE_MASK (0x1 << GPDMA_CCONFIG_IE_SHIFT)
#define GPDMA_CCONFIG_IE(x) ((x) << GPDMA_CCONFIG_IE_SHIFT)
#define GPDMA_CCONFIG_ITC_SHIFT (15)
#define GPDMA_CCONFIG_ITC_MASK (0x1 << GPDMA_CCONFIG_ITC_SHIFT)
#define GPDMA_CCONFIG_ITC(x) ((x) << GPDMA_CCONFIG_ITC_SHIFT)
#define GPDMA_CCONFIG_L_SHIFT (16)
#define GPDMA_CCONFIG_L_MASK (0x1 << GPDMA_CCONFIG_L_SHIFT)
#define GPDMA_CCONFIG_L(x) ((x) << GPDMA_CCONFIG_L_SHIFT)
#define GPDMA_CCONFIG_A_SHIFT (17)
#define GPDMA_CCONFIG_A_MASK (0x1 << GPDMA_CCONFIG_A_SHIFT)
#define GPDMA_CCONFIG_A(x) ((x) << GPDMA_CCONFIG_A_SHIFT)
#define GPDMA_CCONFIG_H_SHIFT (18)
#define GPDMA_CCONFIG_H_MASK (0x1 << GPDMA_CCONFIG_H_SHIFT)
#define GPDMA_CCONFIG_H(x) ((x) << GPDMA_CCONFIG_H_SHIFT)
/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */
/* --- GPDMA_NTSTAT values -------------------------------------- */
/* INTSTAT: Status of DMA channel interrupts after masking */
#define GPDMA_NTSTAT_INTSTAT_SHIFT (0)
#define GPDMA_NTSTAT_INTSTAT_MASK (0xff << GPDMA_NTSTAT_INTSTAT_SHIFT)
#define GPDMA_NTSTAT_INTSTAT(x) ((x) << GPDMA_NTSTAT_INTSTAT_SHIFT)
/* --- GPDMA_INTTCSTAT values ----------------------------------- */
/* INTTCSTAT: Terminal count interrupt request status for DMA channels */
#define GPDMA_INTTCSTAT_INTTCSTAT_SHIFT (0)
#define GPDMA_INTTCSTAT_INTTCSTAT_MASK (0xff << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT)
#define GPDMA_INTTCSTAT_INTTCSTAT(x) ((x) << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT)
/* --- GPDMA_INTTCCLEAR values ---------------------------------- */
/* INTTCCLEAR: Allows clearing the Terminal count interrupt request (IntTCStat)
for DMA channels */
#define GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT (0)
#define GPDMA_INTTCCLEAR_INTTCCLEAR_MASK \
(0xff << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT)
#define GPDMA_INTTCCLEAR_INTTCCLEAR(x) \
((x) << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT)
/* --- GPDMA_INTERRSTAT values ---------------------------------- */
/* INTERRSTAT: Interrupt error status for DMA channels */
#define GPDMA_INTERRSTAT_INTERRSTAT_SHIFT (0)
#define GPDMA_INTERRSTAT_INTERRSTAT_MASK \
(0xff << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT)
#define GPDMA_INTERRSTAT_INTERRSTAT(x) \
((x) << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT)
/* --- GPDMA_INTERRCLR values ----------------------------------- */
/* INTERRCLR: Writing a 1 clears the error interrupt request (IntErrStat)
for DMA channels */
#define GPDMA_INTERRCLR_INTERRCLR_SHIFT (0)
#define GPDMA_INTERRCLR_INTERRCLR_MASK \
(0xff << GPDMA_INTERRCLR_INTERRCLR_SHIFT)
#define GPDMA_INTERRCLR_INTERRCLR(x) \
((x) << GPDMA_INTERRCLR_INTERRCLR_SHIFT)
/* --- GPDMA_RAWINTTCSTAT values -------------------------------- */
/* RAWINTTCSTAT: Status of the terminal count interrupt for DMA channels
prior to masking */
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT (0)
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_MASK \
(0xff << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT)
#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT(x) \
((x) << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT)
/* --- GPDMA_RAWINTERRSTAT values ------------------------------- */
/* RAWINTERRSTAT: Status of the error interrupt for DMA channels prior to
masking */
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT (0)
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_MASK \
(0xff << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT)
#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT(x) \
((x) << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT)
/* --- GPDMA_ENBLDCHNS values ----------------------------------- */
/* ENABLEDCHANNELS: Enable status for DMA channels */
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT (0)
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_MASK \
(0xff << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT)
#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS(x) \
((x) << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT)
/* --- GPDMA_SOFTBREQ values ------------------------------------ */
/* SOFTBREQ: Software burst request flags for each of 16 possible sources */
#define GPDMA_SOFTBREQ_SOFTBREQ_SHIFT (0)
#define GPDMA_SOFTBREQ_SOFTBREQ_MASK (0xffff << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT)
#define GPDMA_SOFTBREQ_SOFTBREQ(x) ((x) << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT)
/* --- GPDMA_SOFTSREQ values ------------------------------------ */
/* SOFTSREQ: Software single transfer request flags for each of 16 possible
sources */
#define GPDMA_SOFTSREQ_SOFTSREQ_SHIFT (0)
#define GPDMA_SOFTSREQ_SOFTSREQ_MASK (0xffff << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT)
#define GPDMA_SOFTSREQ_SOFTSREQ(x) ((x) << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT)
/* --- GPDMA_SOFTLBREQ values ----------------------------------- */
/* SOFTLBREQ: Software last burst request flags for each of 16 possible
sources */
#define GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT (0)
#define GPDMA_SOFTLBREQ_SOFTLBREQ_MASK \
(0xffff << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT)
#define GPDMA_SOFTLBREQ_SOFTLBREQ(x) \
((x) << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT)
/* --- GPDMA_SOFTLSREQ values ----------------------------------- */
/* SOFTLSREQ: Software last single transfer request flags for each of 16
possible sources */
#define GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT (0)
#define GPDMA_SOFTLSREQ_SOFTLSREQ_MASK \
(0xffff << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT)
#define GPDMA_SOFTLSREQ_SOFTLSREQ(x) \
((x) << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT)
/* --- GPDMA_CONFIG values -------------------------------------- */
/* E: DMA Controller enable */
#define GPDMA_CONFIG_E_SHIFT (0)
#define GPDMA_CONFIG_E_MASK (0x1 << GPDMA_CONFIG_E_SHIFT)
#define GPDMA_CONFIG_E(x) ((x) << GPDMA_CONFIG_E_SHIFT)
/* M0: AHB Master 0 endianness configuration */
#define GPDMA_CONFIG_M0_SHIFT (1)
#define GPDMA_CONFIG_M0_MASK (0x1 << GPDMA_CONFIG_M0_SHIFT)
#define GPDMA_CONFIG_M0(x) ((x) << GPDMA_CONFIG_M0_SHIFT)
/* M1: AHB Master 1 endianness configuration */
#define GPDMA_CONFIG_M1_SHIFT (2)
#define GPDMA_CONFIG_M1_MASK (0x1 << GPDMA_CONFIG_M1_SHIFT)
#define GPDMA_CONFIG_M1(x) ((x) << GPDMA_CONFIG_M1_SHIFT)
/* --- GPDMA_SYNC values ---------------------------------------- */
/* DMACSYNC: Controls the synchronization logic for DMA request signals */
#define GPDMA_SYNC_DMACSYNC_SHIFT (0)
#define GPDMA_SYNC_DMACSYNC_MASK (0xffff << GPDMA_SYNC_DMACSYNC_SHIFT)
#define GPDMA_SYNC_DMACSYNC(x) ((x) << GPDMA_SYNC_DMACSYNC_SHIFT)
/* --- GPDMA_C[0..7]SRCADDR values ----------------------------------- */
/* SRCADDR: DMA source address */
#define GPDMA_CxSRCADDR_SRCADDR_SHIFT (0)
#define GPDMA_CxSRCADDR_SRCADDR_MASK \
(0xffffffff << GPDMA_CxSRCADDR_SRCADDR_SHIFT)
#define GPDMA_CxSRCADDR_SRCADDR(x) ((x) << GPDMA_CxSRCADDR_SRCADDR_SHIFT)
/* --- GPDMA_C[0..7]DESTADDR values ---------------------------------- */
/* DESTADDR: DMA source address */
#define GPDMA_CxDESTADDR_DESTADDR_SHIFT (0)
#define GPDMA_CxDESTADDR_DESTADDR_MASK \
(0xffffffff << GPDMA_CxDESTADDR_DESTADDR_SHIFT)
#define GPDMA_CxDESTADDR_DESTADDR(x) ((x) << GPDMA_CxDESTADDR_DESTADDR_SHIFT)
/* --- GPDMA_C[0..7]LLI values --------------------------------------- */
/* LM: AHB master select for loading the next LLI */
#define GPDMA_CxLLI_LM_SHIFT (0)
#define GPDMA_CxLLI_LM_MASK (0x1 << GPDMA_CxLLI_LM_SHIFT)
#define GPDMA_CxLLI_LM(x) ((x) << GPDMA_CxLLI_LM_SHIFT)
/* LLI: Linked list item */
#define GPDMA_CxLLI_LLI_SHIFT (2)
#define GPDMA_CxLLI_LLI_MASK (0x3fffffff << GPDMA_CxLLI_LLI_SHIFT)
#define GPDMA_CxLLI_LLI(x) ((x) << GPDMA_CxLLI_LLI_SHIFT)
/* --- GPDMA_C[0..7]CONTROL values ----------------------------------- */
/* TRANSFERSIZE: Transfer size in number of transfers */
#define GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT (0)
#define GPDMA_CxCONTROL_TRANSFERSIZE_MASK \
(0xfff << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT)
#define GPDMA_CxCONTROL_TRANSFERSIZE(x) \
((x) << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT)
/* SBSIZE: Source burst size */
#define GPDMA_CxCONTROL_SBSIZE_SHIFT (12)
#define GPDMA_CxCONTROL_SBSIZE_MASK (0x7 << GPDMA_CxCONTROL_SBSIZE_SHIFT)
#define GPDMA_CxCONTROL_SBSIZE(x) ((x) << GPDMA_CxCONTROL_SBSIZE_SHIFT)
/* DBSIZE: Destination burst size */
#define GPDMA_CxCONTROL_DBSIZE_SHIFT (15)
#define GPDMA_CxCONTROL_DBSIZE_MASK (0x7 << GPDMA_CxCONTROL_DBSIZE_SHIFT)
#define GPDMA_CxCONTROL_DBSIZE(x) ((x) << GPDMA_CxCONTROL_DBSIZE_SHIFT)
/* SWIDTH: Source transfer width */
#define GPDMA_CxCONTROL_SWIDTH_SHIFT (18)
#define GPDMA_CxCONTROL_SWIDTH_MASK (0x7 << GPDMA_CxCONTROL_SWIDTH_SHIFT)
#define GPDMA_CxCONTROL_SWIDTH(x) ((x) << GPDMA_CxCONTROL_SWIDTH_SHIFT)
/* DWIDTH: Destination transfer width */
#define GPDMA_CxCONTROL_DWIDTH_SHIFT (21)
#define GPDMA_CxCONTROL_DWIDTH_MASK (0x7 << GPDMA_CxCONTROL_DWIDTH_SHIFT)
#define GPDMA_CxCONTROL_DWIDTH(x) ((x) << GPDMA_CxCONTROL_DWIDTH_SHIFT)
/* S: Source AHB master select */
#define GPDMA_CxCONTROL_S_SHIFT (24)
#define GPDMA_CxCONTROL_S_MASK (0x1 << GPDMA_CxCONTROL_S_SHIFT)
#define GPDMA_CxCONTROL_S(x) ((x) << GPDMA_CxCONTROL_S_SHIFT)
/* D: Destination AHB master select */
#define GPDMA_CxCONTROL_D_SHIFT (25)
#define GPDMA_CxCONTROL_D_MASK (0x1 << GPDMA_CxCONTROL_D_SHIFT)
#define GPDMA_CxCONTROL_D(x) ((x) << GPDMA_CxCONTROL_D_SHIFT)
/* SI: Source increment */
#define GPDMA_CxCONTROL_SI_SHIFT (26)
#define GPDMA_CxCONTROL_SI_MASK (0x1 << GPDMA_CxCONTROL_SI_SHIFT)
#define GPDMA_Cx0CONTROL_SI(x) ((x) << GPDMA_CxCONTROL_SI_SHIFT)
/* DI: Destination increment */
#define GPDMA_CxCONTROL_DI_SHIFT (27)
#define GPDMA_CxCONTROL_DI_MASK (0x1 << GPDMA_CxCONTROL_DI_SHIFT)
#define GPDMA_CxCONTROL_DI(x) ((x) << GPDMA_CxCONTROL_DI_SHIFT)
/* PROT1: This information is provided to the peripheral during a DMA bus
access and indicates that the access is in user mode or privileged mode */
#define GPDMA_CxCONTROL_PROT1_SHIFT (28)
#define GPDMA_CxCONTROL_PROT1_MASK (0x1 << GPDMA_CxCONTROL_PROT1_SHIFT)
#define GPDMA_CxCONTROL_PROT1(x) ((x) << GPDMA_CxCONTROL_PROT1_SHIFT)
/* PROT2: This information is provided to the peripheral during a DMA bus
access and indicates to the peripheral that the access is bufferable or not
bufferable */
#define GPDMA_CxCONTROL_PROT2_SHIFT (29)
#define GPDMA_CxCONTROL_PROT2_MASK (0x1 << GPDMA_CxCONTROL_PROT2_SHIFT)
#define GPDMA_CxCONTROL_PROT2(x) ((x) << GPDMA_CxCONTROL_PROT2_SHIFT)
/* PROT3: This information is provided to the peripheral during a DMA bus
access and indicates to the peripheral that the access is cacheable or not
cacheable */
#define GPDMA_CxCONTROL_PROT3_SHIFT (30)
#define GPDMA_CxCONTROL_PROT3_MASK (0x1 << GPDMA_CxCONTROL_PROT3_SHIFT)
#define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT)
/* I: Terminal count interrupt enable bit */
#define GPDMA_CxCONTROL_I_SHIFT (31)
#define GPDMA_CxCONTROL_I_MASK (0x1 << GPDMA_CxCONTROL_I_SHIFT)
#define GPDMA_CxCONTROL_I(x) ((x) << GPDMA_CxCONTROL_I_SHIFT)
/* --- GPDMA_C[0..7]CONFIG values ------------------------------------ */
/* E: Channel enable */
#define GPDMA_CxCONFIG_E_SHIFT (0)
#define GPDMA_CxCONFIG_E_MASK (0x1 << GPDMA_CxCONFIG_E_SHIFT)
#define GPDMA_CxCONFIG_E(x) ((x) << GPDMA_CxCONFIG_E_SHIFT)
/* SRCPERIPHERAL: Source peripheral */
#define GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT (1)
#define GPDMA_CxCONFIG_SRCPERIPHERAL_MASK \
(0x1f << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT)
#define GPDMA_CxCONFIG_SRCPERIPHERAL(x) \
((x) << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT)
/* DESTPERIPHERAL: Destination peripheral */
#define GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT (6)
#define GPDMA_CxCONFIG_DESTPERIPHERAL_MASK \
(0x1f << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT)
#define GPDMA_CxCONFIG_DESTPERIPHERAL(x) \
((x) << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT)
/* FLOWCNTRL: Flow control and transfer type */
#define GPDMA_CxCONFIG_FLOWCNTRL_SHIFT (11)
#define GPDMA_CxCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT)
#define GPDMA_CxCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT)
/* IE: Interrupt error mask */
#define GPDMA_CxCONFIG_IE_SHIFT (14)
#define GPDMA_CxCONFIG_IE_MASK (0x1 << GPDMA_CxCONFIG_IE_SHIFT)
#define GPDMA_CxCONFIG_IE(x) ((x) << GPDMA_CxCONFIG_IE_SHIFT)
/* ITC: Terminal count interrupt mask */
#define GPDMA_CxCONFIG_ITC_SHIFT (15)
#define GPDMA_CxCONFIG_ITC_MASK (0x1 << GPDMA_CxCONFIG_ITC_SHIFT)
#define GPDMA_CxCONFIG_ITC(x) ((x) << GPDMA_CxCONFIG_ITC_SHIFT)
/* L: Lock */
#define GPDMA_CxCONFIG_L_SHIFT (16)
#define GPDMA_CxCONFIG_L_MASK (0x1 << GPDMA_CxCONFIG_L_SHIFT)
#define GPDMA_CxCONFIG_L(x) ((x) << GPDMA_CxCONFIG_L_SHIFT)
/* A: Active */
#define GPDMA_CxCONFIG_A_SHIFT (17)
#define GPDMA_CxCONFIG_A_MASK (0x1 << GPDMA_CxCONFIG_A_SHIFT)
#define GPDMA_CxCONFIG_A(x) ((x) << GPDMA_CxCONFIG_A_SHIFT)
/* H: Halt */
#define GPDMA_CxCONFIG_H_SHIFT (18)
#define GPDMA_CxCONFIG_H_MASK (0x1 << GPDMA_CxCONFIG_H_SHIFT)
#define GPDMA_CxCONFIG_H(x) ((x) << GPDMA_CxCONFIG_H_SHIFT)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/lpc43xx/gpio.h Normal file
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@ -0,0 +1,797 @@
/** @defgroup gpio_defines General Purpose I/O Defines
@brief <b>Defined Constants and Types for the LPC43xx General Purpose I/O</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@author @htmlonly &copy; @endhtmlonly 2014 Jared Boone <jared@sharebrained.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2014 Jared Boone <jared@sharebrained.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_GPIO_H
#define LPC43XX_GPIO_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
#define GPIO0 (GPIO_PORT_BASE + 0x2000)
#define GPIO1 (GPIO_PORT_BASE + 0x2004)
#define GPIO2 (GPIO_PORT_BASE + 0x2008)
#define GPIO3 (GPIO_PORT_BASE + 0x200C)
#define GPIO4 (GPIO_PORT_BASE + 0x2010)
#define GPIO5 (GPIO_PORT_BASE + 0x2014)
#define GPIO6 (GPIO_PORT_BASE + 0x2018)
#define GPIO7 (GPIO_PORT_BASE + 0x201C)
/* GPIO number definitions (for convenience) */
#define GPIOPIN0 (1 << 0)
#define GPIOPIN1 (1 << 1)
#define GPIOPIN2 (1 << 2)
#define GPIOPIN3 (1 << 3)
#define GPIOPIN4 (1 << 4)
#define GPIOPIN5 (1 << 5)
#define GPIOPIN6 (1 << 6)
#define GPIOPIN7 (1 << 7)
#define GPIOPIN8 (1 << 8)
#define GPIOPIN9 (1 << 9)
#define GPIOPIN10 (1 << 10)
#define GPIOPIN11 (1 << 11)
#define GPIOPIN12 (1 << 12)
#define GPIOPIN13 (1 << 13)
#define GPIOPIN14 (1 << 14)
#define GPIOPIN15 (1 << 15)
#define GPIOPIN16 (1 << 16)
#define GPIOPIN17 (1 << 17)
#define GPIOPIN18 (1 << 18)
#define GPIOPIN19 (1 << 19)
#define GPIOPIN20 (1 << 20)
#define GPIOPIN21 (1 << 21)
#define GPIOPIN22 (1 << 22)
#define GPIOPIN23 (1 << 23)
#define GPIOPIN24 (1 << 24)
#define GPIOPIN25 (1 << 25)
#define GPIOPIN26 (1 << 26)
#define GPIOPIN27 (1 << 27)
#define GPIOPIN28 (1 << 28)
#define GPIOPIN29 (1 << 29)
#define GPIOPIN30 (1 << 30)
#define GPIOPIN31 (1 << 31)
/* --- GPIO registers ------------------------------------------------------ */
/* GPIO pin interrupts */
/* Pin Interrupt Mode register */
#define GPIO_PIN_INTERRUPT_ISEL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x000)
/* Pin interrupt level (rising edge) interrupt enable register */
#define GPIO_PIN_INTERRUPT_IENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x004)
/* Pin interrupt level (rising edge) interrupt set register */
#define GPIO_PIN_INTERRUPT_SIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x008)
/* Pin interrupt level (rising edge interrupt) clear register */
#define GPIO_PIN_INTERRUPT_CIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x00C)
/* Pin interrupt active level (falling edge) interrupt enable register */
#define GPIO_PIN_INTERRUPT_IENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x010)
/* Pin interrupt active level (falling edge) interrupt set register */
#define GPIO_PIN_INTERRUPT_SIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x014)
/* Pin interrupt active level (falling edge) interrupt clear register */
#define GPIO_PIN_INTERRUPT_CIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x018)
/* Pin interrupt rising edge register */
#define GPIO_PIN_INTERRUPT_RISE MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x01C)
/* Pin interrupt falling edge register */
#define GPIO_PIN_INTERRUPT_FALL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x020)
/* Pin interrupt status register */
#define GPIO_PIN_INTERRUPT_IST MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x024)
/* GPIO GROUP0 interrupt */
/* GPIO grouped interrupt control register */
#define GPIO_GROUP0_INTERRUPT_CTRL \
MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x000)
/* GPIO grouped interrupt port [0..7] polarity register */
#define GPIO_GROUP0_INTERRUPT_PORT_POL(x) \
MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020 + ((x)*4))
/* GPIO grouped interrupt port [0..7] enable register */
#define GPIO_GROUP0_INTERRUPT_PORT_ENA(x) \
MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040 + ((x)*4))
/* GPIO GROUP1 interrupt */
/* GPIO grouped interrupt control register */
#define GPIO_GROUP1_INTERRUPT_CTRL \
MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x000)
/* GPIO grouped interrupt port [0..7] polarity register */
#define GPIO_GROUP1_INTERRUPT_PORT_POL(x) \
MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020 + ((x)*4))
/* GPIO grouped interrupt port [0..7] enable register */
#define GPIO_GROUP1_INTERRUPT_PORT_ENA(x) \
MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040 + ((x)*4))
/* Byte pin registers port 0; pins PIO0_0 to PIO0_31 (R/W) */
#define GPIO_B0 (GPIO_PORT_BASE + 0x0000)
#define GPIO_B1 (GPIO_PORT_BASE + 0x0001)
#define GPIO_B2 (GPIO_PORT_BASE + 0x0002)
#define GPIO_B3 (GPIO_PORT_BASE + 0x0003)
#define GPIO_B4 (GPIO_PORT_BASE + 0x0004)
#define GPIO_B5 (GPIO_PORT_BASE + 0x0005)
#define GPIO_B6 (GPIO_PORT_BASE + 0x0006)
#define GPIO_B7 (GPIO_PORT_BASE + 0x0007)
#define GPIO_B8 (GPIO_PORT_BASE + 0x0008)
#define GPIO_B9 (GPIO_PORT_BASE + 0x0009)
#define GPIO_B10 (GPIO_PORT_BASE + 0x000A)
#define GPIO_B11 (GPIO_PORT_BASE + 0x000B)
#define GPIO_B12 (GPIO_PORT_BASE + 0x000C)
#define GPIO_B13 (GPIO_PORT_BASE + 0x000D)
#define GPIO_B14 (GPIO_PORT_BASE + 0x000E)
#define GPIO_B15 (GPIO_PORT_BASE + 0x000F)
#define GPIO_B16 (GPIO_PORT_BASE + 0x0010)
#define GPIO_B17 (GPIO_PORT_BASE + 0x0011)
#define GPIO_B18 (GPIO_PORT_BASE + 0x0012)
#define GPIO_B19 (GPIO_PORT_BASE + 0x0013)
#define GPIO_B20 (GPIO_PORT_BASE + 0x0014)
#define GPIO_B21 (GPIO_PORT_BASE + 0x0015)
#define GPIO_B22 (GPIO_PORT_BASE + 0x0016)
#define GPIO_B23 (GPIO_PORT_BASE + 0x0017)
#define GPIO_B24 (GPIO_PORT_BASE + 0x0018)
#define GPIO_B25 (GPIO_PORT_BASE + 0x0019)
#define GPIO_B26 (GPIO_PORT_BASE + 0x001A)
#define GPIO_B27 (GPIO_PORT_BASE + 0x001B)
#define GPIO_B28 (GPIO_PORT_BASE + 0x001C)
#define GPIO_B29 (GPIO_PORT_BASE + 0x001D)
#define GPIO_B30 (GPIO_PORT_BASE + 0x001E)
#define GPIO_B31 (GPIO_PORT_BASE + 0x001F)
/* Byte pin registers port 1 (R/W) */
#define GPIO_B32 (GPIO_PORT_BASE + 0x0020)
#define GPIO_B33 (GPIO_PORT_BASE + 0x0021)
#define GPIO_B34 (GPIO_PORT_BASE + 0x0022)
#define GPIO_B35 (GPIO_PORT_BASE + 0x0023)
#define GPIO_B36 (GPIO_PORT_BASE + 0x0024)
#define GPIO_B37 (GPIO_PORT_BASE + 0x0025)
#define GPIO_B38 (GPIO_PORT_BASE + 0x0026)
#define GPIO_B39 (GPIO_PORT_BASE + 0x0027)
#define GPIO_B40 (GPIO_PORT_BASE + 0x0028)
#define GPIO_B41 (GPIO_PORT_BASE + 0x0029)
#define GPIO_B42 (GPIO_PORT_BASE + 0x002A)
#define GPIO_B43 (GPIO_PORT_BASE + 0x002B)
#define GPIO_B44 (GPIO_PORT_BASE + 0x002C)
#define GPIO_B45 (GPIO_PORT_BASE + 0x002D)
#define GPIO_B46 (GPIO_PORT_BASE + 0x002E)
#define GPIO_B47 (GPIO_PORT_BASE + 0x002F)
#define GPIO_B48 (GPIO_PORT_BASE + 0x0030)
#define GPIO_B49 (GPIO_PORT_BASE + 0x0031)
#define GPIO_B50 (GPIO_PORT_BASE + 0x0032)
#define GPIO_B51 (GPIO_PORT_BASE + 0x0033)
#define GPIO_B52 (GPIO_PORT_BASE + 0x0034)
#define GPIO_B53 (GPIO_PORT_BASE + 0x0035)
#define GPIO_B54 (GPIO_PORT_BASE + 0x0036)
#define GPIO_B55 (GPIO_PORT_BASE + 0x0037)
#define GPIO_B56 (GPIO_PORT_BASE + 0x0038)
#define GPIO_B57 (GPIO_PORT_BASE + 0x0039)
#define GPIO_B58 (GPIO_PORT_BASE + 0x003A)
#define GPIO_B59 (GPIO_PORT_BASE + 0x003B)
#define GPIO_B60 (GPIO_PORT_BASE + 0x003C)
#define GPIO_B61 (GPIO_PORT_BASE + 0x003D)
#define GPIO_B62 (GPIO_PORT_BASE + 0x003E)
#define GPIO_B63 (GPIO_PORT_BASE + 0x003F)
/* Byte pin registers port 2 (R/W) */
#define GPIO_B64 (GPIO_PORT_BASE + 0x0040)
#define GPIO_B65 (GPIO_PORT_BASE + 0x0041)
#define GPIO_B66 (GPIO_PORT_BASE + 0x0042)
#define GPIO_B67 (GPIO_PORT_BASE + 0x0043)
#define GPIO_B68 (GPIO_PORT_BASE + 0x0044)
#define GPIO_B69 (GPIO_PORT_BASE + 0x0045)
#define GPIO_B70 (GPIO_PORT_BASE + 0x0046)
#define GPIO_B71 (GPIO_PORT_BASE + 0x0047)
#define GPIO_B72 (GPIO_PORT_BASE + 0x0048)
#define GPIO_B73 (GPIO_PORT_BASE + 0x0049)
#define GPIO_B74 (GPIO_PORT_BASE + 0x004A)
#define GPIO_B75 (GPIO_PORT_BASE + 0x004B)
#define GPIO_B76 (GPIO_PORT_BASE + 0x004C)
#define GPIO_B77 (GPIO_PORT_BASE + 0x004D)
#define GPIO_B78 (GPIO_PORT_BASE + 0x004E)
#define GPIO_B79 (GPIO_PORT_BASE + 0x004F)
#define GPIO_B80 (GPIO_PORT_BASE + 0x0050)
#define GPIO_B81 (GPIO_PORT_BASE + 0x0051)
#define GPIO_B82 (GPIO_PORT_BASE + 0x0052)
#define GPIO_B83 (GPIO_PORT_BASE + 0x0053)
#define GPIO_B84 (GPIO_PORT_BASE + 0x0054)
#define GPIO_B85 (GPIO_PORT_BASE + 0x0055)
#define GPIO_B86 (GPIO_PORT_BASE + 0x0056)
#define GPIO_B87 (GPIO_PORT_BASE + 0x0057)
#define GPIO_B88 (GPIO_PORT_BASE + 0x0058)
#define GPIO_B89 (GPIO_PORT_BASE + 0x0059)
#define GPIO_B90 (GPIO_PORT_BASE + 0x005A)
#define GPIO_B91 (GPIO_PORT_BASE + 0x005B)
#define GPIO_B92 (GPIO_PORT_BASE + 0x005C)
#define GPIO_B93 (GPIO_PORT_BASE + 0x005D)
#define GPIO_B94 (GPIO_PORT_BASE + 0x005E)
#define GPIO_B95 (GPIO_PORT_BASE + 0x005F)
/* Byte pin registers port 3 (R/W) */
#define GPIO_B96 (GPIO_PORT_BASE + 0x0060)
#define GPIO_B97 (GPIO_PORT_BASE + 0x0061)
#define GPIO_B98 (GPIO_PORT_BASE + 0x0062)
#define GPIO_B99 (GPIO_PORT_BASE + 0x0063)
#define GPIO_B100 (GPIO_PORT_BASE + 0x0064)
#define GPIO_B101 (GPIO_PORT_BASE + 0x0065)
#define GPIO_B102 (GPIO_PORT_BASE + 0x0066)
#define GPIO_B103 (GPIO_PORT_BASE + 0x0067)
#define GPIO_B104 (GPIO_PORT_BASE + 0x0068)
#define GPIO_B105 (GPIO_PORT_BASE + 0x0069)
#define GPIO_B106 (GPIO_PORT_BASE + 0x006A)
#define GPIO_B107 (GPIO_PORT_BASE + 0x006B)
#define GPIO_B108 (GPIO_PORT_BASE + 0x006C)
#define GPIO_B109 (GPIO_PORT_BASE + 0x006D)
#define GPIO_B110 (GPIO_PORT_BASE + 0x006E)
#define GPIO_B111 (GPIO_PORT_BASE + 0x006F)
#define GPIO_B112 (GPIO_PORT_BASE + 0x0070)
#define GPIO_B113 (GPIO_PORT_BASE + 0x0071)
#define GPIO_B114 (GPIO_PORT_BASE + 0x0072)
#define GPIO_B115 (GPIO_PORT_BASE + 0x0073)
#define GPIO_B116 (GPIO_PORT_BASE + 0x0074)
#define GPIO_B117 (GPIO_PORT_BASE + 0x0075)
#define GPIO_B118 (GPIO_PORT_BASE + 0x0076)
#define GPIO_B119 (GPIO_PORT_BASE + 0x0077)
#define GPIO_B120 (GPIO_PORT_BASE + 0x0078)
#define GPIO_B121 (GPIO_PORT_BASE + 0x0079)
#define GPIO_B122 (GPIO_PORT_BASE + 0x007A)
#define GPIO_B123 (GPIO_PORT_BASE + 0x007B)
#define GPIO_B124 (GPIO_PORT_BASE + 0x007C)
#define GPIO_B125 (GPIO_PORT_BASE + 0x007D)
#define GPIO_B126 (GPIO_PORT_BASE + 0x007E)
#define GPIO_B127 (GPIO_PORT_BASE + 0x007F)
/* Byte pin registers port 4 (R/W) */
#define GPIO_B128 (GPIO_PORT_BASE + 0x0080)
#define GPIO_B129 (GPIO_PORT_BASE + 0x0081)
#define GPIO_B130 (GPIO_PORT_BASE + 0x0082)
#define GPIO_B131 (GPIO_PORT_BASE + 0x0083)
#define GPIO_B132 (GPIO_PORT_BASE + 0x0084)
#define GPIO_B133 (GPIO_PORT_BASE + 0x0085)
#define GPIO_B134 (GPIO_PORT_BASE + 0x0086)
#define GPIO_B135 (GPIO_PORT_BASE + 0x0087)
#define GPIO_B136 (GPIO_PORT_BASE + 0x0088)
#define GPIO_B137 (GPIO_PORT_BASE + 0x0089)
#define GPIO_B138 (GPIO_PORT_BASE + 0x008A)
#define GPIO_B139 (GPIO_PORT_BASE + 0x008B)
#define GPIO_B140 (GPIO_PORT_BASE + 0x008C)
#define GPIO_B141 (GPIO_PORT_BASE + 0x008D)
#define GPIO_B142 (GPIO_PORT_BASE + 0x008E)
#define GPIO_B143 (GPIO_PORT_BASE + 0x008F)
#define GPIO_B144 (GPIO_PORT_BASE + 0x0090)
#define GPIO_B145 (GPIO_PORT_BASE + 0x0091)
#define GPIO_B146 (GPIO_PORT_BASE + 0x0092)
#define GPIO_B147 (GPIO_PORT_BASE + 0x0093)
#define GPIO_B148 (GPIO_PORT_BASE + 0x0094)
#define GPIO_B149 (GPIO_PORT_BASE + 0x0095)
#define GPIO_B150 (GPIO_PORT_BASE + 0x0096)
#define GPIO_B151 (GPIO_PORT_BASE + 0x0097)
#define GPIO_B152 (GPIO_PORT_BASE + 0x0098)
#define GPIO_B153 (GPIO_PORT_BASE + 0x0099)
#define GPIO_B154 (GPIO_PORT_BASE + 0x009A)
#define GPIO_B155 (GPIO_PORT_BASE + 0x009B)
#define GPIO_B156 (GPIO_PORT_BASE + 0x009C)
#define GPIO_B157 (GPIO_PORT_BASE + 0x009D)
#define GPIO_B158 (GPIO_PORT_BASE + 0x009E)
#define GPIO_B159 (GPIO_PORT_BASE + 0x009F)
/* Byte pin registers port 5 (R/W) */
#define GPIO_B160 (GPIO_PORT_BASE + 0x00A0)
#define GPIO_B161 (GPIO_PORT_BASE + 0x00A1)
#define GPIO_B162 (GPIO_PORT_BASE + 0x00A2)
#define GPIO_B163 (GPIO_PORT_BASE + 0x00A3)
#define GPIO_B164 (GPIO_PORT_BASE + 0x00A4)
#define GPIO_B165 (GPIO_PORT_BASE + 0x00A5)
#define GPIO_B166 (GPIO_PORT_BASE + 0x00A6)
#define GPIO_B167 (GPIO_PORT_BASE + 0x00A7)
#define GPIO_B168 (GPIO_PORT_BASE + 0x00A8)
#define GPIO_B169 (GPIO_PORT_BASE + 0x00A9)
#define GPIO_B170 (GPIO_PORT_BASE + 0x00AA)
#define GPIO_B171 (GPIO_PORT_BASE + 0x00AB)
#define GPIO_B172 (GPIO_PORT_BASE + 0x00AC)
#define GPIO_B173 (GPIO_PORT_BASE + 0x00AD)
#define GPIO_B174 (GPIO_PORT_BASE + 0x00AE)
#define GPIO_B175 (GPIO_PORT_BASE + 0x00AF)
#define GPIO_B176 (GPIO_PORT_BASE + 0x00B0)
#define GPIO_B177 (GPIO_PORT_BASE + 0x00B1)
#define GPIO_B178 (GPIO_PORT_BASE + 0x00B2)
#define GPIO_B179 (GPIO_PORT_BASE + 0x00B3)
#define GPIO_B180 (GPIO_PORT_BASE + 0x00B4)
#define GPIO_B181 (GPIO_PORT_BASE + 0x00B5)
#define GPIO_B182 (GPIO_PORT_BASE + 0x00B6)
#define GPIO_B183 (GPIO_PORT_BASE + 0x00B7)
#define GPIO_B184 (GPIO_PORT_BASE + 0x00B8)
#define GPIO_B185 (GPIO_PORT_BASE + 0x00B9)
#define GPIO_B186 (GPIO_PORT_BASE + 0x00BA)
#define GPIO_B187 (GPIO_PORT_BASE + 0x00BB)
#define GPIO_B188 (GPIO_PORT_BASE + 0x00BC)
#define GPIO_B189 (GPIO_PORT_BASE + 0x00BD)
#define GPIO_B190 (GPIO_PORT_BASE + 0x00BE)
#define GPIO_B191 (GPIO_PORT_BASE + 0x00BF)
/* Byte pin registers port 6 (R/W) */
#define GPIO_B192 (GPIO_PORT_BASE + 0x00C0)
#define GPIO_B193 (GPIO_PORT_BASE + 0x00C1)
#define GPIO_B194 (GPIO_PORT_BASE + 0x00C2)
#define GPIO_B195 (GPIO_PORT_BASE + 0x00C3)
#define GPIO_B196 (GPIO_PORT_BASE + 0x00C4)
#define GPIO_B197 (GPIO_PORT_BASE + 0x00C5)
#define GPIO_B198 (GPIO_PORT_BASE + 0x00C6)
#define GPIO_B199 (GPIO_PORT_BASE + 0x00C7)
#define GPIO_B200 (GPIO_PORT_BASE + 0x00C8)
#define GPIO_B201 (GPIO_PORT_BASE + 0x00C9)
#define GPIO_B202 (GPIO_PORT_BASE + 0x00CA)
#define GPIO_B203 (GPIO_PORT_BASE + 0x00CB)
#define GPIO_B204 (GPIO_PORT_BASE + 0x00CC)
#define GPIO_B205 (GPIO_PORT_BASE + 0x00CD)
#define GPIO_B206 (GPIO_PORT_BASE + 0x00CE)
#define GPIO_B207 (GPIO_PORT_BASE + 0x00CF)
#define GPIO_B208 (GPIO_PORT_BASE + 0x00D0)
#define GPIO_B209 (GPIO_PORT_BASE + 0x00D1)
#define GPIO_B210 (GPIO_PORT_BASE + 0x00D2)
#define GPIO_B211 (GPIO_PORT_BASE + 0x00D3)
#define GPIO_B212 (GPIO_PORT_BASE + 0x00D4)
#define GPIO_B213 (GPIO_PORT_BASE + 0x00D5)
#define GPIO_B214 (GPIO_PORT_BASE + 0x00D6)
#define GPIO_B215 (GPIO_PORT_BASE + 0x00D7)
#define GPIO_B216 (GPIO_PORT_BASE + 0x00D8)
#define GPIO_B217 (GPIO_PORT_BASE + 0x00D9)
#define GPIO_B218 (GPIO_PORT_BASE + 0x00DA)
#define GPIO_B219 (GPIO_PORT_BASE + 0x00DB)
#define GPIO_B220 (GPIO_PORT_BASE + 0x00DC)
#define GPIO_B221 (GPIO_PORT_BASE + 0x00DD)
#define GPIO_B222 (GPIO_PORT_BASE + 0x00DE)
#define GPIO_B223 (GPIO_PORT_BASE + 0x00DF)
/* Byte pin registers port 7 (R/W) */
#define GPIO_B224 (GPIO_PORT_BASE + 0x00E0)
#define GPIO_B225 (GPIO_PORT_BASE + 0x00E1)
#define GPIO_B226 (GPIO_PORT_BASE + 0x00E2)
#define GPIO_B227 (GPIO_PORT_BASE + 0x00E3)
#define GPIO_B228 (GPIO_PORT_BASE + 0x00E4)
#define GPIO_B229 (GPIO_PORT_BASE + 0x00E5)
#define GPIO_B230 (GPIO_PORT_BASE + 0x00E6)
#define GPIO_B231 (GPIO_PORT_BASE + 0x00E7)
#define GPIO_B232 (GPIO_PORT_BASE + 0x00E8)
#define GPIO_B233 (GPIO_PORT_BASE + 0x00E9)
#define GPIO_B234 (GPIO_PORT_BASE + 0x00EA)
#define GPIO_B235 (GPIO_PORT_BASE + 0x00EB)
#define GPIO_B236 (GPIO_PORT_BASE + 0x00EC)
#define GPIO_B237 (GPIO_PORT_BASE + 0x00ED)
#define GPIO_B238 (GPIO_PORT_BASE + 0x00EE)
#define GPIO_B239 (GPIO_PORT_BASE + 0x00EF)
#define GPIO_B240 (GPIO_PORT_BASE + 0x00F0)
#define GPIO_B241 (GPIO_PORT_BASE + 0x00F1)
#define GPIO_B242 (GPIO_PORT_BASE + 0x00F2)
#define GPIO_B243 (GPIO_PORT_BASE + 0x00F3)
#define GPIO_B244 (GPIO_PORT_BASE + 0x00F4)
#define GPIO_B245 (GPIO_PORT_BASE + 0x00F5)
#define GPIO_B246 (GPIO_PORT_BASE + 0x00F6)
#define GPIO_B247 (GPIO_PORT_BASE + 0x00F7)
#define GPIO_B248 (GPIO_PORT_BASE + 0x00F8)
#define GPIO_B249 (GPIO_PORT_BASE + 0x00F9)
#define GPIO_B250 (GPIO_PORT_BASE + 0x00FA)
#define GPIO_B251 (GPIO_PORT_BASE + 0x00FB)
#define GPIO_B252 (GPIO_PORT_BASE + 0x00FC)
#define GPIO_B253 (GPIO_PORT_BASE + 0x00FD)
#define GPIO_B254 (GPIO_PORT_BASE + 0x00FE)
#define GPIO_B255 (GPIO_PORT_BASE + 0x00FF)
/* Word pin registers port 0 (R/W) */
#define GPIO_W0 (GPIO_PORT_BASE + 0x1000)
#define GPIO_W1 (GPIO_PORT_BASE + 0x1004)
#define GPIO_W2 (GPIO_PORT_BASE + 0x1008)
#define GPIO_W3 (GPIO_PORT_BASE + 0x100C)
#define GPIO_W4 (GPIO_PORT_BASE + 0x1010)
#define GPIO_W5 (GPIO_PORT_BASE + 0x1014)
#define GPIO_W6 (GPIO_PORT_BASE + 0x1018)
#define GPIO_W7 (GPIO_PORT_BASE + 0x101C)
#define GPIO_W8 (GPIO_PORT_BASE + 0x1020)
#define GPIO_W9 (GPIO_PORT_BASE + 0x1024)
#define GPIO_W10 (GPIO_PORT_BASE + 0x1028)
#define GPIO_W11 (GPIO_PORT_BASE + 0x102C)
#define GPIO_W12 (GPIO_PORT_BASE + 0x1030)
#define GPIO_W13 (GPIO_PORT_BASE + 0x1034)
#define GPIO_W14 (GPIO_PORT_BASE + 0x1038)
#define GPIO_W15 (GPIO_PORT_BASE + 0x103C)
#define GPIO_W16 (GPIO_PORT_BASE + 0x1040)
#define GPIO_W17 (GPIO_PORT_BASE + 0x1044)
#define GPIO_W18 (GPIO_PORT_BASE + 0x1048)
#define GPIO_W19 (GPIO_PORT_BASE + 0x104C)
#define GPIO_W20 (GPIO_PORT_BASE + 0x1050)
#define GPIO_W21 (GPIO_PORT_BASE + 0x1054)
#define GPIO_W22 (GPIO_PORT_BASE + 0x1058)
#define GPIO_W23 (GPIO_PORT_BASE + 0x105C)
#define GPIO_W24 (GPIO_PORT_BASE + 0x1060)
#define GPIO_W25 (GPIO_PORT_BASE + 0x1064)
#define GPIO_W26 (GPIO_PORT_BASE + 0x1068)
#define GPIO_W27 (GPIO_PORT_BASE + 0x106C)
#define GPIO_W28 (GPIO_PORT_BASE + 0x1070)
#define GPIO_W29 (GPIO_PORT_BASE + 0x1074)
#define GPIO_W30 (GPIO_PORT_BASE + 0x1078)
#define GPIO_W31 (GPIO_PORT_BASE + 0x107C)
/* Word pin registers port 1 (R/W) */
#define GPIO_W32 (GPIO_PORT_BASE + 0x1080)
#define GPIO_W33 (GPIO_PORT_BASE + 0x1084)
#define GPIO_W34 (GPIO_PORT_BASE + 0x1088)
#define GPIO_W35 (GPIO_PORT_BASE + 0x108C)
#define GPIO_W36 (GPIO_PORT_BASE + 0x1090)
#define GPIO_W37 (GPIO_PORT_BASE + 0x1094)
#define GPIO_W38 (GPIO_PORT_BASE + 0x1098)
#define GPIO_W39 (GPIO_PORT_BASE + 0x109C)
#define GPIO_W40 (GPIO_PORT_BASE + 0x10A0)
#define GPIO_W41 (GPIO_PORT_BASE + 0x10A4)
#define GPIO_W42 (GPIO_PORT_BASE + 0x10A8)
#define GPIO_W43 (GPIO_PORT_BASE + 0x10AC)
#define GPIO_W44 (GPIO_PORT_BASE + 0x10B0)
#define GPIO_W45 (GPIO_PORT_BASE + 0x10B4)
#define GPIO_W46 (GPIO_PORT_BASE + 0x10B8)
#define GPIO_W47 (GPIO_PORT_BASE + 0x10BC)
#define GPIO_W48 (GPIO_PORT_BASE + 0x10C0)
#define GPIO_W49 (GPIO_PORT_BASE + 0x10C4)
#define GPIO_W50 (GPIO_PORT_BASE + 0x10C8)
#define GPIO_W51 (GPIO_PORT_BASE + 0x10CC)
#define GPIO_W52 (GPIO_PORT_BASE + 0x10D0)
#define GPIO_W53 (GPIO_PORT_BASE + 0x10D4)
#define GPIO_W54 (GPIO_PORT_BASE + 0x10D8)
#define GPIO_W55 (GPIO_PORT_BASE + 0x10DC)
#define GPIO_W56 (GPIO_PORT_BASE + 0x10E0)
#define GPIO_W57 (GPIO_PORT_BASE + 0x10E4)
#define GPIO_W58 (GPIO_PORT_BASE + 0x10E8)
#define GPIO_W59 (GPIO_PORT_BASE + 0x10EC)
#define GPIO_W60 (GPIO_PORT_BASE + 0x10F0)
#define GPIO_W61 (GPIO_PORT_BASE + 0x10F4)
#define GPIO_W62 (GPIO_PORT_BASE + 0x10F8)
#define GPIO_W63 (GPIO_PORT_BASE + 0x10FC)
/* Word pin registers port 2 (R/W) */
#define GPIO_W64 (GPIO_PORT_BASE + 0x1100)
#define GPIO_W65 (GPIO_PORT_BASE + 0x1104)
#define GPIO_W66 (GPIO_PORT_BASE + 0x1108)
#define GPIO_W67 (GPIO_PORT_BASE + 0x110C)
#define GPIO_W68 (GPIO_PORT_BASE + 0x1110)
#define GPIO_W69 (GPIO_PORT_BASE + 0x1114)
#define GPIO_W70 (GPIO_PORT_BASE + 0x1118)
#define GPIO_W71 (GPIO_PORT_BASE + 0x111C)
#define GPIO_W72 (GPIO_PORT_BASE + 0x1120)
#define GPIO_W73 (GPIO_PORT_BASE + 0x1124)
#define GPIO_W74 (GPIO_PORT_BASE + 0x1128)
#define GPIO_W75 (GPIO_PORT_BASE + 0x112C)
#define GPIO_W76 (GPIO_PORT_BASE + 0x1130)
#define GPIO_W77 (GPIO_PORT_BASE + 0x1134)
#define GPIO_W78 (GPIO_PORT_BASE + 0x1138)
#define GPIO_W79 (GPIO_PORT_BASE + 0x113C)
#define GPIO_W80 (GPIO_PORT_BASE + 0x1140)
#define GPIO_W81 (GPIO_PORT_BASE + 0x1144)
#define GPIO_W82 (GPIO_PORT_BASE + 0x1148)
#define GPIO_W83 (GPIO_PORT_BASE + 0x114C)
#define GPIO_W84 (GPIO_PORT_BASE + 0x1150)
#define GPIO_W85 (GPIO_PORT_BASE + 0x1154)
#define GPIO_W86 (GPIO_PORT_BASE + 0x1158)
#define GPIO_W87 (GPIO_PORT_BASE + 0x115C)
#define GPIO_W88 (GPIO_PORT_BASE + 0x1160)
#define GPIO_W89 (GPIO_PORT_BASE + 0x1164)
#define GPIO_W90 (GPIO_PORT_BASE + 0x1168)
#define GPIO_W91 (GPIO_PORT_BASE + 0x116C)
#define GPIO_W92 (GPIO_PORT_BASE + 0x1170)
#define GPIO_W93 (GPIO_PORT_BASE + 0x1174)
#define GPIO_W94 (GPIO_PORT_BASE + 0x1178)
#define GPIO_W95 (GPIO_PORT_BASE + 0x117C)
/* Word pin registers port 3 (R/W) */
#define GPIO_W96 (GPIO_PORT_BASE + 0x1180)
#define GPIO_W97 (GPIO_PORT_BASE + 0x1184)
#define GPIO_W98 (GPIO_PORT_BASE + 0x1188)
#define GPIO_W99 (GPIO_PORT_BASE + 0x118C)
#define GPIO_W100 (GPIO_PORT_BASE + 0x1190)
#define GPIO_W101 (GPIO_PORT_BASE + 0x1194)
#define GPIO_W102 (GPIO_PORT_BASE + 0x1198)
#define GPIO_W103 (GPIO_PORT_BASE + 0x119C)
#define GPIO_W104 (GPIO_PORT_BASE + 0x11A0)
#define GPIO_W105 (GPIO_PORT_BASE + 0x11A4)
#define GPIO_W106 (GPIO_PORT_BASE + 0x11A8)
#define GPIO_W107 (GPIO_PORT_BASE + 0x11AC)
#define GPIO_W108 (GPIO_PORT_BASE + 0x11B0)
#define GPIO_W109 (GPIO_PORT_BASE + 0x11B4)
#define GPIO_W110 (GPIO_PORT_BASE + 0x11B8)
#define GPIO_W111 (GPIO_PORT_BASE + 0x11BC)
#define GPIO_W112 (GPIO_PORT_BASE + 0x11C0)
#define GPIO_W113 (GPIO_PORT_BASE + 0x11C4)
#define GPIO_W114 (GPIO_PORT_BASE + 0x11C8)
#define GPIO_W115 (GPIO_PORT_BASE + 0x11CC)
#define GPIO_W116 (GPIO_PORT_BASE + 0x11D0)
#define GPIO_W117 (GPIO_PORT_BASE + 0x11D4)
#define GPIO_W118 (GPIO_PORT_BASE + 0x11D8)
#define GPIO_W119 (GPIO_PORT_BASE + 0x11DC)
#define GPIO_W120 (GPIO_PORT_BASE + 0x11E0)
#define GPIO_W121 (GPIO_PORT_BASE + 0x11E4)
#define GPIO_W122 (GPIO_PORT_BASE + 0x11E8)
#define GPIO_W123 (GPIO_PORT_BASE + 0x11EC)
#define GPIO_W124 (GPIO_PORT_BASE + 0x11F0)
#define GPIO_W125 (GPIO_PORT_BASE + 0x11F4)
#define GPIO_W126 (GPIO_PORT_BASE + 0x11F8)
#define GPIO_W127 (GPIO_PORT_BASE + 0x11FC)
/* Word pin registers port 4 (R/W) */
#define GPIO_W128 (GPIO_PORT_BASE + 0x1200)
#define GPIO_W129 (GPIO_PORT_BASE + 0x1204)
#define GPIO_W130 (GPIO_PORT_BASE + 0x1208)
#define GPIO_W131 (GPIO_PORT_BASE + 0x120C)
#define GPIO_W132 (GPIO_PORT_BASE + 0x1210)
#define GPIO_W133 (GPIO_PORT_BASE + 0x1214)
#define GPIO_W134 (GPIO_PORT_BASE + 0x1218)
#define GPIO_W135 (GPIO_PORT_BASE + 0x121C)
#define GPIO_W136 (GPIO_PORT_BASE + 0x1220)
#define GPIO_W137 (GPIO_PORT_BASE + 0x1224)
#define GPIO_W138 (GPIO_PORT_BASE + 0x1228)
#define GPIO_W139 (GPIO_PORT_BASE + 0x122C)
#define GPIO_W140 (GPIO_PORT_BASE + 0x1230)
#define GPIO_W141 (GPIO_PORT_BASE + 0x1234)
#define GPIO_W142 (GPIO_PORT_BASE + 0x1238)
#define GPIO_W143 (GPIO_PORT_BASE + 0x123C)
#define GPIO_W144 (GPIO_PORT_BASE + 0x1240)
#define GPIO_W145 (GPIO_PORT_BASE + 0x1244)
#define GPIO_W146 (GPIO_PORT_BASE + 0x1248)
#define GPIO_W147 (GPIO_PORT_BASE + 0x124C)
#define GPIO_W148 (GPIO_PORT_BASE + 0x1250)
#define GPIO_W149 (GPIO_PORT_BASE + 0x1254)
#define GPIO_W150 (GPIO_PORT_BASE + 0x1258)
#define GPIO_W151 (GPIO_PORT_BASE + 0x125C)
#define GPIO_W152 (GPIO_PORT_BASE + 0x1260)
#define GPIO_W153 (GPIO_PORT_BASE + 0x1264)
#define GPIO_W154 (GPIO_PORT_BASE + 0x1268)
#define GPIO_W155 (GPIO_PORT_BASE + 0x126C)
#define GPIO_W156 (GPIO_PORT_BASE + 0x1270)
#define GPIO_W157 (GPIO_PORT_BASE + 0x1274)
#define GPIO_W158 (GPIO_PORT_BASE + 0x1278)
#define GPIO_W159 (GPIO_PORT_BASE + 0x127C)
/* Word pin registers port 5 (R/W) */
#define GPIO_W160 (GPIO_PORT_BASE + 0x1280)
#define GPIO_W161 (GPIO_PORT_BASE + 0x1284)
#define GPIO_W162 (GPIO_PORT_BASE + 0x1288)
#define GPIO_W163 (GPIO_PORT_BASE + 0x128C)
#define GPIO_W164 (GPIO_PORT_BASE + 0x1290)
#define GPIO_W165 (GPIO_PORT_BASE + 0x1294)
#define GPIO_W166 (GPIO_PORT_BASE + 0x1298)
#define GPIO_W167 (GPIO_PORT_BASE + 0x129C)
#define GPIO_W168 (GPIO_PORT_BASE + 0x12A0)
#define GPIO_W169 (GPIO_PORT_BASE + 0x12A4)
#define GPIO_W170 (GPIO_PORT_BASE + 0x12A8)
#define GPIO_W171 (GPIO_PORT_BASE + 0x12AC)
#define GPIO_W172 (GPIO_PORT_BASE + 0x12B0)
#define GPIO_W173 (GPIO_PORT_BASE + 0x12B4)
#define GPIO_W174 (GPIO_PORT_BASE + 0x12B8)
#define GPIO_W175 (GPIO_PORT_BASE + 0x12BC)
#define GPIO_W176 (GPIO_PORT_BASE + 0x12C0)
#define GPIO_W177 (GPIO_PORT_BASE + 0x12C4)
#define GPIO_W178 (GPIO_PORT_BASE + 0x12C8)
#define GPIO_W179 (GPIO_PORT_BASE + 0x12CC)
#define GPIO_W180 (GPIO_PORT_BASE + 0x12D0)
#define GPIO_W181 (GPIO_PORT_BASE + 0x12D4)
#define GPIO_W182 (GPIO_PORT_BASE + 0x12D8)
#define GPIO_W183 (GPIO_PORT_BASE + 0x12DC)
#define GPIO_W184 (GPIO_PORT_BASE + 0x12E0)
#define GPIO_W185 (GPIO_PORT_BASE + 0x12E4)
#define GPIO_W186 (GPIO_PORT_BASE + 0x12E8)
#define GPIO_W187 (GPIO_PORT_BASE + 0x12EC)
#define GPIO_W188 (GPIO_PORT_BASE + 0x12F0)
#define GPIO_W189 (GPIO_PORT_BASE + 0x12F4)
#define GPIO_W190 (GPIO_PORT_BASE + 0x12F8)
#define GPIO_W191 (GPIO_PORT_BASE + 0x12FC)
/* Word pin registers port 6 (R/W) */
#define GPIO_W192 (GPIO_PORT_BASE + 0x1300)
#define GPIO_W193 (GPIO_PORT_BASE + 0x1304)
#define GPIO_W194 (GPIO_PORT_BASE + 0x1308)
#define GPIO_W195 (GPIO_PORT_BASE + 0x130C)
#define GPIO_W196 (GPIO_PORT_BASE + 0x1310)
#define GPIO_W197 (GPIO_PORT_BASE + 0x1314)
#define GPIO_W198 (GPIO_PORT_BASE + 0x1318)
#define GPIO_W199 (GPIO_PORT_BASE + 0x131C)
#define GPIO_W200 (GPIO_PORT_BASE + 0x1320)
#define GPIO_W201 (GPIO_PORT_BASE + 0x1324)
#define GPIO_W202 (GPIO_PORT_BASE + 0x1328)
#define GPIO_W203 (GPIO_PORT_BASE + 0x132C)
#define GPIO_W204 (GPIO_PORT_BASE + 0x1330)
#define GPIO_W205 (GPIO_PORT_BASE + 0x1334)
#define GPIO_W206 (GPIO_PORT_BASE + 0x1338)
#define GPIO_W207 (GPIO_PORT_BASE + 0x133C)
#define GPIO_W208 (GPIO_PORT_BASE + 0x1340)
#define GPIO_W209 (GPIO_PORT_BASE + 0x1344)
#define GPIO_W210 (GPIO_PORT_BASE + 0x1348)
#define GPIO_W211 (GPIO_PORT_BASE + 0x134C)
#define GPIO_W212 (GPIO_PORT_BASE + 0x1350)
#define GPIO_W213 (GPIO_PORT_BASE + 0x1354)
#define GPIO_W214 (GPIO_PORT_BASE + 0x1358)
#define GPIO_W215 (GPIO_PORT_BASE + 0x135C)
#define GPIO_W216 (GPIO_PORT_BASE + 0x1360)
#define GPIO_W217 (GPIO_PORT_BASE + 0x1364)
#define GPIO_W218 (GPIO_PORT_BASE + 0x1368)
#define GPIO_W219 (GPIO_PORT_BASE + 0x136C)
#define GPIO_W220 (GPIO_PORT_BASE + 0x1370)
#define GPIO_W221 (GPIO_PORT_BASE + 0x1374)
#define GPIO_W222 (GPIO_PORT_BASE + 0x1378)
#define GPIO_W223 (GPIO_PORT_BASE + 0x137C)
/* Word pin registers port 7 (R/W) */
#define GPIO_W224 (GPIO_PORT_BASE + 0x1380)
#define GPIO_W225 (GPIO_PORT_BASE + 0x1384)
#define GPIO_W226 (GPIO_PORT_BASE + 0x1388)
#define GPIO_W227 (GPIO_PORT_BASE + 0x138C)
#define GPIO_W228 (GPIO_PORT_BASE + 0x1390)
#define GPIO_W229 (GPIO_PORT_BASE + 0x1394)
#define GPIO_W230 (GPIO_PORT_BASE + 0x1398)
#define GPIO_W231 (GPIO_PORT_BASE + 0x139C)
#define GPIO_W232 (GPIO_PORT_BASE + 0x13A0)
#define GPIO_W233 (GPIO_PORT_BASE + 0x13A4)
#define GPIO_W234 (GPIO_PORT_BASE + 0x13A8)
#define GPIO_W235 (GPIO_PORT_BASE + 0x13AC)
#define GPIO_W236 (GPIO_PORT_BASE + 0x13B0)
#define GPIO_W237 (GPIO_PORT_BASE + 0x13B4)
#define GPIO_W238 (GPIO_PORT_BASE + 0x13B8)
#define GPIO_W239 (GPIO_PORT_BASE + 0x13BC)
#define GPIO_W240 (GPIO_PORT_BASE + 0x13C0)
#define GPIO_W241 (GPIO_PORT_BASE + 0x13C4)
#define GPIO_W242 (GPIO_PORT_BASE + 0x13C8)
#define GPIO_W243 (GPIO_PORT_BASE + 0x13CC)
#define GPIO_W244 (GPIO_PORT_BASE + 0x13D0)
#define GPIO_W245 (GPIO_PORT_BASE + 0x13D4)
#define GPIO_W246 (GPIO_PORT_BASE + 0x13D8)
#define GPIO_W247 (GPIO_PORT_BASE + 0x13DC)
#define GPIO_W248 (GPIO_PORT_BASE + 0x13E0)
#define GPIO_W249 (GPIO_PORT_BASE + 0x13E4)
#define GPIO_W250 (GPIO_PORT_BASE + 0x13E8)
#define GPIO_W251 (GPIO_PORT_BASE + 0x13EC)
#define GPIO_W252 (GPIO_PORT_BASE + 0x13F0)
#define GPIO_W253 (GPIO_PORT_BASE + 0x13F4)
#define GPIO_W254 (GPIO_PORT_BASE + 0x13F8)
#define GPIO_W255 (GPIO_PORT_BASE + 0x13FC)
#define GPIO_W(port, pin) MMIO32(GPIO_PORT_BASE + 0x1000 + (port * 0x80) + (pin * 4))
/* GPIO data direction register (GPIOn_DIR) */
#define GPIO_DIR(port) MMIO32(port + 0x00)
#define GPIO0_DIR GPIO_DIR(GPIO0)
#define GPIO1_DIR GPIO_DIR(GPIO1)
#define GPIO2_DIR GPIO_DIR(GPIO2)
#define GPIO3_DIR GPIO_DIR(GPIO3)
#define GPIO4_DIR GPIO_DIR(GPIO4)
#define GPIO5_DIR GPIO_DIR(GPIO5)
#define GPIO6_DIR GPIO_DIR(GPIO6)
#define GPIO7_DIR GPIO_DIR(GPIO7)
/* GPIO fast mask register (GPIOn_MASK) */
#define GPIO_MASK(port) MMIO32(port + 0x80)
#define GPIO0_MASK GPIO_MASK(GPIO0)
#define GPIO1_MASK GPIO_MASK(GPIO1)
#define GPIO2_MASK GPIO_MASK(GPIO2)
#define GPIO3_MASK GPIO_MASK(GPIO3)
#define GPIO4_MASK GPIO_MASK(GPIO4)
#define GPIO5_MASK GPIO_MASK(GPIO5)
#define GPIO6_MASK GPIO_MASK(GPIO6)
#define GPIO7_MASK GPIO_MASK(GPIO7)
/* GPIO port pin value register (GPIOn_PIN) */
#define GPIO_PIN(port) MMIO32(port + 0x100)
#define GPIO0_PIN GPIO_PIN(GPIO0)
#define GPIO1_PIN GPIO_PIN(GPIO1)
#define GPIO2_PIN GPIO_PIN(GPIO2)
#define GPIO3_PIN GPIO_PIN(GPIO3)
#define GPIO4_PIN GPIO_PIN(GPIO4)
#define GPIO5_PIN GPIO_PIN(GPIO5)
#define GPIO6_PIN GPIO_PIN(GPIO6)
#define GPIO7_PIN GPIO_PIN(GPIO7)
/* GPIO port masked pin value register (GPIOn_MPIN) */
#define GPIO_MPIN(port) MMIO32(port + 0x180)
#define GPIO0_MPIN GPIO_MPIN(GPIO0)
#define GPIO1_MPIN GPIO_MPIN(GPIO1)
#define GPIO2_MPIN GPIO_MPIN(GPIO2)
#define GPIO3_MPIN GPIO_MPIN(GPIO3)
#define GPIO4_MPIN GPIO_MPIN(GPIO4)
#define GPIO5_MPIN GPIO_MPIN(GPIO5)
#define GPIO6_MPIN GPIO_MPIN(GPIO6)
#define GPIO7_MPIN GPIO_MPIN(GPIO7)
/* GPIO port output set register (GPIOn_SET) */
#define GPIO_SET(port) MMIO32(port + 0x200)
#define GPIO0_SET GPIO_SET(GPIO0)
#define GPIO1_SET GPIO_SET(GPIO1)
#define GPIO2_SET GPIO_SET(GPIO2)
#define GPIO3_SET GPIO_SET(GPIO3)
#define GPIO4_SET GPIO_SET(GPIO4)
#define GPIO5_SET GPIO_SET(GPIO5)
#define GPIO6_SET GPIO_SET(GPIO6)
#define GPIO7_SET GPIO_SET(GPIO7)
/* GPIO port output clear register (GPIOn_CLR) */
#define GPIO_CLR(port) MMIO32(port + 0x280)
#define GPIO0_CLR GPIO_CLR(GPIO0)
#define GPIO1_CLR GPIO_CLR(GPIO1)
#define GPIO2_CLR GPIO_CLR(GPIO2)
#define GPIO3_CLR GPIO_CLR(GPIO3)
#define GPIO4_CLR GPIO_CLR(GPIO4)
#define GPIO5_CLR GPIO_CLR(GPIO5)
#define GPIO6_CLR GPIO_CLR(GPIO6)
#define GPIO7_CLR GPIO_CLR(GPIO7)
/* GPIO port toggle register (GPIOn_NOT) */
#define GPIO_NOT(port) MMIO32(port + 0x300)
#define GPIO0_NOT GPIO_NOT(GPIO0)
#define GPIO1_NOT GPIO_NOT(GPIO1)
#define GPIO2_NOT GPIO_NOT(GPIO2)
#define GPIO3_NOT GPIO_NOT(GPIO3)
#define GPIO4_NOT GPIO_NOT(GPIO4)
#define GPIO5_NOT GPIO_NOT(GPIO5)
#define GPIO6_NOT GPIO_NOT(GPIO6)
#define GPIO7_NOT GPIO_NOT(GPIO7)
/* TODO interrupts */
BEGIN_DECLS
void gpio_set(uint32_t gpioport, uint32_t gpios);
void gpio_clear(uint32_t gpioport, uint32_t gpios);
void gpio_toggle(uint32_t gpioport, uint32_t gpios);
uint32_t gpio_get(uint32_t gpioport, uint32_t gpios);
END_DECLS
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup i2c_defines I2C Defines
@brief <b>Defined Constants and Types for the LPC43xx I2C</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@author @htmlonly &copy; @endhtmlonly 2013 Benjamin Vernoux <bvernoux@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2014 Jared Boone <jared@sharebrained.com>
@date 19 December 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2013 Benjamin Vernoux <bvernoux@gmail.com>
* Copyright (C) 2014 Jared Boone <jared@sharebrained.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_I2C_H
#define LPC43XX_I2C_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* I2C port base addresses (for convenience) */
#define I2C0 I2C0_BASE
#define I2C1 I2C1_BASE
/* --- I2C registers ------------------------------------------------------- */
/* I2C Control Set Register */
#define I2C_CONSET(port) MMIO32(port + 0x000)
#define I2C0_CONSET I2C_CONSET(I2C0)
#define I2C1_CONSET I2C_CONSET(I2C1)
/* I2C Status Register */
#define I2C_STAT(port) MMIO32(port + 0x004)
#define I2C0_STAT I2C_STAT(I2C0)
#define I2C1_STAT I2C_STAT(I2C1)
/* I2C Data Register */
#define I2C_DAT(port) MMIO32(port + 0x008)
#define I2C0_DAT I2C_DAT(I2C0)
#define I2C1_DAT I2C_DAT(I2C1)
/* I2C Slave Address Register 0 */
#define I2C_ADR0(port) MMIO32(port + 0x00C)
#define I2C0_ADR0 I2C_ADR0(I2C0)
#define I2C1_ADR0 I2C_ADR0(I2C1)
/* SCH Duty Cycle Register High Half Word */
#define I2C_SCLH(port) MMIO32(port + 0x010)
#define I2C0_SCLH I2C_SCLH(I2C0)
#define I2C1_SCLH I2C_SCLH(I2C1)
/* SCL Duty Cycle Register Low Half Word */
#define I2C_SCLL(port) MMIO32(port + 0x014)
#define I2C0_SCLL I2C_SCLL(I2C0)
#define I2C1_SCLL I2C_SCLL(I2C1)
/* I2C Control Clear Register */
#define I2C_CONCLR(port) MMIO32(port + 0x018)
#define I2C0_CONCLR I2C_CONCLR(I2C0)
#define I2C1_CONCLR I2C_CONCLR(I2C1)
/* Monitor mode control register */
#define I2C_MMCTRL(port) MMIO32(port + 0x01C)
#define I2C0_MMCTRL I2C_MMCTRL(I2C0)
#define I2C1_MMCTRL I2C_MMCTRL(I2C1)
/* I2C Slave Address Register 1 */
#define I2C_ADR1(port) MMIO32(port + 0x020)
#define I2C0_ADR1 I2C_ADR1(I2C0)
#define I2C1_ADR1 I2C_ADR1(I2C1)
/* I2C Slave Address Register 2 */
#define I2C_ADR2(port) MMIO32(port + 0x024)
#define I2C0_ADR2 I2C_ADR2(I2C0)
#define I2C1_ADR2 I2C_ADR2(I2C1)
/* I2C Slave Address Register 3 */
#define I2C_ADR3(port) MMIO32(port + 0x028)
#define I2C0_ADR3 I2C_ADR3(I2C0)
#define I2C1_ADR3 I2C_ADR3(I2C1)
/* Data buffer register */
#define I2C_DATA_BUFFER(port) MMIO32(port + 0x02C)
#define I2C0_DATA_BUFFER I2C_DATA_BUFFER(I2C0)
#define I2C1_DATA_BUFFER I2C_DATA_BUFFER(I2C1)
/* I2C Slave address mask register 0 */
#define I2C_MASK0(port) MMIO32(port + 0x030)
#define I2C0_MASK0 I2C_MASK0(I2C0)
#define I2C1_MASK0 I2C_MASK0(I2C1)
/* I2C Slave address mask register 1 */
#define I2C_MASK1(port) MMIO32(port + 0x034)
#define I2C0_MASK1 I2C_MASK1(I2C0)
#define I2C1_MASK1 I2C_MASK1(I2C1)
/* I2C Slave address mask register 2 */
#define I2C_MASK2(port) MMIO32(port + 0x038)
#define I2C0_MASK2 I2C_MASK2(I2C0)
#define I2C1_MASK2 I2C_MASK2(I2C1)
/* I2C Slave address mask register 3 */
#define I2C_MASK3(port) MMIO32(port + 0x03C)
#define I2C0_MASK3 I2C_MASK3(I2C0)
#define I2C1_MASK3 I2C_MASK3(I2C1)
/* --- I2Cx_CONCLR values -------------------------------------------------- */
#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */
#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */
#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */
#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */
/* --- I2Cx_CONSET values -------------------------------------------------- */
#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */
#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */
#define I2C_CONSET_STO (1 << 4) /* STOP flag */
#define I2C_CONSET_STA (1 << 5) /* START flag */
#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */
/* --- I2C const definitions ----------------------------------------------- */
#define I2C_WRITE 0
#define I2C_READ 1
/* --- I2C function prototypes --------------------------------------------- */
BEGIN_DECLS
typedef uint32_t i2c_port_t;
void i2c_init(i2c_port_t port, const uint16_t duty_cycle_count);
void i2c_disable(i2c_port_t port);
void i2c_tx_start(i2c_port_t port);
void i2c_tx_byte(i2c_port_t port, uint8_t byte);
uint8_t i2c_rx_byte(i2c_port_t port, bool ack);
void i2c_stop(i2c_port_t port);
void i2c0_init(const uint16_t duty_cycle_count);
void i2c0_tx_start(void);
void i2c0_tx_byte(uint8_t byte);
uint8_t i2c0_rx_byte(bool ack);
void i2c0_stop(void);
void i2c1_init(const uint16_t duty_cycle_count);
void i2c1_tx_start(void);
void i2c1_tx_byte(uint8_t byte);
uint8_t i2c1_rx_byte(bool ack);
void i2c1_stop(void);
END_DECLS
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup i2s_defines I2S Defines
@brief <b>Defined Constants and Types for the LPC43xx I2S</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_I2S_H
#define LPC43XX_I2S_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* I2S port base addresses (for convenience) */
#define I2S0 I2S0_BASE
#define I2S1 I2S1_BASE
/* --- I2S registers ------------------------------------------------------- */
/* I2S Digital Audio Output Register */
#define I2S_DAO(port) MMIO32(port + 0x000)
#define I2S0_DAO I2S_DAO(I2S0)
#define I2S1_DAO I2S_DAO(I2S1)
/* I2S Digital Audio Input Register */
#define I2S_DAI(port) MMIO32(port + 0x004)
#define I2S0_DAI I2S_DAI(I2S0)
#define I2S1_DAI I2S_DAI(I2S1)
/* I2S Transmit FIFO */
#define I2S_TXFIFO(port) MMIO32(port + 0x008)
#define I2S0_TXFIFO I2S_TXFIFO(I2S0)
#define I2S1_TXFIFO I2S_TXFIFO(I2S1)
/* I2S Receive FIFO */
#define I2S_RXFIFO(port) MMIO32(port + 0x00C)
#define I2S0_RXFIFO I2S_RXFIFO(I2S0)
#define I2S1_RXFIFO I2S_RXFIFO(I2S1)
/* I2S Status Feedback Register */
#define I2S_STATE(port) MMIO32(port + 0x010)
#define I2S0_STATE I2S_STATE(I2S0)
#define I2S1_STATE I2S_STATE(I2S1)
/* I2S DMA Configuration Register 1 */
#define I2S_DMA1(port) MMIO32(port + 0x014)
#define I2S0_DMA1 I2S_DMA1(I2S0)
#define I2S1_DMA1 I2S_DMA1(I2S1)
/* I2S DMA Configuration Register 2 */
#define I2S_DMA2(port) MMIO32(port + 0x018)
#define I2S0_DMA2 I2S_DMA2(I2S0)
#define I2S1_DMA2 I2S_DMA2(I2S1)
/* I2S Interrupt Request Control Register */
#define I2S_IRQ(port) MMIO32(port + 0x01C)
#define I2S0_IRQ I2S_IRQ(I2S0)
#define I2S1_IRQ I2S_IRQ(I2S1)
/* I2S Transmit MCLK divider */
#define I2S_TXRATE(port) MMIO32(port + 0x020)
#define I2S0_TXRATE I2S_TXRATE(I2S0)
#define I2S1_TXRATE I2S_TXRATE(I2S1)
/* I2S Receive MCLK divider */
#define I2S_RXRATE(port) MMIO32(port + 0x024)
#define I2S0_RXRATE I2S_RXRATE(I2S0)
#define I2S1_RXRATE I2S_RXRATE(I2S1)
/* I2S Transmit bit rate divider */
#define I2S_TXBITRATE(port) MMIO32(port + 0x028)
#define I2S0_TXBITRATE I2S_TXBITRATE(I2S0)
#define I2S1_TXBITRATE I2S_TXBITRATE(I2S1)
/* I2S Receive bit rate divider */
#define I2S_RXBITRATE(port) MMIO32(port + 0x02C)
#define I2S0_RXBITRATE I2S_RXBITRATE(I2S0)
#define I2S1_RXBITRATE I2S_RXBITRATE(I2S1)
/* I2S Transmit mode control */
#define I2S_TXMODE(port) MMIO32(port + 0x030)
#define I2S0_TXMODE I2S_TXMODE(I2S0)
#define I2S1_TXMODE I2S_TXMODE(I2S1)
/* I2S Receive mode control */
#define I2S_RXMODE(port) MMIO32(port + 0x034)
#define I2S0_RXMODE I2S_RXMODE(I2S0)
#define I2S1_RXMODE I2S_RXMODE(I2S1)
/* --- I2S0_DAO values ------------------------------------------ */
/* WORDWIDTH: Selects the number of bytes in data */
#define I2S0_DAO_WORDWIDTH_SHIFT (0)
#define I2S0_DAO_WORDWIDTH_MASK (0x3 << I2S0_DAO_WORDWIDTH_SHIFT)
#define I2S0_DAO_WORDWIDTH(x) ((x) << I2S0_DAO_WORDWIDTH_SHIFT)
/* MONO: When 1, data is of monaural format. When 0, the data is in stereo format */
#define I2S0_DAO_MONO_SHIFT (2)
#define I2S0_DAO_MONO_MASK (0x1 << I2S0_DAO_MONO_SHIFT)
#define I2S0_DAO_MONO(x) ((x) << I2S0_DAO_MONO_SHIFT)
/* STOP: When 1, disables accesses on FIFOs, places the transmit channel in mute mode */
#define I2S0_DAO_STOP_SHIFT (3)
#define I2S0_DAO_STOP_MASK (0x1 << I2S0_DAO_STOP_SHIFT)
#define I2S0_DAO_STOP(x) ((x) << I2S0_DAO_STOP_SHIFT)
/* RESET: When 1, asynchronously resets the transmit channel and FIFO */
#define I2S0_DAO_RESET_SHIFT (4)
#define I2S0_DAO_RESET_MASK (0x1 << I2S0_DAO_RESET_SHIFT)
#define I2S0_DAO_RESET(x) ((x) << I2S0_DAO_RESET_SHIFT)
/* WS_SEL: When 0, the interface is in master mode. When 1, the interface is in slave mode */
#define I2S0_DAO_WS_SEL_SHIFT (5)
#define I2S0_DAO_WS_SEL_MASK (0x1 << I2S0_DAO_WS_SEL_SHIFT)
#define I2S0_DAO_WS_SEL(x) ((x) << I2S0_DAO_WS_SEL_SHIFT)
/* WS_HALFPERIOD: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. */
#define I2S0_DAO_WS_HALFPERIOD_SHIFT (6)
#define I2S0_DAO_WS_HALFPERIOD_MASK (0x1ff << I2S0_DAO_WS_HALFPERIOD_SHIFT)
#define I2S0_DAO_WS_HALFPERIOD(x) ((x) << I2S0_DAO_WS_HALFPERIOD_SHIFT)
/* MUTE: When 1, the transmit channel sends only zeroes */
#define I2S0_DAO_MUTE_SHIFT (15)
#define I2S0_DAO_MUTE_MASK (0x1 << I2S0_DAO_MUTE_SHIFT)
#define I2S0_DAO_MUTE(x) ((x) << I2S0_DAO_MUTE_SHIFT)
/* --- I2S1_DAO values ------------------------------------------ */
/* WORDWIDTH: Selects the number of bytes in data */
#define I2S1_DAO_WORDWIDTH_SHIFT (0)
#define I2S1_DAO_WORDWIDTH_MASK (0x3 << I2S1_DAO_WORDWIDTH_SHIFT)
#define I2S1_DAO_WORDWIDTH(x) ((x) << I2S1_DAO_WORDWIDTH_SHIFT)
/* MONO: When 1, data is of monaural format. When 0, the data is in stereo format */
#define I2S1_DAO_MONO_SHIFT (2)
#define I2S1_DAO_MONO_MASK (0x1 << I2S1_DAO_MONO_SHIFT)
#define I2S1_DAO_MONO(x) ((x) << I2S1_DAO_MONO_SHIFT)
/* STOP: When 1, disables accesses on FIFOs, places the transmit channel in mute mode */
#define I2S1_DAO_STOP_SHIFT (3)
#define I2S1_DAO_STOP_MASK (0x1 << I2S1_DAO_STOP_SHIFT)
#define I2S1_DAO_STOP(x) ((x) << I2S1_DAO_STOP_SHIFT)
/* RESET: When 1, asynchronously resets the transmit channel and FIFO */
#define I2S1_DAO_RESET_SHIFT (4)
#define I2S1_DAO_RESET_MASK (0x1 << I2S1_DAO_RESET_SHIFT)
#define I2S1_DAO_RESET(x) ((x) << I2S1_DAO_RESET_SHIFT)
/* WS_SEL: When 0, the interface is in master mode. When 1, the interface is in slave mode */
#define I2S1_DAO_WS_SEL_SHIFT (5)
#define I2S1_DAO_WS_SEL_MASK (0x1 << I2S1_DAO_WS_SEL_SHIFT)
#define I2S1_DAO_WS_SEL(x) ((x) << I2S1_DAO_WS_SEL_SHIFT)
/* WS_HALFPERIOD: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. */
#define I2S1_DAO_WS_HALFPERIOD_SHIFT (6)
#define I2S1_DAO_WS_HALFPERIOD_MASK (0x1ff << I2S1_DAO_WS_HALFPERIOD_SHIFT)
#define I2S1_DAO_WS_HALFPERIOD(x) ((x) << I2S1_DAO_WS_HALFPERIOD_SHIFT)
/* MUTE: When 1, the transmit channel sends only zeroes */
#define I2S1_DAO_MUTE_SHIFT (15)
#define I2S1_DAO_MUTE_MASK (0x1 << I2S1_DAO_MUTE_SHIFT)
#define I2S1_DAO_MUTE(x) ((x) << I2S1_DAO_MUTE_SHIFT)
/* --- I2S0_DAI values ------------------------------------------ */
/* WORDWIDTH: Selects the number of bytes in data */
#define I2S0_DAI_WORDWIDTH_SHIFT (0)
#define I2S0_DAI_WORDWIDTH_MASK (0x3 << I2S0_DAI_WORDWIDTH_SHIFT)
#define I2S0_DAI_WORDWIDTH(x) ((x) << I2S0_DAI_WORDWIDTH_SHIFT)
/* MONO: When 1, data is of monaural format. When 0, the data is in stereo format */
#define I2S0_DAI_MONO_SHIFT (2)
#define I2S0_DAI_MONO_MASK (0x1 << I2S0_DAI_MONO_SHIFT)
#define I2S0_DAI_MONO(x) ((x) << I2S0_DAI_MONO_SHIFT)
/* STOP: When 1, disables accesses on FIFOs, places the transmit channel in mute mode */
#define I2S0_DAI_STOP_SHIFT (3)
#define I2S0_DAI_STOP_MASK (0x1 << I2S0_DAI_STOP_SHIFT)
#define I2S0_DAI_STOP(x) ((x) << I2S0_DAI_STOP_SHIFT)
/* RESET: When 1, asynchronously resets the transmit channel and FIFO */
#define I2S0_DAI_RESET_SHIFT (4)
#define I2S0_DAI_RESET_MASK (0x1 << I2S0_DAI_RESET_SHIFT)
#define I2S0_DAI_RESET(x) ((x) << I2S0_DAI_RESET_SHIFT)
/* WS_SEL: When 0, the interface is in master mode. When 1, the interface is in slave mode */
#define I2S0_DAI_WS_SEL_SHIFT (5)
#define I2S0_DAI_WS_SEL_MASK (0x1 << I2S0_DAI_WS_SEL_SHIFT)
#define I2S0_DAI_WS_SEL(x) ((x) << I2S0_DAI_WS_SEL_SHIFT)
/* WS_HALFPERIOD: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. */
#define I2S0_DAI_WS_HALFPERIOD_SHIFT (6)
#define I2S0_DAI_WS_HALFPERIOD_MASK (0x1ff << I2S0_DAI_WS_HALFPERIOD_SHIFT)
#define I2S0_DAI_WS_HALFPERIOD(x) ((x) << I2S0_DAI_WS_HALFPERIOD_SHIFT)
/* --- I2S1_DAI values ------------------------------------------ */
/* WORDWIDTH: Selects the number of bytes in data */
#define I2S1_DAI_WORDWIDTH_SHIFT (0)
#define I2S1_DAI_WORDWIDTH_MASK (0x3 << I2S1_DAI_WORDWIDTH_SHIFT)
#define I2S1_DAI_WORDWIDTH(x) ((x) << I2S1_DAI_WORDWIDTH_SHIFT)
/* MONO: When 1, data is of monaural format. When 0, the data is in stereo format */
#define I2S1_DAI_MONO_SHIFT (2)
#define I2S1_DAI_MONO_MASK (0x1 << I2S1_DAI_MONO_SHIFT)
#define I2S1_DAI_MONO(x) ((x) << I2S1_DAI_MONO_SHIFT)
/* STOP: When 1, disables accesses on FIFOs, places the transmit channel in mute mode */
#define I2S1_DAI_STOP_SHIFT (3)
#define I2S1_DAI_STOP_MASK (0x1 << I2S1_DAI_STOP_SHIFT)
#define I2S1_DAI_STOP(x) ((x) << I2S1_DAI_STOP_SHIFT)
/* RESET: When 1, asynchronously resets the transmit channel and FIFO */
#define I2S1_DAI_RESET_SHIFT (4)
#define I2S1_DAI_RESET_MASK (0x1 << I2S1_DAI_RESET_SHIFT)
#define I2S1_DAI_RESET(x) ((x) << I2S1_DAI_RESET_SHIFT)
/* WS_SEL: When 0, the interface is in master mode. When 1, the interface is in slave mode */
#define I2S1_DAI_WS_SEL_SHIFT (5)
#define I2S1_DAI_WS_SEL_MASK (0x1 << I2S1_DAI_WS_SEL_SHIFT)
#define I2S1_DAI_WS_SEL(x) ((x) << I2S1_DAI_WS_SEL_SHIFT)
/* WS_HALFPERIOD: Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. */
#define I2S1_DAI_WS_HALFPERIOD_SHIFT (6)
#define I2S1_DAI_WS_HALFPERIOD_MASK (0x1ff << I2S1_DAI_WS_HALFPERIOD_SHIFT)
#define I2S1_DAI_WS_HALFPERIOD(x) ((x) << I2S1_DAI_WS_HALFPERIOD_SHIFT)
/* --- I2S0_TXFIFO values --------------------------------------- */
/* I2STXFIFO: 8 x 32-bit transmit FIFO */
#define I2S0_TXFIFO_I2STXFIFO_SHIFT (0)
#define I2S0_TXFIFO_I2STXFIFO_MASK (0xffffffff << I2S0_TXFIFO_I2STXFIFO_SHIFT)
#define I2S0_TXFIFO_I2STXFIFO(x) ((x) << I2S0_TXFIFO_I2STXFIFO_SHIFT)
/* --- I2S1_TXFIFO values --------------------------------------- */
/* I2STXFIFO: 8 x 32-bit transmit FIFO */
#define I2S1_TXFIFO_I2STXFIFO_SHIFT (0)
#define I2S1_TXFIFO_I2STXFIFO_MASK (0xffffffff << I2S1_TXFIFO_I2STXFIFO_SHIFT)
#define I2S1_TXFIFO_I2STXFIFO(x) ((x) << I2S1_TXFIFO_I2STXFIFO_SHIFT)
/* --- I2S0_RXFIFO values --------------------------------------- */
/* I2SRXFIFO: 8 x 32-bit receive FIFO */
#define I2S0_RXFIFO_I2SRXFIFO_SHIFT (0)
#define I2S0_RXFIFO_I2SRXFIFO_MASK (0xffffffff << I2S0_RXFIFO_I2SRXFIFO_SHIFT)
#define I2S0_RXFIFO_I2SRXFIFO(x) ((x) << I2S0_RXFIFO_I2SRXFIFO_SHIFT)
/* --- I2S1_RXFIFO values --------------------------------------- */
/* I2SRXFIFO: 8 x 32-bit receive FIFO */
#define I2S1_RXFIFO_I2SRXFIFO_SHIFT (0)
#define I2S1_RXFIFO_I2SRXFIFO_MASK (0xffffffff << I2S1_RXFIFO_I2SRXFIFO_SHIFT)
#define I2S1_RXFIFO_I2SRXFIFO(x) ((x) << I2S1_RXFIFO_I2SRXFIFO_SHIFT)
/* --- I2S0_STATE values ---------------------------------------- */
/* IRQ: This bit reflects the presence of Receive Interrupt or Transmit Interrupt */
#define I2S0_STATE_IRQ_SHIFT (0)
#define I2S0_STATE_IRQ_MASK (0x1 << I2S0_STATE_IRQ_SHIFT)
#define I2S0_STATE_IRQ(x) ((x) << I2S0_STATE_IRQ_SHIFT)
/* DMAREQ1: This bit reflects the presence of Receive or Transmit DMA Request 1 */
#define I2S0_STATE_DMAREQ1_SHIFT (1)
#define I2S0_STATE_DMAREQ1_MASK (0x1 << I2S0_STATE_DMAREQ1_SHIFT)
#define I2S0_STATE_DMAREQ1(x) ((x) << I2S0_STATE_DMAREQ1_SHIFT)
/* DMAREQ2: This bit reflects the presence of Receive or Transmit DMA Request 2 */
#define I2S0_STATE_DMAREQ2_SHIFT (2)
#define I2S0_STATE_DMAREQ2_MASK (0x1 << I2S0_STATE_DMAREQ2_SHIFT)
#define I2S0_STATE_DMAREQ2(x) ((x) << I2S0_STATE_DMAREQ2_SHIFT)
/* RX_LEVEL: Reflects the current level of the Receive FIFO */
#define I2S0_STATE_RX_LEVEL_SHIFT (8)
#define I2S0_STATE_RX_LEVEL_MASK (0xf << I2S0_STATE_RX_LEVEL_SHIFT)
#define I2S0_STATE_RX_LEVEL(x) ((x) << I2S0_STATE_RX_LEVEL_SHIFT)
/* TX_LEVEL: Reflects the current level of the Transmit FIFO */
#define I2S0_STATE_TX_LEVEL_SHIFT (16)
#define I2S0_STATE_TX_LEVEL_MASK (0xf << I2S0_STATE_TX_LEVEL_SHIFT)
#define I2S0_STATE_TX_LEVEL(x) ((x) << I2S0_STATE_TX_LEVEL_SHIFT)
/* --- I2S1_STATE values ---------------------------------------- */
/* IRQ: This bit reflects the presence of Receive Interrupt or Transmit Interrupt */
#define I2S1_STATE_IRQ_SHIFT (0)
#define I2S1_STATE_IRQ_MASK (0x1 << I2S1_STATE_IRQ_SHIFT)
#define I2S1_STATE_IRQ(x) ((x) << I2S1_STATE_IRQ_SHIFT)
/* DMAREQ1: This bit reflects the presence of Receive or Transmit DMA Request 1 */
#define I2S1_STATE_DMAREQ1_SHIFT (1)
#define I2S1_STATE_DMAREQ1_MASK (0x1 << I2S1_STATE_DMAREQ1_SHIFT)
#define I2S1_STATE_DMAREQ1(x) ((x) << I2S1_STATE_DMAREQ1_SHIFT)
/* DMAREQ2: This bit reflects the presence of Receive or Transmit DMA Request 2 */
#define I2S1_STATE_DMAREQ2_SHIFT (2)
#define I2S1_STATE_DMAREQ2_MASK (0x1 << I2S1_STATE_DMAREQ2_SHIFT)
#define I2S1_STATE_DMAREQ2(x) ((x) << I2S1_STATE_DMAREQ2_SHIFT)
/* RX_LEVEL: Reflects the current level of the Receive FIFO */
#define I2S1_STATE_RX_LEVEL_SHIFT (8)
#define I2S1_STATE_RX_LEVEL_MASK (0xf << I2S1_STATE_RX_LEVEL_SHIFT)
#define I2S1_STATE_RX_LEVEL(x) ((x) << I2S1_STATE_RX_LEVEL_SHIFT)
/* TX_LEVEL: Reflects the current level of the Transmit FIFO */
#define I2S1_STATE_TX_LEVEL_SHIFT (16)
#define I2S1_STATE_TX_LEVEL_MASK (0xf << I2S1_STATE_TX_LEVEL_SHIFT)
#define I2S1_STATE_TX_LEVEL(x) ((x) << I2S1_STATE_TX_LEVEL_SHIFT)
/* --- I2S0_DMA1 values ----------------------------------------- */
/* RX_DMA1_ENABLE: When 1, enables DMA1 for I2S receive */
#define I2S0_DMA1_RX_DMA1_ENABLE_SHIFT (0)
#define I2S0_DMA1_RX_DMA1_ENABLE_MASK (0x1 << I2S0_DMA1_RX_DMA1_ENABLE_SHIFT)
#define I2S0_DMA1_RX_DMA1_ENABLE(x) ((x) << I2S0_DMA1_RX_DMA1_ENABLE_SHIFT)
/* TX_DMA1_ENABLE: When 1, enables DMA1 for I2S transmit */
#define I2S0_DMA1_TX_DMA1_ENABLE_SHIFT (1)
#define I2S0_DMA1_TX_DMA1_ENABLE_MASK (0x1 << I2S0_DMA1_TX_DMA1_ENABLE_SHIFT)
#define I2S0_DMA1_TX_DMA1_ENABLE(x) ((x) << I2S0_DMA1_TX_DMA1_ENABLE_SHIFT)
/* RX_DEPTH_DMA1: Set the FIFO level that triggers a receive DMA request on DMA1 */
#define I2S0_DMA1_RX_DEPTH_DMA1_SHIFT (8)
#define I2S0_DMA1_RX_DEPTH_DMA1_MASK (0xf << I2S0_DMA1_RX_DEPTH_DMA1_SHIFT)
#define I2S0_DMA1_RX_DEPTH_DMA1(x) ((x) << I2S0_DMA1_RX_DEPTH_DMA1_SHIFT)
/* TX_DEPTH_DMA1: Set the FIFO level that triggers a transmit DMA request on DMA1 */
#define I2S0_DMA1_TX_DEPTH_DMA1_SHIFT (16)
#define I2S0_DMA1_TX_DEPTH_DMA1_MASK (0xf << I2S0_DMA1_TX_DEPTH_DMA1_SHIFT)
#define I2S0_DMA1_TX_DEPTH_DMA1(x) ((x) << I2S0_DMA1_TX_DEPTH_DMA1_SHIFT)
/* --- I2S1_DMA1 values ----------------------------------------- */
/* RX_DMA1_ENABLE: When 1, enables DMA1 for I2S receive */
#define I2S1_DMA1_RX_DMA1_ENABLE_SHIFT (0)
#define I2S1_DMA1_RX_DMA1_ENABLE_MASK (0x1 << I2S1_DMA1_RX_DMA1_ENABLE_SHIFT)
#define I2S1_DMA1_RX_DMA1_ENABLE(x) ((x) << I2S1_DMA1_RX_DMA1_ENABLE_SHIFT)
/* TX_DMA1_ENABLE: When 1, enables DMA1 for I2S transmit */
#define I2S1_DMA1_TX_DMA1_ENABLE_SHIFT (1)
#define I2S1_DMA1_TX_DMA1_ENABLE_MASK (0x1 << I2S1_DMA1_TX_DMA1_ENABLE_SHIFT)
#define I2S1_DMA1_TX_DMA1_ENABLE(x) ((x) << I2S1_DMA1_TX_DMA1_ENABLE_SHIFT)
/* RX_DEPTH_DMA1: Set the FIFO level that triggers a receive DMA request on DMA1 */
#define I2S1_DMA1_RX_DEPTH_DMA1_SHIFT (8)
#define I2S1_DMA1_RX_DEPTH_DMA1_MASK (0xf << I2S1_DMA1_RX_DEPTH_DMA1_SHIFT)
#define I2S1_DMA1_RX_DEPTH_DMA1(x) ((x) << I2S1_DMA1_RX_DEPTH_DMA1_SHIFT)
/* TX_DEPTH_DMA1: Set the FIFO level that triggers a transmit DMA request on DMA1 */
#define I2S1_DMA1_TX_DEPTH_DMA1_SHIFT (16)
#define I2S1_DMA1_TX_DEPTH_DMA1_MASK (0xf << I2S1_DMA1_TX_DEPTH_DMA1_SHIFT)
#define I2S1_DMA1_TX_DEPTH_DMA1(x) ((x) << I2S1_DMA1_TX_DEPTH_DMA1_SHIFT)
/* --- I2S0_DMA2 values ----------------------------------------- */
/* RX_DMA2_ENABLE: When 1, enables DMA2 for I2S receive */
#define I2S0_DMA2_RX_DMA2_ENABLE_SHIFT (0)
#define I2S0_DMA2_RX_DMA2_ENABLE_MASK (0x1 << I2S0_DMA2_RX_DMA2_ENABLE_SHIFT)
#define I2S0_DMA2_RX_DMA2_ENABLE(x) ((x) << I2S0_DMA2_RX_DMA2_ENABLE_SHIFT)
/* TX_DMA2_ENABLE: When 1, enables DMA2 for I2S transmit */
#define I2S0_DMA2_TX_DMA2_ENABLE_SHIFT (1)
#define I2S0_DMA2_TX_DMA2_ENABLE_MASK (0x1 << I2S0_DMA2_TX_DMA2_ENABLE_SHIFT)
#define I2S0_DMA2_TX_DMA2_ENABLE(x) ((x) << I2S0_DMA2_TX_DMA2_ENABLE_SHIFT)
/* RX_DEPTH_DMA2: Set the FIFO level that triggers a receive DMA request on DMA2 */
#define I2S0_DMA2_RX_DEPTH_DMA2_SHIFT (8)
#define I2S0_DMA2_RX_DEPTH_DMA2_MASK (0xf << I2S0_DMA2_RX_DEPTH_DMA2_SHIFT)
#define I2S0_DMA2_RX_DEPTH_DMA2(x) ((x) << I2S0_DMA2_RX_DEPTH_DMA2_SHIFT)
/* TX_DEPTH_DMA2: Set the FIFO level that triggers a transmit DMA request on DMA2 */
#define I2S0_DMA2_TX_DEPTH_DMA2_SHIFT (16)
#define I2S0_DMA2_TX_DEPTH_DMA2_MASK (0xf << I2S0_DMA2_TX_DEPTH_DMA2_SHIFT)
#define I2S0_DMA2_TX_DEPTH_DMA2(x) ((x) << I2S0_DMA2_TX_DEPTH_DMA2_SHIFT)
/* --- I2S1_DMA2 values ----------------------------------------- */
/* RX_DMA2_ENABLE: When 1, enables DMA2 for I2S receive */
#define I2S1_DMA2_RX_DMA2_ENABLE_SHIFT (0)
#define I2S1_DMA2_RX_DMA2_ENABLE_MASK (0x1 << I2S1_DMA2_RX_DMA2_ENABLE_SHIFT)
#define I2S1_DMA2_RX_DMA2_ENABLE(x) ((x) << I2S1_DMA2_RX_DMA2_ENABLE_SHIFT)
/* TX_DMA2_ENABLE: When 1, enables DMA2 for I2S transmit */
#define I2S1_DMA2_TX_DMA2_ENABLE_SHIFT (1)
#define I2S1_DMA2_TX_DMA2_ENABLE_MASK (0x1 << I2S1_DMA2_TX_DMA2_ENABLE_SHIFT)
#define I2S1_DMA2_TX_DMA2_ENABLE(x) ((x) << I2S1_DMA2_TX_DMA2_ENABLE_SHIFT)
/* RX_DEPTH_DMA2: Set the FIFO level that triggers a receive DMA request on DMA2 */
#define I2S1_DMA2_RX_DEPTH_DMA2_SHIFT (8)
#define I2S1_DMA2_RX_DEPTH_DMA2_MASK (0xf << I2S1_DMA2_RX_DEPTH_DMA2_SHIFT)
#define I2S1_DMA2_RX_DEPTH_DMA2(x) ((x) << I2S1_DMA2_RX_DEPTH_DMA2_SHIFT)
/* TX_DEPTH_DMA2: Set the FIFO level that triggers a transmit DMA request on DMA2 */
#define I2S1_DMA2_TX_DEPTH_DMA2_SHIFT (16)
#define I2S1_DMA2_TX_DEPTH_DMA2_MASK (0xf << I2S1_DMA2_TX_DEPTH_DMA2_SHIFT)
#define I2S1_DMA2_TX_DEPTH_DMA2(x) ((x) << I2S1_DMA2_TX_DEPTH_DMA2_SHIFT)
/* --- I2S0_IRQ values ------------------------------------------ */
/* RX_IRQ_ENABLE: When 1, enables I2S receive interrupt */
#define I2S0_IRQ_RX_IRQ_ENABLE_SHIFT (0)
#define I2S0_IRQ_RX_IRQ_ENABLE_MASK (0x1 << I2S0_IRQ_RX_IRQ_ENABLE_SHIFT)
#define I2S0_IRQ_RX_IRQ_ENABLE(x) ((x) << I2S0_IRQ_RX_IRQ_ENABLE_SHIFT)
/* TX_IRQ_ENABLE: When 1, enables I2S transmit interrupt */
#define I2S0_IRQ_TX_IRQ_ENABLE_SHIFT (1)
#define I2S0_IRQ_TX_IRQ_ENABLE_MASK (0x1 << I2S0_IRQ_TX_IRQ_ENABLE_SHIFT)
#define I2S0_IRQ_TX_IRQ_ENABLE(x) ((x) << I2S0_IRQ_TX_IRQ_ENABLE_SHIFT)
/* RX_DEPTH_IRQ: Set the FIFO level on which to create an irq request. */
#define I2S0_IRQ_RX_DEPTH_IRQ_SHIFT (8)
#define I2S0_IRQ_RX_DEPTH_IRQ_MASK (0xf << I2S0_IRQ_RX_DEPTH_IRQ_SHIFT)
#define I2S0_IRQ_RX_DEPTH_IRQ(x) ((x) << I2S0_IRQ_RX_DEPTH_IRQ_SHIFT)
/* TX_DEPTH_IRQ: Set the FIFO level on which to create an irq request. */
#define I2S0_IRQ_TX_DEPTH_IRQ_SHIFT (16)
#define I2S0_IRQ_TX_DEPTH_IRQ_MASK (0xf << I2S0_IRQ_TX_DEPTH_IRQ_SHIFT)
#define I2S0_IRQ_TX_DEPTH_IRQ(x) ((x) << I2S0_IRQ_TX_DEPTH_IRQ_SHIFT)
/* --- I2S1_IRQ values ------------------------------------------ */
/* RX_IRQ_ENABLE: When 1, enables I2S receive interrupt */
#define I2S1_IRQ_RX_IRQ_ENABLE_SHIFT (0)
#define I2S1_IRQ_RX_IRQ_ENABLE_MASK (0x1 << I2S1_IRQ_RX_IRQ_ENABLE_SHIFT)
#define I2S1_IRQ_RX_IRQ_ENABLE(x) ((x) << I2S1_IRQ_RX_IRQ_ENABLE_SHIFT)
/* TX_IRQ_ENABLE: When 1, enables I2S transmit interrupt */
#define I2S1_IRQ_TX_IRQ_ENABLE_SHIFT (1)
#define I2S1_IRQ_TX_IRQ_ENABLE_MASK (0x1 << I2S1_IRQ_TX_IRQ_ENABLE_SHIFT)
#define I2S1_IRQ_TX_IRQ_ENABLE(x) ((x) << I2S1_IRQ_TX_IRQ_ENABLE_SHIFT)
/* RX_DEPTH_IRQ: Set the FIFO level on which to create an irq request. */
#define I2S1_IRQ_RX_DEPTH_IRQ_SHIFT (8)
#define I2S1_IRQ_RX_DEPTH_IRQ_MASK (0xf << I2S1_IRQ_RX_DEPTH_IRQ_SHIFT)
#define I2S1_IRQ_RX_DEPTH_IRQ(x) ((x) << I2S1_IRQ_RX_DEPTH_IRQ_SHIFT)
/* TX_DEPTH_IRQ: Set the FIFO level on which to create an irq request. */
#define I2S1_IRQ_TX_DEPTH_IRQ_SHIFT (16)
#define I2S1_IRQ_TX_DEPTH_IRQ_MASK (0xf << I2S1_IRQ_TX_DEPTH_IRQ_SHIFT)
#define I2S1_IRQ_TX_DEPTH_IRQ(x) ((x) << I2S1_IRQ_TX_DEPTH_IRQ_SHIFT)
/* --- I2S0_TXRATE values --------------------------------------- */
/* Y_DIVIDER: I2S transmit MCLK rate denominator */
#define I2S0_TXRATE_Y_DIVIDER_SHIFT (0)
#define I2S0_TXRATE_Y_DIVIDER_MASK (0xff << I2S0_TXRATE_Y_DIVIDER_SHIFT)
#define I2S0_TXRATE_Y_DIVIDER(x) ((x) << I2S0_TXRATE_Y_DIVIDER_SHIFT)
/* X_DIVIDER: I2S transmit MCLK rate numerator */
#define I2S0_TXRATE_X_DIVIDER_SHIFT (8)
#define I2S0_TXRATE_X_DIVIDER_MASK (0xff << I2S0_TXRATE_X_DIVIDER_SHIFT)
#define I2S0_TXRATE_X_DIVIDER(x) ((x) << I2S0_TXRATE_X_DIVIDER_SHIFT)
/* --- I2S1_TXRATE values --------------------------------------- */
/* Y_DIVIDER: I2S transmit MCLK rate denominator */
#define I2S1_TXRATE_Y_DIVIDER_SHIFT (0)
#define I2S1_TXRATE_Y_DIVIDER_MASK (0xff << I2S1_TXRATE_Y_DIVIDER_SHIFT)
#define I2S1_TXRATE_Y_DIVIDER(x) ((x) << I2S1_TXRATE_Y_DIVIDER_SHIFT)
/* X_DIVIDER: I2S transmit MCLK rate numerator */
#define I2S1_TXRATE_X_DIVIDER_SHIFT (8)
#define I2S1_TXRATE_X_DIVIDER_MASK (0xff << I2S1_TXRATE_X_DIVIDER_SHIFT)
#define I2S1_TXRATE_X_DIVIDER(x) ((x) << I2S1_TXRATE_X_DIVIDER_SHIFT)
/* --- I2S0_RXRATE values --------------------------------------- */
/* Y_DIVIDER: I2S receive MCLK rate denominator */
#define I2S0_RXRATE_Y_DIVIDER_SHIFT (0)
#define I2S0_RXRATE_Y_DIVIDER_MASK (0xff << I2S0_RXRATE_Y_DIVIDER_SHIFT)
#define I2S0_RXRATE_Y_DIVIDER(x) ((x) << I2S0_RXRATE_Y_DIVIDER_SHIFT)
/* X_DIVIDER: I2S receive MCLK rate numerator */
#define I2S0_RXRATE_X_DIVIDER_SHIFT (8)
#define I2S0_RXRATE_X_DIVIDER_MASK (0xff << I2S0_RXRATE_X_DIVIDER_SHIFT)
#define I2S0_RXRATE_X_DIVIDER(x) ((x) << I2S0_RXRATE_X_DIVIDER_SHIFT)
/* --- I2S1_RXRATE values --------------------------------------- */
/* Y_DIVIDER: I2S receive MCLK rate denominator */
#define I2S1_RXRATE_Y_DIVIDER_SHIFT (0)
#define I2S1_RXRATE_Y_DIVIDER_MASK (0xff << I2S1_RXRATE_Y_DIVIDER_SHIFT)
#define I2S1_RXRATE_Y_DIVIDER(x) ((x) << I2S1_RXRATE_Y_DIVIDER_SHIFT)
/* X_DIVIDER: I2S receive MCLK rate numerator */
#define I2S1_RXRATE_X_DIVIDER_SHIFT (8)
#define I2S1_RXRATE_X_DIVIDER_MASK (0xff << I2S1_RXRATE_X_DIVIDER_SHIFT)
#define I2S1_RXRATE_X_DIVIDER(x) ((x) << I2S1_RXRATE_X_DIVIDER_SHIFT)
/* --- I2S0_TXBITRATE values ------------------------------------ */
/* TX_BITRATE: I2S transmit bit rate */
#define I2S0_TXBITRATE_TX_BITRATE_SHIFT (0)
#define I2S0_TXBITRATE_TX_BITRATE_MASK (0x3f << I2S0_TXBITRATE_TX_BITRATE_SHIFT)
#define I2S0_TXBITRATE_TX_BITRATE(x) ((x) << I2S0_TXBITRATE_TX_BITRATE_SHIFT)
/* --- I2S1_TXBITRATE values ------------------------------------ */
/* TX_BITRATE: I2S transmit bit rate */
#define I2S1_TXBITRATE_TX_BITRATE_SHIFT (0)
#define I2S1_TXBITRATE_TX_BITRATE_MASK (0x3f << I2S1_TXBITRATE_TX_BITRATE_SHIFT)
#define I2S1_TXBITRATE_TX_BITRATE(x) ((x) << I2S1_TXBITRATE_TX_BITRATE_SHIFT)
/* --- I2S0_RXBITRATE values ------------------------------------ */
/* RX_BITRATE: I2S receive bit rate */
#define I2S0_RXBITRATE_RX_BITRATE_SHIFT (0)
#define I2S0_RXBITRATE_RX_BITRATE_MASK (0x3f << I2S0_RXBITRATE_RX_BITRATE_SHIFT)
#define I2S0_RXBITRATE_RX_BITRATE(x) ((x) << I2S0_RXBITRATE_RX_BITRATE_SHIFT)
/* --- I2S1_RXBITRATE values ------------------------------------ */
/* RX_BITRATE: I2S receive bit rate */
#define I2S1_RXBITRATE_RX_BITRATE_SHIFT (0)
#define I2S1_RXBITRATE_RX_BITRATE_MASK (0x3f << I2S1_RXBITRATE_RX_BITRATE_SHIFT)
#define I2S1_RXBITRATE_RX_BITRATE(x) ((x) << I2S1_RXBITRATE_RX_BITRATE_SHIFT)
/* --- I2S0_TXMODE values --------------------------------------- */
/* TXCLKSEL: Clock source selection for the transmit bit clock divider */
#define I2S0_TXMODE_TXCLKSEL_SHIFT (0)
#define I2S0_TXMODE_TXCLKSEL_MASK (0x3 << I2S0_TXMODE_TXCLKSEL_SHIFT)
#define I2S0_TXMODE_TXCLKSEL(x) ((x) << I2S0_TXMODE_TXCLKSEL_SHIFT)
/* TX4PIN: Transmit 4-pin mode selection */
#define I2S0_TXMODE_TX4PIN_SHIFT (2)
#define I2S0_TXMODE_TX4PIN_MASK (0x1 << I2S0_TXMODE_TX4PIN_SHIFT)
#define I2S0_TXMODE_TX4PIN(x) ((x) << I2S0_TXMODE_TX4PIN_SHIFT)
/* TXMCENA: Enable for the TX_MCLK output */
#define I2S0_TXMODE_TXMCENA_SHIFT (3)
#define I2S0_TXMODE_TXMCENA_MASK (0x1 << I2S0_TXMODE_TXMCENA_SHIFT)
#define I2S0_TXMODE_TXMCENA(x) ((x) << I2S0_TXMODE_TXMCENA_SHIFT)
/* --- I2S1_TXMODE values --------------------------------------- */
/* TXCLKSEL: Clock source selection for the transmit bit clock divider */
#define I2S1_TXMODE_TXCLKSEL_SHIFT (0)
#define I2S1_TXMODE_TXCLKSEL_MASK (0x3 << I2S1_TXMODE_TXCLKSEL_SHIFT)
#define I2S1_TXMODE_TXCLKSEL(x) ((x) << I2S1_TXMODE_TXCLKSEL_SHIFT)
/* TX4PIN: Transmit 4-pin mode selection */
#define I2S1_TXMODE_TX4PIN_SHIFT (2)
#define I2S1_TXMODE_TX4PIN_MASK (0x1 << I2S1_TXMODE_TX4PIN_SHIFT)
#define I2S1_TXMODE_TX4PIN(x) ((x) << I2S1_TXMODE_TX4PIN_SHIFT)
/* TXMCENA: Enable for the TX_MCLK output */
#define I2S1_TXMODE_TXMCENA_SHIFT (3)
#define I2S1_TXMODE_TXMCENA_MASK (0x1 << I2S1_TXMODE_TXMCENA_SHIFT)
#define I2S1_TXMODE_TXMCENA(x) ((x) << I2S1_TXMODE_TXMCENA_SHIFT)
/* --- I2S0_RXMODE values --------------------------------------- */
/* RXCLKSEL: Clock source selection for the receive bit clock divider */
#define I2S0_RXMODE_RXCLKSEL_SHIFT (0)
#define I2S0_RXMODE_RXCLKSEL_MASK (0x3 << I2S0_RXMODE_RXCLKSEL_SHIFT)
#define I2S0_RXMODE_RXCLKSEL(x) ((x) << I2S0_RXMODE_RXCLKSEL_SHIFT)
/* RX4PIN: Receive 4-pin mode selection */
#define I2S0_RXMODE_RX4PIN_SHIFT (2)
#define I2S0_RXMODE_RX4PIN_MASK (0x1 << I2S0_RXMODE_RX4PIN_SHIFT)
#define I2S0_RXMODE_RX4PIN(x) ((x) << I2S0_RXMODE_RX4PIN_SHIFT)
/* RXMCENA: Enable for the RX_MCLK output */
#define I2S0_RXMODE_RXMCENA_SHIFT (3)
#define I2S0_RXMODE_RXMCENA_MASK (0x1 << I2S0_RXMODE_RXMCENA_SHIFT)
#define I2S0_RXMODE_RXMCENA(x) ((x) << I2S0_RXMODE_RXMCENA_SHIFT)
/* --- I2S1_RXMODE values --------------------------------------- */
/* RXCLKSEL: Clock source selection for the receive bit clock divider */
#define I2S1_RXMODE_RXCLKSEL_SHIFT (0)
#define I2S1_RXMODE_RXCLKSEL_MASK (0x3 << I2S1_RXMODE_RXCLKSEL_SHIFT)
#define I2S1_RXMODE_RXCLKSEL(x) ((x) << I2S1_RXMODE_RXCLKSEL_SHIFT)
/* RX4PIN: Receive 4-pin mode selection */
#define I2S1_RXMODE_RX4PIN_SHIFT (2)
#define I2S1_RXMODE_RX4PIN_MASK (0x1 << I2S1_RXMODE_RX4PIN_SHIFT)
#define I2S1_RXMODE_RX4PIN(x) ((x) << I2S1_RXMODE_RX4PIN_SHIFT)
/* RXMCENA: Enable for the RX_MCLK output */
#define I2S1_RXMODE_RXMCENA_SHIFT (3)
#define I2S1_RXMODE_RXMCENA_MASK (0x1 << I2S1_RXMODE_RXMCENA_SHIFT)
#define I2S1_RXMODE_RXMCENA(x) ((x) << I2S1_RXMODE_RXMCENA_SHIFT)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_IPC_H
#define LPC43XX_IPC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
void ipc_halt_m0(void);
void ipc_start_m0(uint32_t cm0_baseaddr);
void ipc_m0apptxevent_clear(void);
#ifdef __cplusplus
}
#endif
#endif

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includeguard: LIBOPENCM3_LPC43xx_M0_NVIC_H
partname_humanreadable: LPC 43xx series M0 core
partname_doxygen: LPC43xx (M0)
irqs:
0: rtc
1: m4core
2: dma
# reserved: 3
4: flasheepromat
5: ethernet
6: sdio
7: lcd
8: usb0
9: usb1
10: sct
11: ritimer_or_wwdt
12: timer0
13: gint1
14: pin_int4
15: timer3
16: mcpwm
17: adc0
18: i2c0_or_irc1
19: sgpio
20: spi_or_dac
21: adc1
22: ssp0_or_ssp1
23: eventrouter
24: usart0
25: uart1
26: usart2_or_c_can1
27: usart3
28: i2s0_or_i2s1
29: c_can0

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includeguard: LIBOPENCM3_LPC43xx_M4_NVIC_H
partname_humanreadable: LPC 43xx series M4 core
partname_doxygen: LPC43xx (M4)
irqs:
0: dac
1: m0core
2: dma
# reserved: 3, 4
5: ethernet
6: sdio
7: lcd
8: usb0
9: usb1
10: sct
11: ritimer
12: timer0
13: timer1
14: timer2
15: timer3
16: mcpwm
17: adc0
18: i2c0
19: i2c1
20: spi
21: adc1
22: ssp0
23: ssp1
24: usart0
25: uart1
26: usart2
27: usart3
28: i2s0
29: i2s1
30: spifi
31: sgpio
32: pin_int0
33: pin_int1
34: pin_int2
35: pin_int3
36: pin_int4
37: pin_int5
38: pin_int6
39: pin_int7
40: gint0
41: gint1
42: eventrouter
43: c_can1
# reserved: 44, 45
46: atimer
47: rtc
# reserved: 48
49: wwdt
# reserved: 50
51: c_can0
52: qei

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_MEMORYMAP_H
#define LPC43XX_MEMORYMAP_H
#include <libopencm3/cm3/common.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- LPC43XX specific peripheral definitions ----------------------------- */
/* local SRAM / external static memory banks (0x1000 0000 - 0x2000 0000) */
#define SPIFI_DATA_BASE 0x14000000
/* Memory map for all busses */
#define PERIPH_BASE_AHB 0x40000000
#define PERIPH_BASE_APB0 0x40080000
#define PERIPH_BASE_APB1 0x400A0000
#define PERIPH_BASE_APB2 0x400C0000
#define PERIPH_BASE_APB3 0x400E0000
/* Register boundary addresses */
/* AHB (0x4000 0000 - 0x4001 2000) */
#define SCT_BASE (PERIPH_BASE_AHB + 0x00000)
/* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */
#define GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)
#define SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)
#define SDIO_BASE (PERIPH_BASE_AHB + 0x04000)
#define EMC_BASE (PERIPH_BASE_AHB + 0x05000)
#define USB0_BASE (PERIPH_BASE_AHB + 0x06000)
#define USB1_BASE (PERIPH_BASE_AHB + 0x07000)
#define LCD_BASE (PERIPH_BASE_AHB + 0x08000)
/* PERIPH_BASE_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */
#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
/* 0x4001 2000 - 0x4003 FFFF Reserved */
/* RTC domain peripherals */
#define ATIMER_BASE 0x40040000
#define BACKUP_REG_BASE 0x40041000
#define PMC_BASE 0x40042000
#define CREG_BASE 0x40043000
#define EVENTROUTER_BASE 0x40044000
#define OTP_BASE 0x40045000
#define RTC_BASE 0x40046000
/* 0x4004 7000 - 0x4004 FFFF Reserved */
/* clocking/reset control peripherals */
#define CGU_BASE 0x40050000
#define CCU1_BASE 0x40051000
#define CCU2_BASE 0x40052000
#define RGU_BASE 0x40053000
/* 0x4005 4000 - 0x4005 FFFF Reserved */
/* 0x4006 0000 - 0x4007 FFFF Reserved */
/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */
#define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)
#define USART0_BASE (PERIPH_BASE_APB0 + 0x01000)
#define UART1_BASE (PERIPH_BASE_APB0 + 0x02000)
#define SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)
#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)
#define SCU_BASE (PERIPH_BASE_APB0 + 0x06000)
#define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)
#define GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)
#define GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)
/* 0x4008 A000 - 0x4008 FFFF Reserved */
/* 0x4009 0000 - 0x4009 FFFF Reserved */
/* APB1 (0x400A 0000 - 0x400A FFFF) */
#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)
#define I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)
#define I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)
#define I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)
#define C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)
/* 0x400A 5000 - 0x400A FFFF Reserved */
/* 0x400B 0000 - 0x400B FFFF Reserved */
/* APB2 (0x400C 0000 - 0x400C FFFF) */
#define RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)
#define USART2_BASE (PERIPH_BASE_APB2 + 0x01000)
#define USART3_BASE (PERIPH_BASE_APB2 + 0x02000)
#define TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)
#define TIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)
#define SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)
#define QEI_BASE (PERIPH_BASE_APB2 + 0x06000)
#define GIMA_BASE (PERIPH_BASE_APB2 + 0x07000)
/* 0x400C 8000 - 0x400C FFFF Reserved */
/* 0x400D 0000 - 0x400D FFFF Reserved */
/* APB3 (0x400E 0000 - 0x400E FFFF) */
#define I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)
#define DAC_BASE (PERIPH_BASE_APB3 + 0x01000)
#define C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)
#define ADC0_BASE (PERIPH_BASE_APB3 + 0x03000)
#define ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)
/* 0x400E 5000 - 0x400E FFFF Reserved */
/* 0x400F 0000 - 0x400F 0FFF Reserved */
#define AES_BASE 0x400F1000
/* 0x400F 2000 - 0x400F 3FFF Reserved */
#define GPIO_PORT_BASE 0x400F4000
/* 0x400F 8000 - 0x400F FFFF Reserved */
#define SPI_PORT_BASE 0x40100000
#define SGPIO_PORT_BASE 0x40101000
/* 0x4010 2000 - 0x41FF FFFF Reserved */
/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */
/* 0x4400 0000 - 0x5FFF FFFF Reserved */
/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */
#define SPIFI_DATA_UNCACHED_BASE 0x80000000
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup ritimer_defines Repetitive Interrupt Timer Defines
@brief <b>Defined Constants and Types for the LPC43xx Repetitive Interrupt
Timer</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@author @htmlonly &copy; @endhtmlonly 2014 Jared Boone <jared@sharebrained.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2014 Jared Boone <jared@sharebrained.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_RITIMER_H
#define LPC43XX_RITIMER_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Repetitive Interrupt Timer registers -------------------------------- */
/* Compare register */
#define RITIMER_COMPVAL MMIO32(RITIMER_BASE + 0x000)
/* Mask register */
#define RITIMER_MASK MMIO32(RITIMER_BASE + 0x004)
/* Control register */
#define RITIMER_CTRL MMIO32(RITIMER_BASE + 0x008)
/* 32-bit counter */
#define RITIMER_COUNTER MMIO32(RITIMER_BASE + 0x00C)
/* --- RITIMER_COMPVAL values ----------------------------------- */
/* RICOMP: Compare register */
#define RITIMER_COMPVAL_RICOMP_SHIFT (0)
#define RITIMER_COMPVAL_RICOMP_MASK (0xffffffff << RITIMER_COMPVAL_RICOMP_SHIFT)
#define RITIMER_COMPVAL_RICOMP(x) ((x) << RITIMER_COMPVAL_RICOMP_SHIFT)
/* --- RITIMER_MASK values -------------------------------------- */
/* RIMASK: Mask register */
#define RITIMER_MASK_RIMASK_SHIFT (0)
#define RITIMER_MASK_RIMASK_MASK (0xffffffff << RITIMER_MASK_RIMASK_SHIFT)
#define RITIMER_MASK_RIMASK(x) ((x) << RITIMER_MASK_RIMASK_SHIFT)
/* --- RITIMER_CTRL values -------------------------------------- */
/* RITINT: Interrupt flag */
#define RITIMER_CTRL_RITINT_SHIFT (0)
#define RITIMER_CTRL_RITINT_MASK (0x1 << RITIMER_CTRL_RITINT_SHIFT)
#define RITIMER_CTRL_RITINT(x) ((x) << RITIMER_CTRL_RITINT_SHIFT)
/* RITENCLR: Timer enable clear */
#define RITIMER_CTRL_RITENCLR_SHIFT (1)
#define RITIMER_CTRL_RITENCLR_MASK (0x1 << RITIMER_CTRL_RITENCLR_SHIFT)
#define RITIMER_CTRL_RITENCLR(x) ((x) << RITIMER_CTRL_RITENCLR_SHIFT)
/* RITENBR: Timer enable for debug */
#define RITIMER_CTRL_RITENBR_SHIFT (2)
#define RITIMER_CTRL_RITENBR_MASK (0x1 << RITIMER_CTRL_RITENBR_SHIFT)
#define RITIMER_CTRL_RITENBR(x) ((x) << RITIMER_CTRL_RITENBR_SHIFT)
/* RITEN: Timer enable */
#define RITIMER_CTRL_RITEN_SHIFT (3)
#define RITIMER_CTRL_RITEN_MASK (0x1 << RITIMER_CTRL_RITEN_SHIFT)
#define RITIMER_CTRL_RITEN(x) ((x) << RITIMER_CTRL_RITEN_SHIFT)
/* --- RITIMER_COUNTER values ----------------------------------- */
/* RICOUNTER: 32-bit up counter */
#define RITIMER_COUNTER_RICOUNTER_SHIFT (0)
#define RITIMER_COUNTER_RICOUNTER_MASK (0xffffffff << RITIMER_COUNTER_RICOUNTER_SHIFT)
#define RITIMER_COUNTER_RICOUNTER(x) ((x) << RITIMER_COUNTER_RICOUNTER_SHIFT)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup rtc_defines RTC Defines
@brief <b>Defined Constants and Types for the LPC43xx Real Time Clock (RTC)</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2014 Jared Boone <jared@sharebrained.com>
@date 2 January 2014
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2014 Jared Boone <jared@sharebrained.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_RTC_H
#define LPC43XX_RTC_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* RTC port base address (for convenience) */
#define RTC RTC_BASE
/* --- RTC registers ------------------------------------------------------- */
#define RTC_ILR MMIO32(RTC_BASE + 0x000)
#define RTC_CCR MMIO32(RTC_BASE + 0x008)
#define RTC_CIIR MMIO32(RTC_BASE + 0x00c)
#define RTC_AMR MMIO32(RTC_BASE + 0x010)
#define RTC_CTIME0 MMIO32(RTC_BASE + 0x014)
#define RTC_CTIME1 MMIO32(RTC_BASE + 0x018)
#define RTC_CTIME2 MMIO32(RTC_BASE + 0x01c)
#define RTC_SEC MMIO32(RTC_BASE + 0x020)
#define RTC_MIN MMIO32(RTC_BASE + 0x024)
#define RTC_HRS MMIO32(RTC_BASE + 0x028)
#define RTC_DOM MMIO32(RTC_BASE + 0x02c)
#define RTC_DOW MMIO32(RTC_BASE + 0x030)
#define RTC_DOY MMIO32(RTC_BASE + 0x034)
#define RTC_MONTH MMIO32(RTC_BASE + 0x038)
#define RTC_YEAR MMIO32(RTC_BASE + 0x03c)
#define RTC_CALIBRATION MMIO32(RTC_BASE + 0x040)
#define RTC_ASEC MMIO32(RTC_BASE + 0x060)
#define RTC_AMIN MMIO32(RTC_BASE + 0x064)
#define RTC_AHRS MMIO32(RTC_BASE + 0x068)
#define RTC_ADOM MMIO32(RTC_BASE + 0x06c)
#define RTC_ADOW MMIO32(RTC_BASE + 0x070)
#define RTC_ADOY MMIO32(RTC_BASE + 0x074)
#define RTC_AMON MMIO32(RTC_BASE + 0x078)
#define RTC_AYRS MMIO32(RTC_BASE + 0x07c)
/* --- RTC_ILR values ------------------------------------------- */
/* RTCCIF: Counter increment interrupt block interrupted */
#define RTC_ILR_RTCCIF_SHIFT (0)
#define RTC_ILR_RTCCIF_MASK (0x1 << RTC_ILR_RTCCIF_SHIFT)
#define RTC_ILR_RTCCIF(x) ((x) << RTC_ILR_RTCCIF_SHIFT)
/* RTCALF: Alarm interrupted */
#define RTC_ILR_RTCALF_SHIFT (1)
#define RTC_ILR_RTCALF_MASK (0x1 << RTC_ILR_RTCALF_SHIFT)
#define RTC_ILR_RTCALF(x) ((x) << RTC_ILR_RTCALF_SHIFT)
/* --- RTC_CCR values ------------------------------------------- */
/* CLKEN: Clock enable */
#define RTC_CCR_CLKEN_SHIFT (0)
#define RTC_CCR_CLKEN_MASK (0x1 << RTC_CCR_CLKEN_SHIFT)
#define RTC_CCR_CLKEN(x) ((x) << RTC_CCR_CLKEN_SHIFT)
/* CTCRST: CTC reset */
#define RTC_CCR_CTCRST_SHIFT (1)
#define RTC_CCR_CTCRST_MASK (0x1 << RTC_CCR_CTCRST_SHIFT)
#define RTC_CCR_CTCRST(x) ((x) << RTC_CCR_CTCRST_SHIFT)
/* CCALEN: Calibration counter enable */
#define RTC_CCR_CCALEN_SHIFT (4)
#define RTC_CCR_CCALEN_MASK (0x1 << RTC_CCR_CCALEN_SHIFT)
#define RTC_CCR_CCALEN(x) ((x) << RTC_CCR_CCALEN_SHIFT)
/* --- RTC_CIIR values ------------------------------------------ */
/* IMSEC: Second interrupt enable */
#define RTC_CIIR_IMSEC_SHIFT (0)
#define RTC_CIIR_IMSEC_MASK (0x1 << RTC_CIIR_IMSEC_SHIFT)
#define RTC_CIIR_IMSEC(x) ((x) << RTC_CIIR_IMSEC_SHIFT)
/* IMMIN: Minute interrupt enable */
#define RTC_CIIR_IMMIN_SHIFT (1)
#define RTC_CIIR_IMMIN_MASK (0x1 << RTC_CIIR_IMMIN_SHIFT)
#define RTC_CIIR_IMMIN(x) ((x) << RTC_CIIR_IMMIN_SHIFT)
/* IMHOUR: Hour interrupt enable */
#define RTC_CIIR_IMHOUR_SHIFT (2)
#define RTC_CIIR_IMHOUR_MASK (0x1 << RTC_CIIR_IMHOUR_SHIFT)
#define RTC_CIIR_IMHOUR(x) ((x) << RTC_CIIR_IMHOUR_SHIFT)
/* IMDOM: Day of month interrupt enable */
#define RTC_CIIR_IMDOM_SHIFT (3)
#define RTC_CIIR_IMDOM_MASK (0x1 << RTC_CIIR_IMDOM_SHIFT)
#define RTC_CIIR_IMDOM(x) ((x) << RTC_CIIR_IMDOM_SHIFT)
/* IMDOW: Day of week interrupt enable */
#define RTC_CIIR_IMDOW_SHIFT (4)
#define RTC_CIIR_IMDOW_MASK (0x1 << RTC_CIIR_IMDOW_SHIFT)
#define RTC_CIIR_IMDOW(x) ((x) << RTC_CIIR_IMDOW_SHIFT)
/* IMDOY: Day of year interrupt enable */
#define RTC_CIIR_IMDOY_SHIFT (5)
#define RTC_CIIR_IMDOY_MASK (0x1 << RTC_CIIR_IMDOY_SHIFT)
#define RTC_CIIR_IMDOY(x) ((x) << RTC_CIIR_IMDOY_SHIFT)
/* IMMON: Month interrupt enable */
#define RTC_CIIR_IMMON_SHIFT (6)
#define RTC_CIIR_IMMON_MASK (0x1 << RTC_CIIR_IMMON_SHIFT)
#define RTC_CIIR_IMMON(x) ((x) << RTC_CIIR_IMMON_SHIFT)
/* IMYEAR: Year interrupt enable */
#define RTC_CIIR_IMYEAR_SHIFT (7)
#define RTC_CIIR_IMYEAR_MASK (0x1 << RTC_CIIR_IMYEAR_SHIFT)
#define RTC_CIIR_IMYEAR(x) ((x) << RTC_CIIR_IMYEAR_SHIFT)
/* --- RTC_AMR values ------------------------------------------- */
/* AMRSEC: Second not compared for alarm */
#define RTC_AMR_AMRSEC_SHIFT (0)
#define RTC_AMR_AMRSEC_MASK (0x1 << RTC_AMR_AMRSEC_SHIFT)
#define RTC_AMR_AMRSEC(x) ((x) << RTC_AMR_AMRSEC_SHIFT)
/* AMRMIN: Minute not compared for alarm */
#define RTC_AMR_AMRMIN_SHIFT (1)
#define RTC_AMR_AMRMIN_MASK (0x1 << RTC_AMR_AMRMIN_SHIFT)
#define RTC_AMR_AMRMIN(x) ((x) << RTC_AMR_AMRMIN_SHIFT)
/* AMRHOUR: Hour not compared for alarm */
#define RTC_AMR_AMRHOUR_SHIFT (2)
#define RTC_AMR_AMRHOUR_MASK (0x1 << RTC_AMR_AMRHOUR_SHIFT)
#define RTC_AMR_AMRHOUR(x) ((x) << RTC_AMR_AMRHOUR_SHIFT)
/* AMRDOM: Day of month not compared for alarm */
#define RTC_AMR_AMRDOM_SHIFT (3)
#define RTC_AMR_AMRDOM_MASK (0x1 << RTC_AMR_AMRDOM_SHIFT)
#define RTC_AMR_AMRDOM(x) ((x) << RTC_AMR_AMRDOM_SHIFT)
/* AMRDOW: Day of week not compared for alarm */
#define RTC_AMR_AMRDOW_SHIFT (4)
#define RTC_AMR_AMRDOW_MASK (0x1 << RTC_AMR_AMRDOW_SHIFT)
#define RTC_AMR_AMRDOW(x) ((x) << RTC_AMR_AMRDOW_SHIFT)
/* AMRDOY: Day of year not compared for alarm */
#define RTC_AMR_AMRDOY_SHIFT (5)
#define RTC_AMR_AMRDOY_MASK (0x1 << RTC_AMR_AMRDOY_SHIFT)
#define RTC_AMR_AMRDOY(x) ((x) << RTC_AMR_AMRDOY_SHIFT)
/* AMRMON: Month not compared for alarm */
#define RTC_AMR_AMRMON_SHIFT (6)
#define RTC_AMR_AMRMON_MASK (0x1 << RTC_AMR_AMRMON_SHIFT)
#define RTC_AMR_AMRMON(x) ((x) << RTC_AMR_AMRMON_SHIFT)
/* AMRYEAR: Year not compared for alarm */
#define RTC_AMR_AMRYEAR_SHIFT (7)
#define RTC_AMR_AMRYEAR_MASK (0x1 << RTC_AMR_AMRYEAR_SHIFT)
#define RTC_AMR_AMRYEAR(x) ((x) << RTC_AMR_AMRYEAR_SHIFT)
/* --- RTC_CTIME0 values ---------------------------------------- */
/* SECONDS: Seconds */
#define RTC_CTIME0_SECONDS_SHIFT (0)
#define RTC_CTIME0_SECONDS_MASK (0x3f << RTC_CTIME0_SECONDS_SHIFT)
#define RTC_CTIME0_SECONDS(x) ((x) << RTC_CTIME0_SECONDS_SHIFT)
/* MINUTES: Minutes */
#define RTC_CTIME0_MINUTES_SHIFT (8)
#define RTC_CTIME0_MINUTES_MASK (0x3f << RTC_CTIME0_MINUTES_SHIFT)
#define RTC_CTIME0_MINUTES(x) ((x) << RTC_CTIME0_MINUTES_SHIFT)
/* HOURS: Hours */
#define RTC_CTIME0_HOURS_SHIFT (16)
#define RTC_CTIME0_HOURS_MASK (0x1f << RTC_CTIME0_HOURS_SHIFT)
#define RTC_CTIME0_HOURS(x) ((x) << RTC_CTIME0_HOURS_SHIFT)
/* DOW: Day of week */
#define RTC_CTIME0_DOW_SHIFT (24)
#define RTC_CTIME0_DOW_MASK (0x7 << RTC_CTIME0_DOW_SHIFT)
#define RTC_CTIME0_DOW(x) ((x) << RTC_CTIME0_DOW_SHIFT)
/* --- RTC_CTIME1 values ---------------------------------------- */
/* DOM: Day of month */
#define RTC_CTIME1_DOM_SHIFT (0)
#define RTC_CTIME1_DOM_MASK (0x1f << RTC_CTIME1_DOM_SHIFT)
#define RTC_CTIME1_DOM(x) ((x) << RTC_CTIME1_DOM_SHIFT)
/* MONTH: Month */
#define RTC_CTIME1_MONTH_SHIFT (8)
#define RTC_CTIME1_MONTH_MASK (0xf << RTC_CTIME1_MONTH_SHIFT)
#define RTC_CTIME1_MONTH(x) ((x) << RTC_CTIME1_MONTH_SHIFT)
/* YEAR: Year */
#define RTC_CTIME1_YEAR_SHIFT (16)
#define RTC_CTIME1_YEAR_MASK (0xfff << RTC_CTIME1_YEAR_SHIFT)
#define RTC_CTIME1_YEAR(x) ((x) << RTC_CTIME1_YEAR_SHIFT)
/* --- RTC_CTIME2 values ---------------------------------------- */
/* DOY: Day of year */
#define RTC_CTIME2_DOY_SHIFT (0)
#define RTC_CTIME2_DOY_MASK (0xfff << RTC_CTIME2_DOY_SHIFT)
#define RTC_CTIME2_DOY(x) ((x) << RTC_CTIME2_DOY_SHIFT)
/* --- RTC_SEC values ------------------------------------------- */
/* SECONDS: Seconds */
#define RTC_SEC_SECONDS_SHIFT (0)
#define RTC_SEC_SECONDS_MASK (0x3f << RTC_SEC_SECONDS_SHIFT)
#define RTC_SEC_SECONDS(x) ((x) << RTC_SEC_SECONDS_SHIFT)
/* --- RTC_MIN values ------------------------------------------- */
/* MINUTES: Minutes */
#define RTC_MIN_MINUTES_SHIFT (0)
#define RTC_MIN_MINUTES_MASK (0x3f << RTC_MIN_MINUTES_SHIFT)
#define RTC_MIN_MINUTES(x) ((x) << RTC_MIN_MINUTES_SHIFT)
/* --- RTC_HRS values ------------------------------------------- */
/* HOURS: Hours */
#define RTC_HRS_HOURS_SHIFT (0)
#define RTC_HRS_HOURS_MASK (0x1f << RTC_HRS_HOURS_SHIFT)
#define RTC_HRS_HOURS(x) ((x) << RTC_HRS_HOURS_SHIFT)
/* --- RTC_DOM values ------------------------------------------- */
/* DOM: Day of month */
#define RTC_DOM_DOM_SHIFT (0)
#define RTC_DOM_DOM_MASK (0x1f << RTC_DOM_DOM_SHIFT)
#define RTC_DOM_DOM(x) ((x) << RTC_DOM_DOM_SHIFT)
/* --- RTC_DOW values ------------------------------------------- */
/* DOW: Day of week */
#define RTC_DOW_DOW_SHIFT (0)
#define RTC_DOW_DOW_MASK (0x7 << RTC_DOW_DOW_SHIFT)
#define RTC_DOW_DOW(x) ((x) << RTC_DOW_DOW_SHIFT)
/* --- RTC_DOY values ------------------------------------------- */
/* DOY: Day of year */
#define RTC_DOY_DOY_SHIFT (0)
#define RTC_DOY_DOY_MASK (0x1ff << RTC_DOY_DOY_SHIFT)
#define RTC_DOY_DOY(x) ((x) << RTC_DOY_DOY_SHIFT)
/* --- RTC_MONTH values ----------------------------------------- */
/* MONTH: Month */
#define RTC_MONTH_MONTH_SHIFT (0)
#define RTC_MONTH_MONTH_MASK (0xf << RTC_MONTH_MONTH_SHIFT)
#define RTC_MONTH_MONTH(x) ((x) << RTC_MONTH_MONTH_SHIFT)
/* --- RTC_YEAR values ------------------------------------------ */
/* YEAR: Year */
#define RTC_YEAR_YEAR_SHIFT (0)
#define RTC_YEAR_YEAR_MASK (0xfff << RTC_YEAR_YEAR_SHIFT)
#define RTC_YEAR_YEAR(x) ((x) << RTC_YEAR_YEAR_SHIFT)
/* --- RTC_CALIBRATION values ----------------------------------- */
/* CALVAL: Calibration counter max */
#define RTC_CALIBRATION_CALVAL_SHIFT (0)
#define RTC_CALIBRATION_CALVAL_MASK (0x1ffff << RTC_CALIBRATION_CALVAL_SHIFT)
#define RTC_CALIBRATION_CALVAL(x) ((x) << RTC_CALIBRATION_CALVAL_SHIFT)
/* CALDIR: Calibration counter direction */
#define RTC_CALIBRATION_CALDIR_SHIFT (17)
#define RTC_CALIBRATION_CALDIR_MASK (0x1 << RTC_CALIBRATION_CALDIR_SHIFT)
#define RTC_CALIBRATION_CALDIR(x) ((x) << RTC_CALIBRATION_CALDIR_SHIFT)
/* --- RTC_ASEC values ------------------------------------------ */
/* SECONDS: Alarm seconds */
#define RTC_ASEC_SECONDS_SHIFT (0)
#define RTC_ASEC_SECONDS_MASK (0x3f << RTC_ASEC_SECONDS_SHIFT)
#define RTC_ASEC_SECONDS(x) ((x) << RTC_ASEC_SECONDS_SHIFT)
/* --- RTC_AMIN values ------------------------------------------ */
/* MINUTES: Alarm minutes */
#define RTC_AMIN_MINUTES_SHIFT (0)
#define RTC_AMIN_MINUTES_MASK (0x3f << RTC_AMIN_MINUTES_SHIFT)
#define RTC_AMIN_MINUTES(x) ((x) << RTC_AMIN_MINUTES_SHIFT)
/* --- RTC_AHRS values ------------------------------------------ */
/* HOURS: Alarm hours */
#define RTC_AHRS_HOURS_SHIFT (0)
#define RTC_AHRS_HOURS_MASK (0x1f << RTC_AHRS_HOURS_SHIFT)
#define RTC_AHRS_HOURS(x) ((x) << RTC_AHRS_HOURS_SHIFT)
/* --- RTC_ADOM values ------------------------------------------ */
/* DOM: Alarm day of month */
#define RTC_ADOM_DOM_SHIFT (0)
#define RTC_ADOM_DOM_MASK (0x1f << RTC_ADOM_DOM_SHIFT)
#define RTC_ADOM_DOM(x) ((x) << RTC_ADOM_DOM_SHIFT)
/* --- RTC_ADOW values ------------------------------------------ */
/* DOW: Alarm day of week */
#define RTC_ADOW_DOW_SHIFT (0)
#define RTC_ADOW_DOW_MASK (0x7 << RTC_ADOW_DOW_SHIFT)
#define RTC_ADOW_DOW(x) ((x) << RTC_ADOW_DOW_SHIFT)
/* --- RTC_ADOY values ------------------------------------------ */
/* DOY: Alarm day of year */
#define RTC_ADOY_DOY_SHIFT (0)
#define RTC_ADOY_DOY_MASK (0x1ff << RTC_ADOY_DOY_SHIFT)
#define RTC_ADOY_DOY(x) ((x) << RTC_ADOY_DOY_SHIFT)
/* --- RTC_AMON values ------------------------------------------ */
/* MONTH: Alarm month */
#define RTC_AMON_MONTH_SHIFT (0)
#define RTC_AMON_MONTH_MASK (0xf << RTC_AMON_MONTH_SHIFT)
#define RTC_AMON_MONTH(x) ((x) << RTC_AMON_MONTH_SHIFT)
/* --- RTC_AYRS values ------------------------------------------ */
/* YEAR: Alarm year */
#define RTC_AYRS_YEAR_SHIFT (0)
#define RTC_AYRS_YEAR_MASK (0xfff << RTC_AYRS_YEAR_SHIFT)
#define RTC_AYRS_YEAR(x) ((x) << RTC_AYRS_YEAR_SHIFT)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup scu_defines System Control Unit Defines
@brief <b>Defined Constants and Types for the LPC43xx System Control Unit</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_SCU_H
#define LPC43XX_SCU_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* Pin group base addresses */
#define PIN_GROUP0 (SCU_BASE + 0x000)
#define PIN_GROUP1 (SCU_BASE + 0x080)
#define PIN_GROUP2 (SCU_BASE + 0x100)
#define PIN_GROUP3 (SCU_BASE + 0x180)
#define PIN_GROUP4 (SCU_BASE + 0x200)
#define PIN_GROUP5 (SCU_BASE + 0x280)
#define PIN_GROUP6 (SCU_BASE + 0x300)
#define PIN_GROUP7 (SCU_BASE + 0x380)
#define PIN_GROUP8 (SCU_BASE + 0x400)
#define PIN_GROUP9 (SCU_BASE + 0x480)
#define PIN_GROUPA (SCU_BASE + 0x500)
#define PIN_GROUPB (SCU_BASE + 0x580)
#define PIN_GROUPC (SCU_BASE + 0x600)
#define PIN_GROUPD (SCU_BASE + 0x680)
#define PIN_GROUPE (SCU_BASE + 0x700)
#define PIN_GROUPF (SCU_BASE + 0x780)
#define PIN0 0x000
#define PIN1 0x004
#define PIN2 0x008
#define PIN3 0x00C
#define PIN4 0x010
#define PIN5 0x014
#define PIN6 0x018
#define PIN7 0x01C
#define PIN8 0x020
#define PIN9 0x024
#define PIN10 0x028
#define PIN11 0x02C
#define PIN12 0x030
#define PIN13 0x034
#define PIN14 0x038
#define PIN15 0x03C
#define PIN16 0x040
#define PIN17 0x044
#define PIN18 0x048
#define PIN19 0x04C
#define PIN20 0x050
/* --- SCU registers ------------------------------------------------------- */
/* Pin configuration registers */
#define SCU_SFS(group, pin) MMIO32(group + pin)
/* Pins P0_n */
#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0)
#define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1)
/* Pins P1_n */
#define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0)
#define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1)
#define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2)
#define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3)
#define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4)
#define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5)
#define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6)
#define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7)
#define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8)
#define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9)
#define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10)
#define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11)
#define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12)
#define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13)
#define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14)
#define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15)
#define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16)
#define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17)
#define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18)
#define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19)
#define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20)
/* Pins P2_n */
#define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0)
#define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1)
#define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2)
#define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3)
#define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4)
#define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5)
#define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6)
#define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7)
#define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8)
#define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9)
#define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10)
#define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11)
#define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12)
#define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13)
/* Pins P3_n */
#define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0)
#define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1)
#define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2)
#define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3)
#define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4)
#define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5)
#define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6)
#define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7)
#define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8)
/* Pins P4_n */
#define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0)
#define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1)
#define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2)
#define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3)
#define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4)
#define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5)
#define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6)
#define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7)
#define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8)
#define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9)
#define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10)
/* Pins P5_n */
#define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0)
#define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1)
#define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2)
#define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3)
#define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4)
#define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5)
#define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6)
#define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7)
/* Pins P6_n */
#define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0)
#define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1)
#define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2)
#define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3)
#define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4)
#define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5)
#define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6)
#define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7)
#define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8)
#define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9)
#define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10)
#define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11)
#define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12)
/* Pins P7_n */
#define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0)
#define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1)
#define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2)
#define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3)
#define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4)
#define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5)
#define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6)
#define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7)
/* Pins P8_n */
#define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0)
#define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1)
#define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2)
#define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3)
#define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4)
#define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5)
#define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6)
#define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7)
#define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8)
/* Pins P9_n */
#define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0)
#define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1)
#define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2)
#define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3)
#define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4)
#define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5)
#define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6)
/* Pins PA_n */
#define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0)
#define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1)
#define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2)
#define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3)
#define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4)
/* Pins PB_n */
#define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0)
#define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1)
#define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2)
#define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3)
#define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4)
#define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5)
#define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6)
/* Pins PC_n */
#define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0)
#define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1)
#define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2)
#define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3)
#define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4)
#define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5)
#define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6)
#define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7)
#define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8)
#define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9)
#define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10)
#define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11)
#define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12)
#define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13)
#define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14)
/* Pins PD_n */
#define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0)
#define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1)
#define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2)
#define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3)
#define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4)
#define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5)
#define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6)
#define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7)
#define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8)
#define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9)
#define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10)
#define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11)
#define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12)
#define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13)
#define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14)
#define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15)
#define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16)
/* Pins PE_n */
#define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0)
#define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1)
#define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2)
#define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3)
#define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4)
#define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5)
#define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6)
#define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7)
#define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8)
#define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9)
#define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10)
#define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11)
#define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12)
#define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13)
#define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14)
#define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15)
/* Pins PF_n */
#define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0)
#define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1)
#define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2)
#define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3)
#define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4)
#define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5)
#define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6)
#define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7)
#define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8)
#define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9)
#define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10)
#define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11)
/* CLKn pins */
#define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00)
#define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04)
#define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08)
#define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C)
/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */
#define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80)
#define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84)
/* ADC pin select registers */
/* ADC0 function select register */
#define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88)
/* ADC1 function select register */
#define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C)
/* Analog function select register */
#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90)
/* EMC clock delay register */
#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00)
/* Pin interrupt select registers */
/* Pin interrupt select register for pin interrupts 0 to 3 */
#define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00)
/* Pin interrupt select register for pin interrupts 4 to 7 */
#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04)
/**************************/
/* SCU I2C0 Configuration */
/**************************/
/*
* Select input glitch filter time constant for the SCL pin.
* 0 = 50 ns glitch filter.
* 1 = 3ns glitch filter.
*/
#define SCU_SCL_EFP (BIT0)
/* BIT1 Reserved. Always write a 0 to this bit. */
/*
* Select I2C mode for the SCL pin.
* 0 = Standard/Fast mode transmit.
* 1 = Fast-mode Plus transmit.
*/
#define SCU_SCL_EHD (BIT2)
/*
* Enable the input receiver for the SCL pin.
* Always write a 1 to this bit when using the
* I2C0.
* 0 = Disabled.
* 1 = Enabled.
*/
#define SCU_SCL_EZI_EN (BIT3)
/* BIT4-6 Reserved. */
/*
* Enable or disable input glitch filter for the
* SCL pin. The filter time constant is
* determined by bit EFP.
* 0 = Enable input filter.
* 1 = Disable input filter.
*/
#define SCU_SCL_ZIF_DIS (BIT7)
/*
* Select input glitch filter time constant for the SDA pin.
* 0 = 50 ns glitch filter.
* 1 = 3ns glitch filter.
*/
#define SCU_SDA_EFP (BIT8)
/* BIT9 Reserved. Always write a 0 to this bit. */
/*
* Select I2C mode for the SDA pin.
* 0 = Standard/Fast mode transmit.
* 1 = Fast-mode Plus transmit.
*/
#define SCU_SDA_EHD (BIT10)
/*
* Enable the input receiver for the SDA pin.
* Always write a 1 to this bit when using the
* I2C0.
* 0 = Disabled.
* 1 = Enabled.
*/
#define SCU_SDA_EZI_EN (BIT11)
/* BIT 12-14 - Reserved */
/*
* Enable or disable input glitch filter for the
* SDA pin. The filter time constant is
* determined by bit SDA_EFP.
* 0 = Enable input filter.
* 1 = Disable input filter.
*/
#define SCU_SDA_ZIF_DIS (BIT15)
/* Standard mode for I2C SCL/SDA Standard/Fast mode */
#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN)
/* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */
#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | \
SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | \
SCU_SDA_EZI_EN)
/*
* SCU PIN Normal Drive:
* The configuration registers for normal-drive pins control the following pins:
* - P0_0 and P0_1
* - P1_0 to P1_16 and P1_18 to P1_20
* - P2_0 to P2_2 and P2_6 to P2_13
* - P3_0 to P3_2 and P3_4 to P3_8
* - P4_0 to P4_10
* - P5_0 to P5_7
* - P6_0 to P6_12
* - P7_0 to P7_7
* - P8_3 to P8_8
* - P9_0 to P9_6
* - PA_0 and PA_4
* - PB_0 to PB_6
* - PC_0 to PC_14
* - PE_0 to PE_15
* - PF_0 to PF_11
*
* Pin configuration registers for High-Drive pins.
* The configuration registers for high-drive pins control the following pins:
* - P1_17
* - P2_3 to P2_5
* - P8_0 to P8_2
* - PA_1 to PA_3
*
* Pin configuration registers for High-Speed pins.
* This register controls the following pins:
* - P3_3 and pins CLK0 to CLK3.
*/
typedef enum {
/* Group Port 0 */
P0_0 = (PIN_GROUP0+PIN0),
P0_1 = (PIN_GROUP0+PIN1),
/* Group Port 1 */
P1_0 = (PIN_GROUP1+PIN0),
P1_1 = (PIN_GROUP1+PIN1),
P1_2 = (PIN_GROUP1+PIN2),
P1_3 = (PIN_GROUP1+PIN3),
P1_4 = (PIN_GROUP1+PIN4),
P1_5 = (PIN_GROUP1+PIN5),
P1_6 = (PIN_GROUP1+PIN6),
P1_7 = (PIN_GROUP1+PIN7),
P1_8 = (PIN_GROUP1+PIN8),
P1_9 = (PIN_GROUP1+PIN9),
P1_10 = (PIN_GROUP1+PIN10),
P1_11 = (PIN_GROUP1+PIN11),
P1_12 = (PIN_GROUP1+PIN12),
P1_13 = (PIN_GROUP1+PIN13),
P1_14 = (PIN_GROUP1+PIN14),
P1_15 = (PIN_GROUP1+PIN15),
P1_16 = (PIN_GROUP1+PIN16),
/* P1_17 is High-Drive pin */
P1_17 = (PIN_GROUP1+PIN17),
P1_18 = (PIN_GROUP1+PIN18),
P1_19 = (PIN_GROUP1+PIN19),
P1_20 = (PIN_GROUP1+PIN20),
/* Group Port 2 */
P2_0 = (PIN_GROUP2+PIN0),
P2_1 = (PIN_GROUP2+PIN1),
P2_2 = (PIN_GROUP2+PIN2),
/* P2_3 to P2_5 are High-Drive pins */
P2_3 = (PIN_GROUP2+PIN3),
P2_4 = (PIN_GROUP2+PIN4),
P2_5 = (PIN_GROUP2+PIN5),
P2_6 = (PIN_GROUP2+PIN6),
P2_7 = (PIN_GROUP2+PIN7),
P2_8 = (PIN_GROUP2+PIN8),
P2_9 = (PIN_GROUP2+PIN9),
P2_10 = (PIN_GROUP2+PIN10),
P2_11 = (PIN_GROUP2+PIN11),
P2_12 = (PIN_GROUP2+PIN12),
P2_13 = (PIN_GROUP2+PIN13),
/* Group Port 3 */
P3_0 = (PIN_GROUP3+PIN0),
P3_1 = (PIN_GROUP3+PIN1),
P3_2 = (PIN_GROUP3+PIN2),
/* P3_3 is High-Speed pin */
P3_3 = (PIN_GROUP3+PIN3),
P3_4 = (PIN_GROUP3+PIN4),
P3_5 = (PIN_GROUP3+PIN5),
P3_6 = (PIN_GROUP3+PIN6),
P3_7 = (PIN_GROUP3+PIN7),
P3_8 = (PIN_GROUP3+PIN8),
/* Group Port 4 */
P4_0 = (PIN_GROUP4+PIN0),
P4_1 = (PIN_GROUP4+PIN1),
P4_2 = (PIN_GROUP4+PIN2),
P4_3 = (PIN_GROUP4+PIN3),
P4_4 = (PIN_GROUP4+PIN4),
P4_5 = (PIN_GROUP4+PIN5),
P4_6 = (PIN_GROUP4+PIN6),
P4_7 = (PIN_GROUP4+PIN7),
P4_8 = (PIN_GROUP4+PIN8),
P4_9 = (PIN_GROUP4+PIN9),
P4_10 = (PIN_GROUP4+PIN10),
/* Group Port 5 */
P5_0 = (PIN_GROUP5+PIN0),
P5_1 = (PIN_GROUP5+PIN1),
P5_2 = (PIN_GROUP5+PIN2),
P5_3 = (PIN_GROUP5+PIN3),
P5_4 = (PIN_GROUP5+PIN4),
P5_5 = (PIN_GROUP5+PIN5),
P5_6 = (PIN_GROUP5+PIN6),
P5_7 = (PIN_GROUP5+PIN7),
/* Group Port 6 */
P6_0 = (PIN_GROUP6+PIN0),
P6_1 = (PIN_GROUP6+PIN1),
P6_2 = (PIN_GROUP6+PIN2),
P6_3 = (PIN_GROUP6+PIN3),
P6_4 = (PIN_GROUP6+PIN4),
P6_5 = (PIN_GROUP6+PIN5),
P6_6 = (PIN_GROUP6+PIN6),
P6_7 = (PIN_GROUP6+PIN7),
P6_8 = (PIN_GROUP6+PIN8),
P6_9 = (PIN_GROUP6+PIN9),
P6_10 = (PIN_GROUP6+PIN10),
P6_11 = (PIN_GROUP6+PIN11),
P6_12 = (PIN_GROUP6+PIN12),
/* Group Port 7 */
P7_0 = (PIN_GROUP7+PIN0),
P7_1 = (PIN_GROUP7+PIN1),
P7_2 = (PIN_GROUP7+PIN2),
P7_3 = (PIN_GROUP7+PIN3),
P7_4 = (PIN_GROUP7+PIN4),
P7_5 = (PIN_GROUP7+PIN5),
P7_6 = (PIN_GROUP7+PIN6),
P7_7 = (PIN_GROUP7+PIN7),
/* Group Port 8 */
/* P8_0 to P8_2 are High-Drive pins */
P8_0 = (PIN_GROUP8+PIN0),
P8_1 = (PIN_GROUP8+PIN1),
P8_2 = (PIN_GROUP8+PIN2),
P8_3 = (PIN_GROUP8+PIN3),
P8_4 = (PIN_GROUP8+PIN4),
P8_5 = (PIN_GROUP8+PIN5),
P8_6 = (PIN_GROUP8+PIN6),
P8_7 = (PIN_GROUP8+PIN7),
P8_8 = (PIN_GROUP8+PIN8),
/* Group Port 9 */
P9_0 = (PIN_GROUP9+PIN0),
P9_1 = (PIN_GROUP9+PIN1),
P9_2 = (PIN_GROUP9+PIN2),
P9_3 = (PIN_GROUP9+PIN3),
P9_4 = (PIN_GROUP9+PIN4),
P9_5 = (PIN_GROUP9+PIN5),
P9_6 = (PIN_GROUP9+PIN6),
/* Group Port A */
PA_0 = (PIN_GROUPA+PIN0),
/* PA_1 to PA_3 are Normal & High-Drive Pins */
PA_1 = (PIN_GROUPA+PIN1),
PA_2 = (PIN_GROUPA+PIN2),
PA_3 = (PIN_GROUPA+PIN3),
PA_4 = (PIN_GROUPA+PIN4),
/* Group Port B */
PB_0 = (PIN_GROUPB+PIN0),
PB_1 = (PIN_GROUPB+PIN1),
PB_2 = (PIN_GROUPB+PIN2),
PB_3 = (PIN_GROUPB+PIN3),
PB_4 = (PIN_GROUPB+PIN4),
PB_5 = (PIN_GROUPB+PIN5),
PB_6 = (PIN_GROUPB+PIN6),
/* Group Port C */
PC_0 = (PIN_GROUPC+PIN0),
PC_1 = (PIN_GROUPC+PIN1),
PC_2 = (PIN_GROUPC+PIN2),
PC_3 = (PIN_GROUPC+PIN3),
PC_4 = (PIN_GROUPC+PIN4),
PC_5 = (PIN_GROUPC+PIN5),
PC_6 = (PIN_GROUPC+PIN6),
PC_7 = (PIN_GROUPC+PIN7),
PC_8 = (PIN_GROUPC+PIN8),
PC_9 = (PIN_GROUPC+PIN9),
PC_10 = (PIN_GROUPC+PIN10),
PC_11 = (PIN_GROUPC+PIN11),
PC_12 = (PIN_GROUPC+PIN12),
PC_13 = (PIN_GROUPC+PIN13),
PC_14 = (PIN_GROUPC+PIN14),
/* Group Port D (seems not configurable through SCU, not defined in
* UM10503.pdf Rev.1, keep it here)
*/
PD_0 = (PIN_GROUPD+PIN0),
PD_1 = (PIN_GROUPD+PIN1),
PD_2 = (PIN_GROUPD+PIN2),
PD_3 = (PIN_GROUPD+PIN3),
PD_4 = (PIN_GROUPD+PIN4),
PD_5 = (PIN_GROUPD+PIN5),
PD_6 = (PIN_GROUPD+PIN6),
PD_7 = (PIN_GROUPD+PIN7),
PD_8 = (PIN_GROUPD+PIN8),
PD_9 = (PIN_GROUPD+PIN9),
PD_10 = (PIN_GROUPD+PIN10),
PD_11 = (PIN_GROUPD+PIN11),
PD_12 = (PIN_GROUPD+PIN12),
PD_13 = (PIN_GROUPD+PIN13),
PD_14 = (PIN_GROUPD+PIN14),
PD_15 = (PIN_GROUPD+PIN15),
PD_16 = (PIN_GROUPD+PIN16),
/* Group Port E */
PE_0 = (PIN_GROUPE+PIN0),
PE_1 = (PIN_GROUPE+PIN1),
PE_2 = (PIN_GROUPE+PIN2),
PE_3 = (PIN_GROUPE+PIN3),
PE_4 = (PIN_GROUPE+PIN4),
PE_5 = (PIN_GROUPE+PIN5),
PE_6 = (PIN_GROUPE+PIN6),
PE_7 = (PIN_GROUPE+PIN7),
PE_8 = (PIN_GROUPE+PIN8),
PE_9 = (PIN_GROUPE+PIN9),
PE_10 = (PIN_GROUPE+PIN10),
PE_11 = (PIN_GROUPE+PIN11),
PE_12 = (PIN_GROUPE+PIN12),
PE_13 = (PIN_GROUPE+PIN13),
PE_14 = (PIN_GROUPE+PIN14),
PE_15 = (PIN_GROUPE+PIN15),
/* Group Port F */
PF_0 = (PIN_GROUPF+PIN0),
PF_1 = (PIN_GROUPF+PIN1),
PF_2 = (PIN_GROUPF+PIN2),
PF_3 = (PIN_GROUPF+PIN3),
PF_4 = (PIN_GROUPF+PIN4),
PF_5 = (PIN_GROUPF+PIN5),
PF_6 = (PIN_GROUPF+PIN6),
PF_7 = (PIN_GROUPF+PIN7),
PF_8 = (PIN_GROUPF+PIN8),
PF_9 = (PIN_GROUPF+PIN9),
PF_10 = (PIN_GROUPF+PIN10),
PF_11 = (PIN_GROUPF+PIN11),
/* Group Clock 0 to 3 High-Speed pins */
CLK0 = (SCU_BASE + 0xC00),
CLK1 = (SCU_BASE + 0xC04),
CLK2 = (SCU_BASE + 0xC08),
CLK3 = (SCU_BASE + 0xC0C)
} scu_grp_pin_t;
/*
* Pin Configuration to be used for scu_pinmux() parameter scu_conf
* For normal-drive pins, high-drive pins, high-speed pins
*/
/*
* Function BIT0 to 2.
* Common to normal-drive pins, high-drive pins, high-speed pins.
*/
#define SCU_CONF_FUNCTION0 (0x0)
#define SCU_CONF_FUNCTION1 (0x1)
#define SCU_CONF_FUNCTION2 (0x2)
#define SCU_CONF_FUNCTION3 (0x3)
#define SCU_CONF_FUNCTION4 (0x4)
#define SCU_CONF_FUNCTION5 (0x5)
#define SCU_CONF_FUNCTION6 (0x6)
#define SCU_CONF_FUNCTION7 (0x7)
/*
* Enable pull-down resistor at pad
* By default=0 Disable pull-down.
* Available to normal-drive pins, high-drive pins, high-speed pins
*/
#define SCU_CONF_EPD_EN_PULLDOWN (BIT3)
/*
* Disable pull-up resistor at pad.
* By default=0 the pull-up resistor is enabled at reset.
* Available to normal-drive pins, high-drive pins, high-speed pins
*/
#define SCU_CONF_EPUN_DIS_PULLUP (BIT4)
/*
* Select Slew Rate.
* By Default=0 Slow.
* Available to normal-drive and high-speed pins, reserved for high-drive pins.
*/
#define SCU_CONF_EHS_FAST (BIT5)
/*
* Input buffer enable.
* By Default=0 Disable Input Buffer.
* The input buffer is disabled by default at reset and must be enabled for
* receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer
* to the pad(in high-drive pins).
* Available to normal-drive pins, high-drive pins, high-speed pins.
*/
#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6)
/*
* Input glitch filter. Disable the input glitch filter for clocking signals
* higher than 30 MHz.
* Available to normal-drive pins, high-drive pins, high-speed pins.
*/
#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7)
/*
* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9).
* Available to high-drive pins, reserved for others.
*/
#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100)
#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200)
#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300)
/* BIT10 to 31 are Reserved */
/* Configuration for different I/O pins types */
#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EPD_EN_PULLDOWN | \
SCU_CONF_EZI_EN_IN_BUFFER)
#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | \
SCU_CONF_EHS_FAST | \
SCU_CONF_EZI_EN_IN_BUFFER | \
SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
BEGIN_DECLS
void scu_pinmux(scu_grp_pin_t group_pin, uint32_t scu_conf);
END_DECLS
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup sdio_defines SDIO
@brief <b>Defined Constants and Types for the LPC43xx SDIO</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@author @htmlonly &copy; @endhtmlonly 2014 Jared Boone <jared@sharebrained.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2014 Jared Boone <jared@sharebrained.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_SDIO_H
#define LPC43XX_SDIO_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- SDIO registers ----------------------------------------------------- */
/* Control Register */
#define SDIO_CTRL MMIO32(SDIO_BASE + 0x000)
/* Power Enable Register */
#define SDIO_PWREN MMIO32(SDIO_BASE + 0x004)
/* Clock Divider Register */
#define SDIO_CLKDIV MMIO32(SDIO_BASE + 0x008)
/* SD Clock Source Register */
#define SDIO_CLKSRC MMIO32(SDIO_BASE + 0x00C)
/* Clock Enable Register */
#define SDIO_CLKENA MMIO32(SDIO_BASE + 0x010)
/* Time-out Register */
#define SDIO_TMOUT MMIO32(SDIO_BASE + 0x014)
/* Card Type Register */
#define SDIO_CTYPE MMIO32(SDIO_BASE + 0x018)
/* Block Size Register */
#define SDIO_BLKSIZ MMIO32(SDIO_BASE + 0x01C)
/* Byte Count Register */
#define SDIO_BYTCNT MMIO32(SDIO_BASE + 0x020)
/* Interrupt Mask Register */
#define SDIO_INTMASK MMIO32(SDIO_BASE + 0x024)
/* Command Argument Register */
#define SDIO_CMDARG MMIO32(SDIO_BASE + 0x028)
/* Command Register */
#define SDIO_CMD MMIO32(SDIO_BASE + 0x02C)
/* Response Register 0 */
#define SDIO_RESP0 MMIO32(SDIO_BASE + 0x030)
/* Response Register 1 */
#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x034)
/* Response Register 2 */
#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x038)
/* Response Register 3 */
#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x03C)
/* Masked Interrupt Status Register */
#define SDIO_MINTSTS MMIO32(SDIO_BASE + 0x040)
/* Raw Interrupt Status Register */
#define SDIO_RINTSTS MMIO32(SDIO_BASE + 0x044)
/* Status Register */
#define SDIO_STATUS MMIO32(SDIO_BASE + 0x048)
/* FIFO Threshold Watermark Register */
#define SDIO_FIFOTH MMIO32(SDIO_BASE + 0x04C)
/* Card Detect Register */
#define SDIO_CDETECT MMIO32(SDIO_BASE + 0x050)
/* Write Protect Register */
#define SDIO_WRTPRT MMIO32(SDIO_BASE + 0x054)
/* Transferred CIU Card Byte Count Register */
#define SDIO_TCBCNT MMIO32(SDIO_BASE + 0x05C)
/* Transferred Host to BIU-FIFO Byte Count Register */
#define SDIO_TBBCNT MMIO32(SDIO_BASE + 0x060)
/* Debounce Count Register */
#define SDIO_DEBNCE MMIO32(SDIO_BASE + 0x064)
/* Hardware Reset */
#define SDIO_RST_N MMIO32(SDIO_BASE + 0x078)
/* Bus Mode Register */
#define SDIO_BMOD MMIO32(SDIO_BASE + 0x080)
/* Poll Demand Register */
#define SDIO_PLDMND MMIO32(SDIO_BASE + 0x084)
/* Descriptor List Base Address Register */
#define SDIO_DBADDR MMIO32(SDIO_BASE + 0x088)
/* Internal DMAC Status Register */
#define SDIO_IDSTS MMIO32(SDIO_BASE + 0x08C)
/* Internal DMAC Interrupt Enable Register */
#define SDIO_IDINTEN MMIO32(SDIO_BASE + 0x090)
/* Current Host Descriptor Address Register */
#define SDIO_DSCADDR MMIO32(SDIO_BASE + 0x094)
/* Current Buffer Descriptor Address Register */
#define SDIO_BUFADDR MMIO32(SDIO_BASE + 0x098)
/* Data FIFO read/write */
#define SDIO_DATA MMIO32(SDIO_BASE + 0x100)
/* --- SDIO_CTRL values ----------------------------------------- */
/* CONTROLLER_RESET: Controller reset */
#define SDIO_CTRL_CONTROLLER_RESET_SHIFT (0)
#define SDIO_CTRL_CONTROLLER_RESET_MASK (0x1 << SDIO_CTRL_CONTROLLER_RESET_SHIFT)
#define SDIO_CTRL_CONTROLLER_RESET(x) ((x) << SDIO_CTRL_CONTROLLER_RESET_SHIFT)
/* FIFO_RESET: FIFO reset */
#define SDIO_CTRL_FIFO_RESET_SHIFT (1)
#define SDIO_CTRL_FIFO_RESET_MASK (0x1 << SDIO_CTRL_FIFO_RESET_SHIFT)
#define SDIO_CTRL_FIFO_RESET(x) ((x) << SDIO_CTRL_FIFO_RESET_SHIFT)
/* DMA_RESET: DMA reset */
#define SDIO_CTRL_DMA_RESET_SHIFT (2)
#define SDIO_CTRL_DMA_RESET_MASK (0x1 << SDIO_CTRL_DMA_RESET_SHIFT)
#define SDIO_CTRL_DMA_RESET(x) ((x) << SDIO_CTRL_DMA_RESET_SHIFT)
/* INT_ENABLE: Global interrupt enable/disable */
#define SDIO_CTRL_INT_ENABLE_SHIFT (4)
#define SDIO_CTRL_INT_ENABLE_MASK (0x1 << SDIO_CTRL_INT_ENABLE_SHIFT)
#define SDIO_CTRL_INT_ENABLE(x) ((x) << SDIO_CTRL_INT_ENABLE_SHIFT)
/* READ_WAIT: Read/wait send */
#define SDIO_CTRL_READ_WAIT_SHIFT (6)
#define SDIO_CTRL_READ_WAIT_MASK (0x1 << SDIO_CTRL_READ_WAIT_SHIFT)
#define SDIO_CTRL_READ_WAIT(x) ((x) << SDIO_CTRL_READ_WAIT_SHIFT)
/* SEND_IRQ_RESPONSE: Send IRQ response */
#define SDIO_CTRL_SEND_IRQ_RESPONSE_SHIFT (7)
#define SDIO_CTRL_SEND_IRQ_RESPONSE_MASK (0x1 << SDIO_CTRL_SEND_IRQ_RESPONSE_SHIFT)
#define SDIO_CTRL_SEND_IRQ_RESPONSE(x) ((x) << SDIO_CTRL_SEND_IRQ_RESPONSE_SHIFT)
/* ABORT_READ_DATA: Abort read data */
#define SDIO_CTRL_ABORT_READ_DATA_SHIFT (8)
#define SDIO_CTRL_ABORT_READ_DATA_MASK (0x1 << SDIO_CTRL_ABORT_READ_DATA_SHIFT)
#define SDIO_CTRL_ABORT_READ_DATA(x) ((x) << SDIO_CTRL_ABORT_READ_DATA_SHIFT)
/* SEND_CCSD: Send CCSD */
#define SDIO_CTRL_SEND_CCSD_SHIFT (9)
#define SDIO_CTRL_SEND_CCSD_MASK (0x1 << SDIO_CTRL_SEND_CCSD_SHIFT)
#define SDIO_CTRL_SEND_CCSD(x) ((x) << SDIO_CTRL_SEND_CCSD_SHIFT)
/* SEND_AUTO_STOP_CCSD: Send auto stop CCSD */
#define SDIO_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10)
#define SDIO_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x1 << SDIO_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)
#define SDIO_CTRL_SEND_AUTO_STOP_CCSD(x) ((x) << SDIO_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)
/* CEATA_DEVICE_INTERRUPT_STATUS: CEATA device interrupt status */
#define SDIO_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11)
#define SDIO_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x1 << SDIO_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)
#define SDIO_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) ((x) << SDIO_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)
/* CARD_VOLTAGE_A0: SD_VOLT0 pin control */
#define SDIO_CTRL_CARD_VOLTAGE_A0_SHIFT (16)
#define SDIO_CTRL_CARD_VOLTAGE_A0_MASK (0x1 << SDIO_CTRL_CARD_VOLTAGE_A0_SHIFT)
#define SDIO_CTRL_CARD_VOLTAGE_A0(x) ((x) << SDIO_CTRL_CARD_VOLTAGE_A0_SHIFT)
/* CARD_VOLTAGE_A1: SD_VOLT1 pin control */
#define SDIO_CTRL_CARD_VOLTAGE_A1_SHIFT (17)
#define SDIO_CTRL_CARD_VOLTAGE_A1_MASK (0x1 << SDIO_CTRL_CARD_VOLTAGE_A1_SHIFT)
#define SDIO_CTRL_CARD_VOLTAGE_A1(x) ((x) << SDIO_CTRL_CARD_VOLTAGE_A1_SHIFT)
/* CARD_VOLTAGE_A2: SD_VOLT2 pin control */
#define SDIO_CTRL_CARD_VOLTAGE_A2_SHIFT (18)
#define SDIO_CTRL_CARD_VOLTAGE_A2_MASK (0x1 << SDIO_CTRL_CARD_VOLTAGE_A2_SHIFT)
#define SDIO_CTRL_CARD_VOLTAGE_A2(x) ((x) << SDIO_CTRL_CARD_VOLTAGE_A2_SHIFT)
/* USE_INTERNAL_DMAC: SD/MMC DMA use */
#define SDIO_CTRL_USE_INTERNAL_DMAC_SHIFT (25)
#define SDIO_CTRL_USE_INTERNAL_DMAC_MASK (0x1 << SDIO_CTRL_USE_INTERNAL_DMAC_SHIFT)
#define SDIO_CTRL_USE_INTERNAL_DMAC(x) ((x) << SDIO_CTRL_USE_INTERNAL_DMAC_SHIFT)
/* --- SDIO_PWREN values ---------------------------------------- */
/* POWER_ENABLE: Power on/off switch for card */
#define SDIO_PWREN_POWER_ENABLE_SHIFT (0)
#define SDIO_PWREN_POWER_ENABLE_MASK (0x1 << SDIO_PWREN_POWER_ENABLE_SHIFT)
#define SDIO_PWREN_POWER_ENABLE(x) ((x) << SDIO_PWREN_POWER_ENABLE_SHIFT)
/* --- SDIO_CLKDIV values --------------------------------------- */
/* CLK_DIVIDER0: Clock divider-0 value */
#define SDIO_CLKDIV_CLK_DIVIDER0_SHIFT (0)
#define SDIO_CLKDIV_CLK_DIVIDER0_MASK (0xff << SDIO_CLKDIV_CLK_DIVIDER0_SHIFT)
#define SDIO_CLKDIV_CLK_DIVIDER0(x) ((x) << SDIO_CLKDIV_CLK_DIVIDER0_SHIFT)
/* CLK_DIVIDER1: Clock divider-1 value */
#define SDIO_CLKDIV_CLK_DIVIDER1_SHIFT (8)
#define SDIO_CLKDIV_CLK_DIVIDER1_MASK (0xff << SDIO_CLKDIV_CLK_DIVIDER1_SHIFT)
#define SDIO_CLKDIV_CLK_DIVIDER1(x) ((x) << SDIO_CLKDIV_CLK_DIVIDER1_SHIFT)
/* CLK_DIVIDER2: Clock divider-2 value */
#define SDIO_CLKDIV_CLK_DIVIDER2_SHIFT (16)
#define SDIO_CLKDIV_CLK_DIVIDER2_MASK (0xff << SDIO_CLKDIV_CLK_DIVIDER2_SHIFT)
#define SDIO_CLKDIV_CLK_DIVIDER2(x) ((x) << SDIO_CLKDIV_CLK_DIVIDER2_SHIFT)
/* CLK_DIVIDER3: Clock divider-3 value */
#define SDIO_CLKDIV_CLK_DIVIDER3_SHIFT (24)
#define SDIO_CLKDIV_CLK_DIVIDER3_MASK (0xff << SDIO_CLKDIV_CLK_DIVIDER3_SHIFT)
#define SDIO_CLKDIV_CLK_DIVIDER3(x) ((x) << SDIO_CLKDIV_CLK_DIVIDER3_SHIFT)
/* --- SDIO_CLKSRC values --------------------------------------- */
/* CLK_SOURCE: Clock divider source for SD card */
#define SDIO_CLKSRC_CLK_SOURCE_SHIFT (0)
#define SDIO_CLKSRC_CLK_SOURCE_MASK (0x3 << SDIO_CLKSRC_CLK_SOURCE_SHIFT)
#define SDIO_CLKSRC_CLK_SOURCE(x) ((x) << SDIO_CLKSRC_CLK_SOURCE_SHIFT)
/* --- SDIO_CLKENA values --------------------------------------- */
/* CCLK_ENABLE: Clock-enable control for SD card clock */
#define SDIO_CLKENA_CCLK_ENABLE_SHIFT (0)
#define SDIO_CLKENA_CCLK_ENABLE_MASK (0x1 << SDIO_CLKENA_CCLK_ENABLE_SHIFT)
#define SDIO_CLKENA_CCLK_ENABLE(x) ((x) << SDIO_CLKENA_CCLK_ENABLE_SHIFT)
/* CCLK_LOW_POWER: Low-power control for SD card clock */
#define SDIO_CLKENA_CCLK_LOW_POWER_SHIFT (16)
#define SDIO_CLKENA_CCLK_LOW_POWER_MASK (0x1 << SDIO_CLKENA_CCLK_LOW_POWER_SHIFT)
#define SDIO_CLKENA_CCLK_LOW_POWER(x) ((x) << SDIO_CLKENA_CCLK_LOW_POWER_SHIFT)
/* --- SDIO_TMOUT values ---------------------------------------- */
/* RESPONSE_TIMEOUT: Response time-out value */
#define SDIO_TMOUT_RESPONSE_TIMEOUT_SHIFT (0)
#define SDIO_TMOUT_RESPONSE_TIMEOUT_MASK (0xff << SDIO_TMOUT_RESPONSE_TIMEOUT_SHIFT)
#define SDIO_TMOUT_RESPONSE_TIMEOUT(x) ((x) << SDIO_TMOUT_RESPONSE_TIMEOUT_SHIFT)
/* DATA_TIMEOUT: Value for card data read time-out */
#define SDIO_TMOUT_DATA_TIMEOUT_SHIFT (8)
#define SDIO_TMOUT_DATA_TIMEOUT_MASK (0xffffff << SDIO_TMOUT_DATA_TIMEOUT_SHIFT)
#define SDIO_TMOUT_DATA_TIMEOUT(x) ((x) << SDIO_TMOUT_DATA_TIMEOUT_SHIFT)
/* --- SDIO_CTYPE values ---------------------------------------- */
/* CARD_WIDTH0: Indicates if card is 1-bit or 4-bit */
#define SDIO_CTYPE_CARD_WIDTH0_SHIFT (0)
#define SDIO_CTYPE_CARD_WIDTH0_MASK (0x1 << SDIO_CTYPE_CARD_WIDTH0_SHIFT)
#define SDIO_CTYPE_CARD_WIDTH0(x) ((x) << SDIO_CTYPE_CARD_WIDTH0_SHIFT)
/* CARD_WIDTH1: Indicates if card is 8-bit */
#define SDIO_CTYPE_CARD_WIDTH1_SHIFT (16)
#define SDIO_CTYPE_CARD_WIDTH1_MASK (0x1 << SDIO_CTYPE_CARD_WIDTH1_SHIFT)
#define SDIO_CTYPE_CARD_WIDTH1(x) ((x) << SDIO_CTYPE_CARD_WIDTH1_SHIFT)
/* --- SDIO_BLKSIZ values --------------------------------------- */
/* BLOCK_SIZE: Block size */
#define SDIO_BLKSIZ_BLOCK_SIZE_SHIFT (0)
#define SDIO_BLKSIZ_BLOCK_SIZE_MASK (0xffff << SDIO_BLKSIZ_BLOCK_SIZE_SHIFT)
#define SDIO_BLKSIZ_BLOCK_SIZE(x) ((x) << SDIO_BLKSIZ_BLOCK_SIZE_SHIFT)
/* --- SDIO_BYTCNT values --------------------------------------- */
/* BYTE_COUNT: Number of bytes to be transferred */
#define SDIO_BYTCNT_BYTE_COUNT_SHIFT (0)
#define SDIO_BYTCNT_BYTE_COUNT_MASK (0xffffffff << SDIO_BYTCNT_BYTE_COUNT_SHIFT)
#define SDIO_BYTCNT_BYTE_COUNT(x) ((x) << SDIO_BYTCNT_BYTE_COUNT_SHIFT)
/* --- SDIO_INTMASK values -------------------------------------- */
/* CDET: Card detect */
#define SDIO_INTMASK_CDET_SHIFT (0)
#define SDIO_INTMASK_CDET_MASK (0x1 << SDIO_INTMASK_CDET_SHIFT)
#define SDIO_INTMASK_CDET(x) ((x) << SDIO_INTMASK_CDET_SHIFT)
/* RE: Response error */
#define SDIO_INTMASK_RE_SHIFT (1)
#define SDIO_INTMASK_RE_MASK (0x1 << SDIO_INTMASK_RE_SHIFT)
#define SDIO_INTMASK_RE(x) ((x) << SDIO_INTMASK_RE_SHIFT)
/* CDONE: Command done */
#define SDIO_INTMASK_CDONE_SHIFT (2)
#define SDIO_INTMASK_CDONE_MASK (0x1 << SDIO_INTMASK_CDONE_SHIFT)
#define SDIO_INTMASK_CDONE(x) ((x) << SDIO_INTMASK_CDONE_SHIFT)
/* DTO: Data transfer over */
#define SDIO_INTMASK_DTO_SHIFT (3)
#define SDIO_INTMASK_DTO_MASK (0x1 << SDIO_INTMASK_DTO_SHIFT)
#define SDIO_INTMASK_DTO(x) ((x) << SDIO_INTMASK_DTO_SHIFT)
/* TXDR: Transmit FIFO data request */
#define SDIO_INTMASK_TXDR_SHIFT (4)
#define SDIO_INTMASK_TXDR_MASK (0x1 << SDIO_INTMASK_TXDR_SHIFT)
#define SDIO_INTMASK_TXDR(x) ((x) << SDIO_INTMASK_TXDR_SHIFT)
/* RXDR: Receive FIFO data request */
#define SDIO_INTMASK_RXDR_SHIFT (5)
#define SDIO_INTMASK_RXDR_MASK (0x1 << SDIO_INTMASK_RXDR_SHIFT)
#define SDIO_INTMASK_RXDR(x) ((x) << SDIO_INTMASK_RXDR_SHIFT)
/* RCRC: Response CRC error */
#define SDIO_INTMASK_RCRC_SHIFT (6)
#define SDIO_INTMASK_RCRC_MASK (0x1 << SDIO_INTMASK_RCRC_SHIFT)
#define SDIO_INTMASK_RCRC(x) ((x) << SDIO_INTMASK_RCRC_SHIFT)
/* DCRC: Data CRC error */
#define SDIO_INTMASK_DCRC_SHIFT (7)
#define SDIO_INTMASK_DCRC_MASK (0x1 << SDIO_INTMASK_DCRC_SHIFT)
#define SDIO_INTMASK_DCRC(x) ((x) << SDIO_INTMASK_DCRC_SHIFT)
/* RTO: Response time-out */
#define SDIO_INTMASK_RTO_SHIFT (8)
#define SDIO_INTMASK_RTO_MASK (0x1 << SDIO_INTMASK_RTO_SHIFT)
#define SDIO_INTMASK_RTO(x) ((x) << SDIO_INTMASK_RTO_SHIFT)
/* DRTO: Data read time-out */
#define SDIO_INTMASK_DRTO_SHIFT (9)
#define SDIO_INTMASK_DRTO_MASK (0x1 << SDIO_INTMASK_DRTO_SHIFT)
#define SDIO_INTMASK_DRTO(x) ((x) << SDIO_INTMASK_DRTO_SHIFT)
/* HTO: Data starvation-by-host time-out/volt_switch_int */
#define SDIO_INTMASK_HTO_SHIFT (10)
#define SDIO_INTMASK_HTO_MASK (0x1 << SDIO_INTMASK_HTO_SHIFT)
#define SDIO_INTMASK_HTO(x) ((x) << SDIO_INTMASK_HTO_SHIFT)
/* FRUN: FIFO underrun/overrun error */
#define SDIO_INTMASK_FRUN_SHIFT (11)
#define SDIO_INTMASK_FRUN_MASK (0x1 << SDIO_INTMASK_FRUN_SHIFT)
#define SDIO_INTMASK_FRUN(x) ((x) << SDIO_INTMASK_FRUN_SHIFT)
/* HLE: Hardware locked write error */
#define SDIO_INTMASK_HLE_SHIFT (12)
#define SDIO_INTMASK_HLE_MASK (0x1 << SDIO_INTMASK_HLE_SHIFT)
#define SDIO_INTMASK_HLE(x) ((x) << SDIO_INTMASK_HLE_SHIFT)
/* SBE: Start-bit error */
#define SDIO_INTMASK_SBE_SHIFT (13)
#define SDIO_INTMASK_SBE_MASK (0x1 << SDIO_INTMASK_SBE_SHIFT)
#define SDIO_INTMASK_SBE(x) ((x) << SDIO_INTMASK_SBE_SHIFT)
/* ACD: Auto command done */
#define SDIO_INTMASK_ACD_SHIFT (14)
#define SDIO_INTMASK_ACD_MASK (0x1 << SDIO_INTMASK_ACD_SHIFT)
#define SDIO_INTMASK_ACD(x) ((x) << SDIO_INTMASK_ACD_SHIFT)
/* EBE: End-bit error (read)/Write no CRC */
#define SDIO_INTMASK_EBE_SHIFT (15)
#define SDIO_INTMASK_EBE_MASK (0x1 << SDIO_INTMASK_EBE_SHIFT)
#define SDIO_INTMASK_EBE(x) ((x) << SDIO_INTMASK_EBE_SHIFT)
/* SDIO_INT_MASK: Mask SDIO interrupt */
#define SDIO_INTMASK_SDIO_INT_MASK_SHIFT (16)
#define SDIO_INTMASK_SDIO_INT_MASK_MASK (0x1 << SDIO_INTMASK_SDIO_INT_MASK_SHIFT)
#define SDIO_INTMASK_SDIO_INT_MASK(x) ((x) << SDIO_INTMASK_SDIO_INT_MASK_SHIFT)
/* --- SDIO_CMDARG values --------------------------------------- */
/* CMD_ARG: Value indicates command argument to be passed to card */
#define SDIO_CMDARG_CMD_ARG_SHIFT (0)
#define SDIO_CMDARG_CMD_ARG_MASK (0xffffffff << SDIO_CMDARG_CMD_ARG_SHIFT)
#define SDIO_CMDARG_CMD_ARG(x) ((x) << SDIO_CMDARG_CMD_ARG_SHIFT)
/* --- SDIO_CMD values ------------------------------------------ */
/* CMD_INDEX: Command index */
#define SDIO_CMD_CMD_INDEX_SHIFT (0)
#define SDIO_CMD_CMD_INDEX_MASK (0x3f << SDIO_CMD_CMD_INDEX_SHIFT)
#define SDIO_CMD_CMD_INDEX(x) ((x) << SDIO_CMD_CMD_INDEX_SHIFT)
/* RESPONSE_EXPECT: Response expect */
#define SDIO_CMD_RESPONSE_EXPECT_SHIFT (6)
#define SDIO_CMD_RESPONSE_EXPECT_MASK (0x1 << SDIO_CMD_RESPONSE_EXPECT_SHIFT)
#define SDIO_CMD_RESPONSE_EXPECT(x) ((x) << SDIO_CMD_RESPONSE_EXPECT_SHIFT)
/* RESPONSE_LENGTH: Response length */
#define SDIO_CMD_RESPONSE_LENGTH_SHIFT (7)
#define SDIO_CMD_RESPONSE_LENGTH_MASK (0x1 << SDIO_CMD_RESPONSE_LENGTH_SHIFT)
#define SDIO_CMD_RESPONSE_LENGTH(x) ((x) << SDIO_CMD_RESPONSE_LENGTH_SHIFT)
/* CHECK_RESPONSE_CRC: Check response CRC */
#define SDIO_CMD_CHECK_RESPONSE_CRC_SHIFT (8)
#define SDIO_CMD_CHECK_RESPONSE_CRC_MASK (0x1 << SDIO_CMD_CHECK_RESPONSE_CRC_SHIFT)
#define SDIO_CMD_CHECK_RESPONSE_CRC(x) ((x) << SDIO_CMD_CHECK_RESPONSE_CRC_SHIFT)
/* DATA_EXPECTED: Data expected */
#define SDIO_CMD_DATA_EXPECTED_SHIFT (9)
#define SDIO_CMD_DATA_EXPECTED_MASK (0x1 << SDIO_CMD_DATA_EXPECTED_SHIFT)
#define SDIO_CMD_DATA_EXPECTED(x) ((x) << SDIO_CMD_DATA_EXPECTED_SHIFT)
/* READ_WRITE: Read/write */
#define SDIO_CMD_READ_WRITE_SHIFT (10)
#define SDIO_CMD_READ_WRITE_MASK (0x1 << SDIO_CMD_READ_WRITE_SHIFT)
#define SDIO_CMD_READ_WRITE(x) ((x) << SDIO_CMD_READ_WRITE_SHIFT)
/* TRANSFER_MODE: Transfer mode */
#define SDIO_CMD_TRANSFER_MODE_SHIFT (11)
#define SDIO_CMD_TRANSFER_MODE_MASK (0x1 << SDIO_CMD_TRANSFER_MODE_SHIFT)
#define SDIO_CMD_TRANSFER_MODE(x) ((x) << SDIO_CMD_TRANSFER_MODE_SHIFT)
/* SEND_AUTO_STOP: Send auto stop */
#define SDIO_CMD_SEND_AUTO_STOP_SHIFT (12)
#define SDIO_CMD_SEND_AUTO_STOP_MASK (0x1 << SDIO_CMD_SEND_AUTO_STOP_SHIFT)
#define SDIO_CMD_SEND_AUTO_STOP(x) ((x) << SDIO_CMD_SEND_AUTO_STOP_SHIFT)
/* WAIT_PRVDATA_COMPLETE: Wait prvdata complete */
#define SDIO_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13)
#define SDIO_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x1 << SDIO_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)
#define SDIO_CMD_WAIT_PRVDATA_COMPLETE(x) ((x) << SDIO_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)
/* STOP_ABORT_CMD: Stop abort command */
#define SDIO_CMD_STOP_ABORT_CMD_SHIFT (14)
#define SDIO_CMD_STOP_ABORT_CMD_MASK (0x1 << SDIO_CMD_STOP_ABORT_CMD_SHIFT)
#define SDIO_CMD_STOP_ABORT_CMD(x) ((x) << SDIO_CMD_STOP_ABORT_CMD_SHIFT)
/* SEND_INITIALIZATION: Send initialization */
#define SDIO_CMD_SEND_INITIALIZATION_SHIFT (15)
#define SDIO_CMD_SEND_INITIALIZATION_MASK (0x1 << SDIO_CMD_SEND_INITIALIZATION_SHIFT)
#define SDIO_CMD_SEND_INITIALIZATION(x) ((x) << SDIO_CMD_SEND_INITIALIZATION_SHIFT)
/* UPDATE_CLOCK_REGISTERS_ONLY: Update clock registers only */
#define SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21)
#define SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x1 << SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)
#define SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) ((x) << SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)
/* READ_CEATA_DEVICE: Read CEATA device */
#define SDIO_CMD_READ_CEATA_DEVICE_SHIFT (22)
#define SDIO_CMD_READ_CEATA_DEVICE_MASK (0x1 << SDIO_CMD_READ_CEATA_DEVICE_SHIFT)
#define SDIO_CMD_READ_CEATA_DEVICE(x) ((x) << SDIO_CMD_READ_CEATA_DEVICE_SHIFT)
/* CCS_EXPECTED: CCS expected */
#define SDIO_CMD_CCS_EXPECTED_SHIFT (23)
#define SDIO_CMD_CCS_EXPECTED_MASK (0x1 << SDIO_CMD_CCS_EXPECTED_SHIFT)
#define SDIO_CMD_CCS_EXPECTED(x) ((x) << SDIO_CMD_CCS_EXPECTED_SHIFT)
/* ENABLE_BOOT: Enable boot */
#define SDIO_CMD_ENABLE_BOOT_SHIFT (24)
#define SDIO_CMD_ENABLE_BOOT_MASK (0x1 << SDIO_CMD_ENABLE_BOOT_SHIFT)
#define SDIO_CMD_ENABLE_BOOT(x) ((x) << SDIO_CMD_ENABLE_BOOT_SHIFT)
/* EXPECT_BOOT_ACK: Expect boot acknowledge */
#define SDIO_CMD_EXPECT_BOOT_ACK_SHIFT (25)
#define SDIO_CMD_EXPECT_BOOT_ACK_MASK (0x1 << SDIO_CMD_EXPECT_BOOT_ACK_SHIFT)
#define SDIO_CMD_EXPECT_BOOT_ACK(x) ((x) << SDIO_CMD_EXPECT_BOOT_ACK_SHIFT)
/* DISABLE_BOOT: Disable boot */
#define SDIO_CMD_DISABLE_BOOT_SHIFT (26)
#define SDIO_CMD_DISABLE_BOOT_MASK (0x1 << SDIO_CMD_DISABLE_BOOT_SHIFT)
#define SDIO_CMD_DISABLE_BOOT(x) ((x) << SDIO_CMD_DISABLE_BOOT_SHIFT)
/* BOOT_MODE: Boot mode */
#define SDIO_CMD_BOOT_MODE_SHIFT (27)
#define SDIO_CMD_BOOT_MODE_MASK (0x1 << SDIO_CMD_BOOT_MODE_SHIFT)
#define SDIO_CMD_BOOT_MODE(x) ((x) << SDIO_CMD_BOOT_MODE_SHIFT)
/* VOLT_SWITCH: Voltage switch bit */
#define SDIO_CMD_VOLT_SWITCH_SHIFT (28)
#define SDIO_CMD_VOLT_SWITCH_MASK (0x1 << SDIO_CMD_VOLT_SWITCH_SHIFT)
#define SDIO_CMD_VOLT_SWITCH(x) ((x) << SDIO_CMD_VOLT_SWITCH_SHIFT)
/* START_CMD: Start command */
#define SDIO_CMD_START_CMD_SHIFT (31)
#define SDIO_CMD_START_CMD_MASK (0x1 << SDIO_CMD_START_CMD_SHIFT)
#define SDIO_CMD_START_CMD(x) ((x) << SDIO_CMD_START_CMD_SHIFT)
/* --- SDIO_RESP0 values ---------------------------------------- */
/* RESPONSE0: Bit[31:0] of response */
#define SDIO_RESP0_RESPONSE0_SHIFT (0)
#define SDIO_RESP0_RESPONSE0_MASK (0xffffffff << SDIO_RESP0_RESPONSE0_SHIFT)
#define SDIO_RESP0_RESPONSE0(x) ((x) << SDIO_RESP0_RESPONSE0_SHIFT)
/* --- SDIO_RESP1 values ---------------------------------------- */
/* RESPONSE1: Bit[63:32] of long response */
#define SDIO_RESP1_RESPONSE1_SHIFT (0)
#define SDIO_RESP1_RESPONSE1_MASK (0xffffffff << SDIO_RESP1_RESPONSE1_SHIFT)
#define SDIO_RESP1_RESPONSE1(x) ((x) << SDIO_RESP1_RESPONSE1_SHIFT)
/* --- SDIO_RESP2 values ---------------------------------------- */
/* RESPONSE2: Bit[95:64] of long response */
#define SDIO_RESP2_RESPONSE2_SHIFT (0)
#define SDIO_RESP2_RESPONSE2_MASK (0xffffffff << SDIO_RESP2_RESPONSE2_SHIFT)
#define SDIO_RESP2_RESPONSE2(x) ((x) << SDIO_RESP2_RESPONSE2_SHIFT)
/* --- SDIO_RESP3 values ---------------------------------------- */
/* RESPONSE3: Bit[127:96] of long response */
#define SDIO_RESP3_RESPONSE3_SHIFT (0)
#define SDIO_RESP3_RESPONSE3_MASK (0xffffffff << SDIO_RESP3_RESPONSE3_SHIFT)
#define SDIO_RESP3_RESPONSE3(x) ((x) << SDIO_RESP3_RESPONSE3_SHIFT)
/* --- SDIO_MINTSTS values -------------------------------------- */
/* CDET: Card detect */
#define SDIO_MINTSTS_CDET_SHIFT (0)
#define SDIO_MINTSTS_CDET_MASK (0x1 << SDIO_MINTSTS_CDET_SHIFT)
#define SDIO_MINTSTS_CDET(x) ((x) << SDIO_MINTSTS_CDET_SHIFT)
/* RE: Response error */
#define SDIO_MINTSTS_RE_SHIFT (1)
#define SDIO_MINTSTS_RE_MASK (0x1 << SDIO_MINTSTS_RE_SHIFT)
#define SDIO_MINTSTS_RE(x) ((x) << SDIO_MINTSTS_RE_SHIFT)
/* CDONE: Command done */
#define SDIO_MINTSTS_CDONE_SHIFT (2)
#define SDIO_MINTSTS_CDONE_MASK (0x1 << SDIO_MINTSTS_CDONE_SHIFT)
#define SDIO_MINTSTS_CDONE(x) ((x) << SDIO_MINTSTS_CDONE_SHIFT)
/* DTO: Data transfer over */
#define SDIO_MINTSTS_DTO_SHIFT (3)
#define SDIO_MINTSTS_DTO_MASK (0x1 << SDIO_MINTSTS_DTO_SHIFT)
#define SDIO_MINTSTS_DTO(x) ((x) << SDIO_MINTSTS_DTO_SHIFT)
/* TXDR: Transmit FIFO data request */
#define SDIO_MINTSTS_TXDR_SHIFT (4)
#define SDIO_MINTSTS_TXDR_MASK (0x1 << SDIO_MINTSTS_TXDR_SHIFT)
#define SDIO_MINTSTS_TXDR(x) ((x) << SDIO_MINTSTS_TXDR_SHIFT)
/* RXDR: Receive FIFO data request */
#define SDIO_MINTSTS_RXDR_SHIFT (5)
#define SDIO_MINTSTS_RXDR_MASK (0x1 << SDIO_MINTSTS_RXDR_SHIFT)
#define SDIO_MINTSTS_RXDR(x) ((x) << SDIO_MINTSTS_RXDR_SHIFT)
/* RCRC: Response CRC error */
#define SDIO_MINTSTS_RCRC_SHIFT (6)
#define SDIO_MINTSTS_RCRC_MASK (0x1 << SDIO_MINTSTS_RCRC_SHIFT)
#define SDIO_MINTSTS_RCRC(x) ((x) << SDIO_MINTSTS_RCRC_SHIFT)
/* DCRC: Data CRC error */
#define SDIO_MINTSTS_DCRC_SHIFT (7)
#define SDIO_MINTSTS_DCRC_MASK (0x1 << SDIO_MINTSTS_DCRC_SHIFT)
#define SDIO_MINTSTS_DCRC(x) ((x) << SDIO_MINTSTS_DCRC_SHIFT)
/* RTO: Response time-out */
#define SDIO_MINTSTS_RTO_SHIFT (8)
#define SDIO_MINTSTS_RTO_MASK (0x1 << SDIO_MINTSTS_RTO_SHIFT)
#define SDIO_MINTSTS_RTO(x) ((x) << SDIO_MINTSTS_RTO_SHIFT)
/* DRTO: Data read time-out */
#define SDIO_MINTSTS_DRTO_SHIFT (9)
#define SDIO_MINTSTS_DRTO_MASK (0x1 << SDIO_MINTSTS_DRTO_SHIFT)
#define SDIO_MINTSTS_DRTO(x) ((x) << SDIO_MINTSTS_DRTO_SHIFT)
/* HTO: Data starvation-by-host time-out */
#define SDIO_MINTSTS_HTO_SHIFT (10)
#define SDIO_MINTSTS_HTO_MASK (0x1 << SDIO_MINTSTS_HTO_SHIFT)
#define SDIO_MINTSTS_HTO(x) ((x) << SDIO_MINTSTS_HTO_SHIFT)
/* FRUN: FIFO underrun/overrun error */
#define SDIO_MINTSTS_FRUN_SHIFT (11)
#define SDIO_MINTSTS_FRUN_MASK (0x1 << SDIO_MINTSTS_FRUN_SHIFT)
#define SDIO_MINTSTS_FRUN(x) ((x) << SDIO_MINTSTS_FRUN_SHIFT)
/* HLE: Hardware locked write error */
#define SDIO_MINTSTS_HLE_SHIFT (12)
#define SDIO_MINTSTS_HLE_MASK (0x1 << SDIO_MINTSTS_HLE_SHIFT)
#define SDIO_MINTSTS_HLE(x) ((x) << SDIO_MINTSTS_HLE_SHIFT)
/* SBE: Start-bit error */
#define SDIO_MINTSTS_SBE_SHIFT (13)
#define SDIO_MINTSTS_SBE_MASK (0x1 << SDIO_MINTSTS_SBE_SHIFT)
#define SDIO_MINTSTS_SBE(x) ((x) << SDIO_MINTSTS_SBE_SHIFT)
/* ACD: Auto command done */
#define SDIO_MINTSTS_ACD_SHIFT (14)
#define SDIO_MINTSTS_ACD_MASK (0x1 << SDIO_MINTSTS_ACD_SHIFT)
#define SDIO_MINTSTS_ACD(x) ((x) << SDIO_MINTSTS_ACD_SHIFT)
/* EBE: End-bit error (read)/write no CRC */
#define SDIO_MINTSTS_EBE_SHIFT (15)
#define SDIO_MINTSTS_EBE_MASK (0x1 << SDIO_MINTSTS_EBE_SHIFT)
#define SDIO_MINTSTS_EBE(x) ((x) << SDIO_MINTSTS_EBE_SHIFT)
/* SDIO_INTERRUPT: Interrupt from SDIO card */
#define SDIO_MINTSTS_SDIO_INTERRUPT_SHIFT (16)
#define SDIO_MINTSTS_SDIO_INTERRUPT_MASK (0x1 << SDIO_MINTSTS_SDIO_INTERRUPT_SHIFT)
#define SDIO_MINTSTS_SDIO_INTERRUPT(x) ((x) << SDIO_MINTSTS_SDIO_INTERRUPT_SHIFT)
/* --- SDIO_RINTSTS values -------------------------------------- */
/* CDET: Card detect */
#define SDIO_RINTSTS_CDET_SHIFT (0)
#define SDIO_RINTSTS_CDET_MASK (0x1 << SDIO_RINTSTS_CDET_SHIFT)
#define SDIO_RINTSTS_CDET(x) ((x) << SDIO_RINTSTS_CDET_SHIFT)
/* RE: Response error */
#define SDIO_RINTSTS_RE_SHIFT (1)
#define SDIO_RINTSTS_RE_MASK (0x1 << SDIO_RINTSTS_RE_SHIFT)
#define SDIO_RINTSTS_RE(x) ((x) << SDIO_RINTSTS_RE_SHIFT)
/* CDONE: Command done */
#define SDIO_RINTSTS_CDONE_SHIFT (2)
#define SDIO_RINTSTS_CDONE_MASK (0x1 << SDIO_RINTSTS_CDONE_SHIFT)
#define SDIO_RINTSTS_CDONE(x) ((x) << SDIO_RINTSTS_CDONE_SHIFT)
/* DTO: Data transfer over */
#define SDIO_RINTSTS_DTO_SHIFT (3)
#define SDIO_RINTSTS_DTO_MASK (0x1 << SDIO_RINTSTS_DTO_SHIFT)
#define SDIO_RINTSTS_DTO(x) ((x) << SDIO_RINTSTS_DTO_SHIFT)
/* TXDR: Transmit FIFO data request */
#define SDIO_RINTSTS_TXDR_SHIFT (4)
#define SDIO_RINTSTS_TXDR_MASK (0x1 << SDIO_RINTSTS_TXDR_SHIFT)
#define SDIO_RINTSTS_TXDR(x) ((x) << SDIO_RINTSTS_TXDR_SHIFT)
/* RXDR: Receive FIFO data request */
#define SDIO_RINTSTS_RXDR_SHIFT (5)
#define SDIO_RINTSTS_RXDR_MASK (0x1 << SDIO_RINTSTS_RXDR_SHIFT)
#define SDIO_RINTSTS_RXDR(x) ((x) << SDIO_RINTSTS_RXDR_SHIFT)
/* RCRC: Response CRC error */
#define SDIO_RINTSTS_RCRC_SHIFT (6)
#define SDIO_RINTSTS_RCRC_MASK (0x1 << SDIO_RINTSTS_RCRC_SHIFT)
#define SDIO_RINTSTS_RCRC(x) ((x) << SDIO_RINTSTS_RCRC_SHIFT)
/* DCRC: Data CRC error */
#define SDIO_RINTSTS_DCRC_SHIFT (7)
#define SDIO_RINTSTS_DCRC_MASK (0x1 << SDIO_RINTSTS_DCRC_SHIFT)
#define SDIO_RINTSTS_DCRC(x) ((x) << SDIO_RINTSTS_DCRC_SHIFT)
/* RTO_BAR: Response time-out (RTO)/boot ack received (BAR) */
#define SDIO_RINTSTS_RTO_BAR_SHIFT (8)
#define SDIO_RINTSTS_RTO_BAR_MASK (0x1 << SDIO_RINTSTS_RTO_BAR_SHIFT)
#define SDIO_RINTSTS_RTO_BAR(x) ((x) << SDIO_RINTSTS_RTO_BAR_SHIFT)
/* DRTO_BDS: Data read time-out (DRTO)/boot data start (BDS) */
#define SDIO_RINTSTS_DRTO_BDS_SHIFT (9)
#define SDIO_RINTSTS_DRTO_BDS_MASK (0x1 << SDIO_RINTSTS_DRTO_BDS_SHIFT)
#define SDIO_RINTSTS_DRTO_BDS(x) ((x) << SDIO_RINTSTS_DRTO_BDS_SHIFT)
/* HTO: Data starvation-by-host time-out */
#define SDIO_RINTSTS_HTO_SHIFT (10)
#define SDIO_RINTSTS_HTO_MASK (0x1 << SDIO_RINTSTS_HTO_SHIFT)
#define SDIO_RINTSTS_HTO(x) ((x) << SDIO_RINTSTS_HTO_SHIFT)
/* FRUN: FIFO underrun/overrun error */
#define SDIO_RINTSTS_FRUN_SHIFT (11)
#define SDIO_RINTSTS_FRUN_MASK (0x1 << SDIO_RINTSTS_FRUN_SHIFT)
#define SDIO_RINTSTS_FRUN(x) ((x) << SDIO_RINTSTS_FRUN_SHIFT)
/* HLE: Hardware locked write error */
#define SDIO_RINTSTS_HLE_SHIFT (12)
#define SDIO_RINTSTS_HLE_MASK (0x1 << SDIO_RINTSTS_HLE_SHIFT)
#define SDIO_RINTSTS_HLE(x) ((x) << SDIO_RINTSTS_HLE_SHIFT)
/* SBE: Start-bit error */
#define SDIO_RINTSTS_SBE_SHIFT (13)
#define SDIO_RINTSTS_SBE_MASK (0x1 << SDIO_RINTSTS_SBE_SHIFT)
#define SDIO_RINTSTS_SBE(x) ((x) << SDIO_RINTSTS_SBE_SHIFT)
/* ACD: Auto command done */
#define SDIO_RINTSTS_ACD_SHIFT (14)
#define SDIO_RINTSTS_ACD_MASK (0x1 << SDIO_RINTSTS_ACD_SHIFT)
#define SDIO_RINTSTS_ACD(x) ((x) << SDIO_RINTSTS_ACD_SHIFT)
/* EBE: End-bit error (read)/write no CRC */
#define SDIO_RINTSTS_EBE_SHIFT (15)
#define SDIO_RINTSTS_EBE_MASK (0x1 << SDIO_RINTSTS_EBE_SHIFT)
#define SDIO_RINTSTS_EBE(x) ((x) << SDIO_RINTSTS_EBE_SHIFT)
/* SDIO_INTERRUPT: Interrupt from SDIO card */
#define SDIO_RINTSTS_SDIO_INTERRUPT_SHIFT (16)
#define SDIO_RINTSTS_SDIO_INTERRUPT_MASK (0x1 << SDIO_RINTSTS_SDIO_INTERRUPT_SHIFT)
#define SDIO_RINTSTS_SDIO_INTERRUPT(x) ((x) << SDIO_RINTSTS_SDIO_INTERRUPT_SHIFT)
/* --- SDIO_STATUS values --------------------------------------- */
/* FIFO_RX_WATERMARK: FIFO reached receive watermark level */
#define SDIO_STATUS_FIFO_RX_WATERMARK_SHIFT (0)
#define SDIO_STATUS_FIFO_RX_WATERMARK_MASK (0x1 << SDIO_STATUS_FIFO_RX_WATERMARK_SHIFT)
#define SDIO_STATUS_FIFO_RX_WATERMARK(x) ((x) << SDIO_STATUS_FIFO_RX_WATERMARK_SHIFT)
/* FIFO_TX_WATERMARK: FIFO reached transmit watermark level */
#define SDIO_STATUS_FIFO_TX_WATERMARK_SHIFT (1)
#define SDIO_STATUS_FIFO_TX_WATERMARK_MASK (0x1 << SDIO_STATUS_FIFO_TX_WATERMARK_SHIFT)
#define SDIO_STATUS_FIFO_TX_WATERMARK(x) ((x) << SDIO_STATUS_FIFO_TX_WATERMARK_SHIFT)
/* FIFO_EMPTY: FIFO is empty */
#define SDIO_STATUS_FIFO_EMPTY_SHIFT (2)
#define SDIO_STATUS_FIFO_EMPTY_MASK (0x1 << SDIO_STATUS_FIFO_EMPTY_SHIFT)
#define SDIO_STATUS_FIFO_EMPTY(x) ((x) << SDIO_STATUS_FIFO_EMPTY_SHIFT)
/* FIFO_FULL: FIFO is full */
#define SDIO_STATUS_FIFO_FULL_SHIFT (3)
#define SDIO_STATUS_FIFO_FULL_MASK (0x1 << SDIO_STATUS_FIFO_FULL_SHIFT)
#define SDIO_STATUS_FIFO_FULL(x) ((x) << SDIO_STATUS_FIFO_FULL_SHIFT)
/* CMDFSMSTATES: Command FSM states */
#define SDIO_STATUS_CMDFSMSTATES_SHIFT (4)
#define SDIO_STATUS_CMDFSMSTATES_MASK (0xf << SDIO_STATUS_CMDFSMSTATES_SHIFT)
#define SDIO_STATUS_CMDFSMSTATES(x) ((x) << SDIO_STATUS_CMDFSMSTATES_SHIFT)
/* DATA_3_STATUS: Raw selected card_data[3] */
#define SDIO_STATUS_DATA_3_STATUS_SHIFT (8)
#define SDIO_STATUS_DATA_3_STATUS_MASK (0x1 << SDIO_STATUS_DATA_3_STATUS_SHIFT)
#define SDIO_STATUS_DATA_3_STATUS(x) ((x) << SDIO_STATUS_DATA_3_STATUS_SHIFT)
/* DATA_BUSY: Inverted version of raw selected card_data[0] */
#define SDIO_STATUS_DATA_BUSY_SHIFT (9)
#define SDIO_STATUS_DATA_BUSY_MASK (0x1 << SDIO_STATUS_DATA_BUSY_SHIFT)
#define SDIO_STATUS_DATA_BUSY(x) ((x) << SDIO_STATUS_DATA_BUSY_SHIFT)
/* DATA_STATE_MC_BUSY: Data transmit or receive state-machine is busy */
#define SDIO_STATUS_DATA_STATE_MC_BUSY_SHIFT (10)
#define SDIO_STATUS_DATA_STATE_MC_BUSY_MASK (0x1 << SDIO_STATUS_DATA_STATE_MC_BUSY_SHIFT)
#define SDIO_STATUS_DATA_STATE_MC_BUSY(x) ((x) << SDIO_STATUS_DATA_STATE_MC_BUSY_SHIFT)
/* RESPONSE_INDEX: Index of previous response */
#define SDIO_STATUS_RESPONSE_INDEX_SHIFT (11)
#define SDIO_STATUS_RESPONSE_INDEX_MASK (0x3f << SDIO_STATUS_RESPONSE_INDEX_SHIFT)
#define SDIO_STATUS_RESPONSE_INDEX(x) ((x) << SDIO_STATUS_RESPONSE_INDEX_SHIFT)
/* FIFO_COUNT: Number of filled locations in FIFO */
#define SDIO_STATUS_FIFO_COUNT_SHIFT (17)
#define SDIO_STATUS_FIFO_COUNT_MASK (0x1fff << SDIO_STATUS_FIFO_COUNT_SHIFT)
#define SDIO_STATUS_FIFO_COUNT(x) ((x) << SDIO_STATUS_FIFO_COUNT_SHIFT)
/* DMA_ACK: DMA acknowledge signal */
#define SDIO_STATUS_DMA_ACK_SHIFT (30)
#define SDIO_STATUS_DMA_ACK_MASK (0x1 << SDIO_STATUS_DMA_ACK_SHIFT)
#define SDIO_STATUS_DMA_ACK(x) ((x) << SDIO_STATUS_DMA_ACK_SHIFT)
/* DMA_REQ: DMA request signal */
#define SDIO_STATUS_DMA_REQ_SHIFT (31)
#define SDIO_STATUS_DMA_REQ_MASK (0x1 << SDIO_STATUS_DMA_REQ_SHIFT)
#define SDIO_STATUS_DMA_REQ(x) ((x) << SDIO_STATUS_DMA_REQ_SHIFT)
/* --- SDIO_FIFOTH values --------------------------------------- */
/* TX_WMARK: FIFO threshold watermark level when transmitting data to card */
#define SDIO_FIFOTH_TX_WMARK_SHIFT (0)
#define SDIO_FIFOTH_TX_WMARK_MASK (0xfff << SDIO_FIFOTH_TX_WMARK_SHIFT)
#define SDIO_FIFOTH_TX_WMARK(x) ((x) << SDIO_FIFOTH_TX_WMARK_SHIFT)
/* RX_WMARK: FIFO threshold watermark level when receiving data from card */
#define SDIO_FIFOTH_RX_WMARK_SHIFT (16)
#define SDIO_FIFOTH_RX_WMARK_MASK (0xfff << SDIO_FIFOTH_RX_WMARK_SHIFT)
#define SDIO_FIFOTH_RX_WMARK(x) ((x) << SDIO_FIFOTH_RX_WMARK_SHIFT)
/* DMA_MTS: Burst size of multiple transaction */
#define SDIO_FIFOTH_DMA_MTS_SHIFT (28)
#define SDIO_FIFOTH_DMA_MTS_MASK (0x7 << SDIO_FIFOTH_DMA_MTS_SHIFT)
#define SDIO_FIFOTH_DMA_MTS(x) ((x) << SDIO_FIFOTH_DMA_MTS_SHIFT)
/* --- SDIO_CDETECT values -------------------------------------- */
/* CARD_DETECT: Card detect - 0 represents presence of card */
#define SDIO_CDETECT_CARD_DETECT_SHIFT (0)
#define SDIO_CDETECT_CARD_DETECT_MASK (0x1 << SDIO_CDETECT_CARD_DETECT_SHIFT)
#define SDIO_CDETECT_CARD_DETECT(x) ((x) << SDIO_CDETECT_CARD_DETECT_SHIFT)
/* --- SDIO_WRTPRT values --------------------------------------- */
/* WRITE_PROTECT: Write protect - 1 represents write protection */
#define SDIO_WRTPRT_WRITE_PROTECT_SHIFT (0)
#define SDIO_WRTPRT_WRITE_PROTECT_MASK (0x1 << SDIO_WRTPRT_WRITE_PROTECT_SHIFT)
#define SDIO_WRTPRT_WRITE_PROTECT(x) ((x) << SDIO_WRTPRT_WRITE_PROTECT_SHIFT)
/* --- SDIO_TCBCNT values --------------------------------------- */
/* TRANS_CARD_BYTE_COUNT: Number of bytes transferred by CIU unit to card */
#define SDIO_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0)
#define SDIO_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xffffffff << SDIO_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)
#define SDIO_TCBCNT_TRANS_CARD_BYTE_COUNT(x) ((x) << SDIO_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)
/* --- SDIO_TBBCNT values --------------------------------------- */
/* TRANS_FIFO_BYTE_COUNT: Number of bytes transferred between host/DMA memory and BIU FIFO */
#define SDIO_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0)
#define SDIO_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xffffffff << SDIO_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)
#define SDIO_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) ((x) << SDIO_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)
/* --- SDIO_DEBNCE values --------------------------------------- */
/* DEBOUNCE_COUNT: Number of host clocks used by debounce filter logic for card detect */
#define SDIO_DEBNCE_DEBOUNCE_COUNT_SHIFT (0)
#define SDIO_DEBNCE_DEBOUNCE_COUNT_MASK (0xffffff << SDIO_DEBNCE_DEBOUNCE_COUNT_SHIFT)
#define SDIO_DEBNCE_DEBOUNCE_COUNT(x) ((x) << SDIO_DEBNCE_DEBOUNCE_COUNT_SHIFT)
/* --- SDIO_RST_N values ---------------------------------------- */
/* CARD_RESET: Hardware reset */
#define SDIO_RST_N_CARD_RESET_SHIFT (0)
#define SDIO_RST_N_CARD_RESET_MASK (0x1 << SDIO_RST_N_CARD_RESET_SHIFT)
#define SDIO_RST_N_CARD_RESET(x) ((x) << SDIO_RST_N_CARD_RESET_SHIFT)
/* --- SDIO_BMOD values ----------------------------------------- */
/* SWR: Software reset */
#define SDIO_BMOD_SWR_SHIFT (0)
#define SDIO_BMOD_SWR_MASK (0x1 << SDIO_BMOD_SWR_SHIFT)
#define SDIO_BMOD_SWR(x) ((x) << SDIO_BMOD_SWR_SHIFT)
/* FB: Fixed burst */
#define SDIO_BMOD_FB_SHIFT (1)
#define SDIO_BMOD_FB_MASK (0x1 << SDIO_BMOD_FB_SHIFT)
#define SDIO_BMOD_FB(x) ((x) << SDIO_BMOD_FB_SHIFT)
/* DSL: Descriptor skip length */
#define SDIO_BMOD_DSL_SHIFT (2)
#define SDIO_BMOD_DSL_MASK (0x1f << SDIO_BMOD_DSL_SHIFT)
#define SDIO_BMOD_DSL(x) ((x) << SDIO_BMOD_DSL_SHIFT)
/* DE: SD/MMC DMA enable */
#define SDIO_BMOD_DE_SHIFT (7)
#define SDIO_BMOD_DE_MASK (0x1 << SDIO_BMOD_DE_SHIFT)
#define SDIO_BMOD_DE(x) ((x) << SDIO_BMOD_DE_SHIFT)
/* PBL: Programmable burst length */
#define SDIO_BMOD_PBL_SHIFT (8)
#define SDIO_BMOD_PBL_MASK (0x7 << SDIO_BMOD_PBL_SHIFT)
#define SDIO_BMOD_PBL(x) ((x) << SDIO_BMOD_PBL_SHIFT)
/* --- SDIO_PLDMND values --------------------------------------- */
/* PD: Poll demand */
#define SDIO_PLDMND_PD_SHIFT (0)
#define SDIO_PLDMND_PD_MASK (0xffffffff << SDIO_PLDMND_PD_SHIFT)
#define SDIO_PLDMND_PD(x) ((x) << SDIO_PLDMND_PD_SHIFT)
/* --- SDIO_DBADDR values --------------------------------------- */
/* SDL: Start of descriptor list */
#define SDIO_DBADDR_SDL_SHIFT (0)
#define SDIO_DBADDR_SDL_MASK (0xffffffff << SDIO_DBADDR_SDL_SHIFT)
#define SDIO_DBADDR_SDL(x) ((x) << SDIO_DBADDR_SDL_SHIFT)
/* --- SDIO_IDSTS values ---------------------------------------- */
/* TI: Transmit interrupt */
#define SDIO_IDSTS_TI_SHIFT (0)
#define SDIO_IDSTS_TI_MASK (0x1 << SDIO_IDSTS_TI_SHIFT)
#define SDIO_IDSTS_TI(x) ((x) << SDIO_IDSTS_TI_SHIFT)
/* RI: Receive interrupt */
#define SDIO_IDSTS_RI_SHIFT (1)
#define SDIO_IDSTS_RI_MASK (0x1 << SDIO_IDSTS_RI_SHIFT)
#define SDIO_IDSTS_RI(x) ((x) << SDIO_IDSTS_RI_SHIFT)
/* FBE: Fatal bus error interrupt */
#define SDIO_IDSTS_FBE_SHIFT (2)
#define SDIO_IDSTS_FBE_MASK (0x1 << SDIO_IDSTS_FBE_SHIFT)
#define SDIO_IDSTS_FBE(x) ((x) << SDIO_IDSTS_FBE_SHIFT)
/* DU: Descriptor unavailable interrupt */
#define SDIO_IDSTS_DU_SHIFT (4)
#define SDIO_IDSTS_DU_MASK (0x1 << SDIO_IDSTS_DU_SHIFT)
#define SDIO_IDSTS_DU(x) ((x) << SDIO_IDSTS_DU_SHIFT)
/* CES: Card error summary */
#define SDIO_IDSTS_CES_SHIFT (5)
#define SDIO_IDSTS_CES_MASK (0x1 << SDIO_IDSTS_CES_SHIFT)
#define SDIO_IDSTS_CES(x) ((x) << SDIO_IDSTS_CES_SHIFT)
/* NIS: Normal interrupt summary */
#define SDIO_IDSTS_NIS_SHIFT (8)
#define SDIO_IDSTS_NIS_MASK (0x1 << SDIO_IDSTS_NIS_SHIFT)
#define SDIO_IDSTS_NIS(x) ((x) << SDIO_IDSTS_NIS_SHIFT)
/* AIS: Abnormal interrupt summary */
#define SDIO_IDSTS_AIS_SHIFT (9)
#define SDIO_IDSTS_AIS_MASK (0x1 << SDIO_IDSTS_AIS_SHIFT)
#define SDIO_IDSTS_AIS(x) ((x) << SDIO_IDSTS_AIS_SHIFT)
/* EB: Error bits */
#define SDIO_IDSTS_EB_SHIFT (10)
#define SDIO_IDSTS_EB_MASK (0x7 << SDIO_IDSTS_EB_SHIFT)
#define SDIO_IDSTS_EB(x) ((x) << SDIO_IDSTS_EB_SHIFT)
/* FSM: DMAC state machine present state */
#define SDIO_IDSTS_FSM_SHIFT (13)
#define SDIO_IDSTS_FSM_MASK (0xf << SDIO_IDSTS_FSM_SHIFT)
#define SDIO_IDSTS_FSM(x) ((x) << SDIO_IDSTS_FSM_SHIFT)
/* --- SDIO_IDINTEN values -------------------------------------- */
/* TI: Transmit interrupt enable */
#define SDIO_IDINTEN_TI_SHIFT (0)
#define SDIO_IDINTEN_TI_MASK (0x1 << SDIO_IDINTEN_TI_SHIFT)
#define SDIO_IDINTEN_TI(x) ((x) << SDIO_IDINTEN_TI_SHIFT)
/* RI: Receive interrupt enable */
#define SDIO_IDINTEN_RI_SHIFT (1)
#define SDIO_IDINTEN_RI_MASK (0x1 << SDIO_IDINTEN_RI_SHIFT)
#define SDIO_IDINTEN_RI(x) ((x) << SDIO_IDINTEN_RI_SHIFT)
/* FBE: Fatal bus error enable */
#define SDIO_IDINTEN_FBE_SHIFT (2)
#define SDIO_IDINTEN_FBE_MASK (0x1 << SDIO_IDINTEN_FBE_SHIFT)
#define SDIO_IDINTEN_FBE(x) ((x) << SDIO_IDINTEN_FBE_SHIFT)
/* DU: Descriptor unavailable interrupt */
#define SDIO_IDINTEN_DU_SHIFT (4)
#define SDIO_IDINTEN_DU_MASK (0x1 << SDIO_IDINTEN_DU_SHIFT)
#define SDIO_IDINTEN_DU(x) ((x) << SDIO_IDINTEN_DU_SHIFT)
/* CES: Card error summary interrupt */
#define SDIO_IDINTEN_CES_SHIFT (5)
#define SDIO_IDINTEN_CES_MASK (0x1 << SDIO_IDINTEN_CES_SHIFT)
#define SDIO_IDINTEN_CES(x) ((x) << SDIO_IDINTEN_CES_SHIFT)
/* NIS: Normal interrupt summary enable */
#define SDIO_IDINTEN_NIS_SHIFT (8)
#define SDIO_IDINTEN_NIS_MASK (0x1 << SDIO_IDINTEN_NIS_SHIFT)
#define SDIO_IDINTEN_NIS(x) ((x) << SDIO_IDINTEN_NIS_SHIFT)
/* AIS: Abnormal interrupt summary enable */
#define SDIO_IDINTEN_AIS_SHIFT (9)
#define SDIO_IDINTEN_AIS_MASK (0x1 << SDIO_IDINTEN_AIS_SHIFT)
#define SDIO_IDINTEN_AIS(x) ((x) << SDIO_IDINTEN_AIS_SHIFT)
/* --- SDIO_DSCADDR values -------------------------------------- */
/* HDA: Host descriptor address pointer */
#define SDIO_DSCADDR_HDA_SHIFT (0)
#define SDIO_DSCADDR_HDA_MASK (0xffffffff << SDIO_DSCADDR_HDA_SHIFT)
#define SDIO_DSCADDR_HDA(x) ((x) << SDIO_DSCADDR_HDA_SHIFT)
/* --- SDIO_BUFADDR values -------------------------------------- */
/* HBA: Host buffer address pointer */
#define SDIO_BUFADDR_HBA_SHIFT (0)
#define SDIO_BUFADDR_HBA_MASK (0xffffffff << SDIO_BUFADDR_HBA_SHIFT)
#define SDIO_BUFADDR_HBA(x) ((x) << SDIO_BUFADDR_HBA_SHIFT)
BEGIN_DECLS
/*****/
END_DECLS
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

699
Software/portapack-mayhem/hackrf/firmware/libopencm3/include/libopencm3/lpc43xx/sgpio.h Normal file
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@ -0,0 +1,699 @@
/** @defgroup sgpio_defines Serial General Purpose I/O
@brief <b>Defined Constants and Types for the LPC43xx Serial General Purpose
I/O</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/** @defgroup sdio_defines SDIO
@brief <b>Defined Constants and Types for the LPC43xx SDIO</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2012 Jared Boone <jared@sharebrained.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_SGPIO_H
#define LPC43XX_SGPIO_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- SGPIO registers ----------------------------------------------------- */
/* Pin multiplexer configuration registers (OUT_MUX_CFG0 to 15) */
#define SGPIO_OUT_MUX_CFG(pin) MMIO32(SGPIO_PORT_BASE + (pin * 0x04))
#define SGPIO_OUT_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x00)
#define SGPIO_OUT_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x04)
#define SGPIO_OUT_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x08)
#define SGPIO_OUT_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x0C)
#define SGPIO_OUT_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x10)
#define SGPIO_OUT_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x14)
#define SGPIO_OUT_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x18)
#define SGPIO_OUT_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x1C)
#define SGPIO_OUT_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x20)
#define SGPIO_OUT_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x24)
#define SGPIO_OUT_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x28)
#define SGPIO_OUT_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x2C)
#define SGPIO_OUT_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x30)
#define SGPIO_OUT_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x34)
#define SGPIO_OUT_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x38)
#define SGPIO_OUT_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x3C)
/* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */
#define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + \
(slice * 0x04))
#define SGPIO_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x40)
#define SGPIO_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x44)
#define SGPIO_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x48)
#define SGPIO_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x4C)
#define SGPIO_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x50)
#define SGPIO_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x54)
#define SGPIO_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x58)
#define SGPIO_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x5C)
#define SGPIO_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x60)
#define SGPIO_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x64)
#define SGPIO_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x68)
#define SGPIO_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x6C)
#define SGPIO_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x70)
#define SGPIO_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x74)
#define SGPIO_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x78)
#define SGPIO_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x7C)
/* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */
#define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + \
(slice * 0x04))
#define SGPIO_SLICE_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x80)
#define SGPIO_SLICE_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x84)
#define SGPIO_SLICE_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x88)
#define SGPIO_SLICE_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x8C)
#define SGPIO_SLICE_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x90)
#define SGPIO_SLICE_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x94)
#define SGPIO_SLICE_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x98)
#define SGPIO_SLICE_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x9C)
#define SGPIO_SLICE_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0xA0)
#define SGPIO_SLICE_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0xA4)
#define SGPIO_SLICE_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0xA8)
#define SGPIO_SLICE_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0xAC)
#define SGPIO_SLICE_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0xB0)
#define SGPIO_SLICE_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0xB4)
#define SGPIO_SLICE_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0xB8)
#define SGPIO_SLICE_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0xBC)
/* Slice data registers (REG0 to 15) */
#define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + \
(slice * 0x04))
#define SGPIO_REG0 MMIO32(SGPIO_PORT_BASE + 0xC0)
#define SGPIO_REG1 MMIO32(SGPIO_PORT_BASE + 0xC4)
#define SGPIO_REG2 MMIO32(SGPIO_PORT_BASE + 0xC8)
#define SGPIO_REG3 MMIO32(SGPIO_PORT_BASE + 0xCC)
#define SGPIO_REG4 MMIO32(SGPIO_PORT_BASE + 0xD0)
#define SGPIO_REG5 MMIO32(SGPIO_PORT_BASE + 0xD4)
#define SGPIO_REG6 MMIO32(SGPIO_PORT_BASE + 0xD8)
#define SGPIO_REG7 MMIO32(SGPIO_PORT_BASE + 0xDC)
#define SGPIO_REG8 MMIO32(SGPIO_PORT_BASE + 0xE0)
#define SGPIO_REG9 MMIO32(SGPIO_PORT_BASE + 0xE4)
#define SGPIO_REG10 MMIO32(SGPIO_PORT_BASE + 0xE8)
#define SGPIO_REG11 MMIO32(SGPIO_PORT_BASE + 0xEC)
#define SGPIO_REG12 MMIO32(SGPIO_PORT_BASE + 0xF0)
#define SGPIO_REG13 MMIO32(SGPIO_PORT_BASE + 0xF4)
#define SGPIO_REG14 MMIO32(SGPIO_PORT_BASE + 0xF8)
#define SGPIO_REG15 MMIO32(SGPIO_PORT_BASE + 0xFC)
/* Slice data shadow registers (REG_SS0 to 15) */
#define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + \
(slice * 0x04))
#define SGPIO_REG_SS0 MMIO32(SGPIO_PORT_BASE + 0x100)
#define SGPIO_REG_SS1 MMIO32(SGPIO_PORT_BASE + 0x104)
#define SGPIO_REG_SS2 MMIO32(SGPIO_PORT_BASE + 0x108)
#define SGPIO_REG_SS3 MMIO32(SGPIO_PORT_BASE + 0x10C)
#define SGPIO_REG_SS4 MMIO32(SGPIO_PORT_BASE + 0x110)
#define SGPIO_REG_SS5 MMIO32(SGPIO_PORT_BASE + 0x114)
#define SGPIO_REG_SS6 MMIO32(SGPIO_PORT_BASE + 0x118)
#define SGPIO_REG_SS7 MMIO32(SGPIO_PORT_BASE + 0x11C)
#define SGPIO_REG_SS8 MMIO32(SGPIO_PORT_BASE + 0x120)
#define SGPIO_REG_SS9 MMIO32(SGPIO_PORT_BASE + 0x124)
#define SGPIO_REG_SS10 MMIO32(SGPIO_PORT_BASE + 0x128)
#define SGPIO_REG_SS11 MMIO32(SGPIO_PORT_BASE + 0x12C)
#define SGPIO_REG_SS12 MMIO32(SGPIO_PORT_BASE + 0x130)
#define SGPIO_REG_SS13 MMIO32(SGPIO_PORT_BASE + 0x134)
#define SGPIO_REG_SS14 MMIO32(SGPIO_PORT_BASE + 0x138)
#define SGPIO_REG_SS15 MMIO32(SGPIO_PORT_BASE + 0x13C)
/* Reload registers (PRESET0 to 15) */
#define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + \
(slice * 0x04))
#define SGPIO_PRESET0 MMIO32(SGPIO_PORT_BASE + 0x140)
#define SGPIO_PRESET1 MMIO32(SGPIO_PORT_BASE + 0x144)
#define SGPIO_PRESET2 MMIO32(SGPIO_PORT_BASE + 0x148)
#define SGPIO_PRESET3 MMIO32(SGPIO_PORT_BASE + 0x14C)
#define SGPIO_PRESET4 MMIO32(SGPIO_PORT_BASE + 0x150)
#define SGPIO_PRESET5 MMIO32(SGPIO_PORT_BASE + 0x154)
#define SGPIO_PRESET6 MMIO32(SGPIO_PORT_BASE + 0x158)
#define SGPIO_PRESET7 MMIO32(SGPIO_PORT_BASE + 0x15C)
#define SGPIO_PRESET8 MMIO32(SGPIO_PORT_BASE + 0x160)
#define SGPIO_PRESET9 MMIO32(SGPIO_PORT_BASE + 0x164)
#define SGPIO_PRESET10 MMIO32(SGPIO_PORT_BASE + 0x168)
#define SGPIO_PRESET11 MMIO32(SGPIO_PORT_BASE + 0x16C)
#define SGPIO_PRESET12 MMIO32(SGPIO_PORT_BASE + 0x170)
#define SGPIO_PRESET13 MMIO32(SGPIO_PORT_BASE + 0x174)
#define SGPIO_PRESET14 MMIO32(SGPIO_PORT_BASE + 0x178)
#define SGPIO_PRESET15 MMIO32(SGPIO_PORT_BASE + 0x17C)
/* Down counter registers (COUNT0 to 15) */
#define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + \
(slice * 0x04))
#define SGPIO_COUNT0 MMIO32(SGPIO_PORT_BASE + 0x180)
#define SGPIO_COUNT1 MMIO32(SGPIO_PORT_BASE + 0x184)
#define SGPIO_COUNT2 MMIO32(SGPIO_PORT_BASE + 0x188)
#define SGPIO_COUNT3 MMIO32(SGPIO_PORT_BASE + 0x18C)
#define SGPIO_COUNT4 MMIO32(SGPIO_PORT_BASE + 0x190)
#define SGPIO_COUNT5 MMIO32(SGPIO_PORT_BASE + 0x194)
#define SGPIO_COUNT6 MMIO32(SGPIO_PORT_BASE + 0x198)
#define SGPIO_COUNT7 MMIO32(SGPIO_PORT_BASE + 0x19C)
#define SGPIO_COUNT8 MMIO32(SGPIO_PORT_BASE + 0x1A0)
#define SGPIO_COUNT9 MMIO32(SGPIO_PORT_BASE + 0x1A4)
#define SGPIO_COUNT10 MMIO32(SGPIO_PORT_BASE + 0x1A8)
#define SGPIO_COUNT11 MMIO32(SGPIO_PORT_BASE + 0x1AC)
#define SGPIO_COUNT12 MMIO32(SGPIO_PORT_BASE + 0x1B0)
#define SGPIO_COUNT13 MMIO32(SGPIO_PORT_BASE + 0x1B4)
#define SGPIO_COUNT14 MMIO32(SGPIO_PORT_BASE + 0x1B8)
#define SGPIO_COUNT15 MMIO32(SGPIO_PORT_BASE + 0x1BC)
/* Position registers (POS0 to 15) */
#define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + \
(slice * 0x04))
#define SGPIO_POS0 MMIO32(SGPIO_PORT_BASE + 0x1C0)
#define SGPIO_POS1 MMIO32(SGPIO_PORT_BASE + 0x1C4)
#define SGPIO_POS2 MMIO32(SGPIO_PORT_BASE + 0x1C8)
#define SGPIO_POS3 MMIO32(SGPIO_PORT_BASE + 0x1CC)
#define SGPIO_POS4 MMIO32(SGPIO_PORT_BASE + 0x1D0)
#define SGPIO_POS5 MMIO32(SGPIO_PORT_BASE + 0x1D4)
#define SGPIO_POS6 MMIO32(SGPIO_PORT_BASE + 0x1D8)
#define SGPIO_POS7 MMIO32(SGPIO_PORT_BASE + 0x1DC)
#define SGPIO_POS8 MMIO32(SGPIO_PORT_BASE + 0x1E0)
#define SGPIO_POS9 MMIO32(SGPIO_PORT_BASE + 0x1E4)
#define SGPIO_POS10 MMIO32(SGPIO_PORT_BASE + 0x1E8)
#define SGPIO_POS11 MMIO32(SGPIO_PORT_BASE + 0x1EC)
#define SGPIO_POS12 MMIO32(SGPIO_PORT_BASE + 0x1F0)
#define SGPIO_POS13 MMIO32(SGPIO_PORT_BASE + 0x1F4)
#define SGPIO_POS14 MMIO32(SGPIO_PORT_BASE + 0x1F8)
#define SGPIO_POS15 MMIO32(SGPIO_PORT_BASE + 0x1FC)
/* Slice name to slice index mapping */
#define SGPIO_SLICE_A 0
#define SGPIO_SLICE_B 1
#define SGPIO_SLICE_C 2
#define SGPIO_SLICE_D 3
#define SGPIO_SLICE_E 4
#define SGPIO_SLICE_F 5
#define SGPIO_SLICE_G 6
#define SGPIO_SLICE_H 7
#define SGPIO_SLICE_I 8
#define SGPIO_SLICE_J 9
#define SGPIO_SLICE_K 10
#define SGPIO_SLICE_L 11
#define SGPIO_SLICE_M 12
#define SGPIO_SLICE_N 13
#define SGPIO_SLICE_O 14
#define SGPIO_SLICE_P 15
/* Mask for pattern match function of slice A */
#define SGPIO_MASK_A MMIO32(SGPIO_PORT_BASE + 0x200)
/* Mask for pattern match function of slice H */
#define SGPIO_MASK_H MMIO32(SGPIO_PORT_BASE + 0x204)
/* Mask for pattern match function of slice I */
#define SGPIO_MASK_I MMIO32(SGPIO_PORT_BASE + 0x208)
/* Mask for pattern match function of slice P */
#define SGPIO_MASK_P MMIO32(SGPIO_PORT_BASE + 0x20C)
/* GPIO input status register */
#define SGPIO_GPIO_INREG MMIO32(SGPIO_PORT_BASE + 0x210)
/* GPIO output control register */
#define SGPIO_GPIO_OUTREG MMIO32(SGPIO_PORT_BASE + 0x214)
/* GPIO OE control register */
#define SGPIO_GPIO_OENREG MMIO32(SGPIO_PORT_BASE + 0x218)
/* Enables the slice COUNT counter */
#define SGPIO_CTRL_ENABLE MMIO32(SGPIO_PORT_BASE + 0x21C)
/* Disables the slice COUNT counter */
#define SGPIO_CTRL_DISABLE MMIO32(SGPIO_PORT_BASE + 0x220)
/* Shift clock interrupt clear mask */
#define SGPIO_CLR_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF00)
/* Shift clock interrupt set mask */
#define SGPIO_SET_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF04)
/* Shift clock interrupt enable */
#define SGPIO_ENABLE_0 MMIO32(SGPIO_PORT_BASE + 0xF08)
/* Shift clock interrupt status */
#define SGPIO_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF0C)
/* Shift clock interrupt clear status */
#define SGPIO_CLR_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF10)
/* Shift clock interrupt set status */
#define SGPIO_SET_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF14)
/* Exchange clock interrupt clear mask */
#define SGPIO_CLR_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF20)
/* Exchange clock interrupt set mask */
#define SGPIO_SET_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF24)
/* Exchange clock interrupt enable */
#define SGPIO_ENABLE_1 MMIO32(SGPIO_PORT_BASE + 0xF28)
/* Exchange clock interrupt status */
#define SGPIO_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF2C)
/* Exchange clock interrupt clear status */
#define SGPIO_CLR_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF30)
/* Exchange clock interrupt set status */
#define SGPIO_SET_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF34)
/* Pattern match interrupt clear mask */
#define SGPIO_CLR_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF40)
/* Pattern match interrupt set mask */
#define SGPIO_SET_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF44)
/* Pattern match interrupt enable */
#define SGPIO_ENABLE_2 MMIO32(SGPIO_PORT_BASE + 0xF48)
/* Pattern match interrupt status */
#define SGPIO_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF4C)
/* Pattern match interrupt clear status */
#define SGPIO_CLR_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF50)
/* Pattern match interrupt set status */
#define SGPIO_SET_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF54)
/* Input interrupt clear mask */
#define SGPIO_CLR_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF60)
/* Input bit match interrupt set mask */
#define SGPIO_SET_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF64)
/* Input bit match interrupt enable */
#define SGPIO_ENABLE_3 MMIO32(SGPIO_PORT_BASE + 0xF68)
/* Input bit match interrupt status */
#define SGPIO_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF6C)
/* Input bit match interrupt clear status */
#define SGPIO_CLR_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF70)
/* Input bit match interrupt set status */
#define SGPIO_SET_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF74)
/* --- Common register fields ----------------------------------- */
/* TODO: Generate this stuff with the gen.py script as well! */
#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT (0)
#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_MASK \
(0xf << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT)
#define SGPIO_OUT_MUX_CFG_P_OUT_CFG(x) \
((x) << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT)
#define SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT (4)
#define SGPIO_OUT_MUX_CFG_P_OE_CFG_MASK \
(0x7 << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT)
#define SGPIO_OUT_MUX_CFG_P_OE_CFG(x) \
((x) << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT)
#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT (0)
#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_MASK \
(1 << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT)
#define SGPIO_MUX_CFG_EXT_CLK_ENABLE(x) \
((x) << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT)
#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT (1)
#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_MASK \
(0x3 << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT)
#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(x) \
((x) << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT)
#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT (3)
#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_MASK \
(0x3 << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT)
#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(x) \
((x) << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT)
#define SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT (5)
#define SGPIO_MUX_CFG_QUALIFIER_MODE_MASK \
(0x3 << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT)
#define SGPIO_MUX_CFG_QUALIFIER_MODE(x) \
((x) << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT)
#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT (7)
#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_MASK \
(0x3 << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT)
#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(x) \
((x) << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT)
#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT (9)
#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_MASK \
(0x3 << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT)
#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(x) \
((x) << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT)
#define SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT (11)
#define SGPIO_MUX_CFG_CONCAT_ENABLE_MASK \
(1 << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT)
#define SGPIO_MUX_CFG_CONCAT_ENABLE(x) \
((x) << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT)
#define SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT (12)
#define SGPIO_MUX_CFG_CONCAT_ORDER_MASK \
(0x3 << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT)
#define SGPIO_MUX_CFG_CONCAT_ORDER(x) \
((x) << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT)
#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT (0)
#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_MASK \
(1 << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFG_MATCH_MODE(x) \
((x) << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT (1)
#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_MASK \
(1 << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(x) \
((x) << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT (2)
#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_MASK \
(1 << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(x) \
((x) << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT (3)
#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_MASK \
(1 << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT)
#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(x) \
((x) << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT)
#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT (4)
#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_MASK \
(0x3 << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(x) \
((x) << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT (6)
#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_MASK \
(0x3 << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(x) \
((x) << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT (8)
#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_MASK \
(1 << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT)
#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(x) \
((x) << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT)
#define SGPIO_POS_POS_SHIFT (0)
#define SGPIO_POS_POS_MASK (0xff << SGPIO_POS_POS_SHIFT)
#define SGPIO_POS_POS(x) ((x) << SGPIO_POS_POS_SHIFT)
#define SGPIO_POS_POS_RESET_SHIFT (8)
#define SGPIO_POS_POS_RESET_MASK (0xff << SGPIO_POS_POS_RESET_SHIFT)
#define SGPIO_POS_POS_RESET(x) ((x) << SGPIO_POS_POS_RESET_SHIFT)
/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */
/* --- SGPIO_OUT_MUX_CFG[0..15] values ------------------------------------ */
/* P_OUT_CFG: Output control of output SGPIOn */
#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT (0)
#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_MASK \
(0xf << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT)
#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG(x) \
((x) << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT)
/* P_OE_CFG: Output enable source */
#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT (4)
#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_MASK \
(0x7 << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT)
#define SGPIO_OUT_MUX_CFGx_P_OE_CFG(x) \
((x) << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT)
/* --- SGPIO_MUX_CFG[0..15] values ---------------------------------------- */
/* EXT_CLK_ENABLE: Select clock signal */
#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT (0)
#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE \
(1 << SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT)
/* CLK_SOURCE_PIN_MODE: Select source clock pin */
#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT (1)
#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_MASK \
(0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT)
#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE(x) \
((x) << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT)
/* CLK_SOURCE_SLICE_MODE: Select clock source slice */
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT (3)
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_MASK \
(0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT)
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x) \
((x) << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT)
/* QUALIFIER_MODE: Select qualifier mode */
#define SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT (5)
#define SGPIO_MUX_CFGx_QUALIFIER_MODE_MASK \
(0x3 << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT)
#define SGPIO_MUX_CFGx_QUALIFIER_MODE(x) \
((x) << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT)
/* QUALIFIER_PIN_MODE: Select qualifier pin */
#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT (7)
#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_MASK \
(0x3 << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT)
#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE(x) \
((x) << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT)
/* QUALIFIER_SLICE_MODE: Select qualifier slice */
#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT (9)
#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_MASK \
(0x3 << SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT)
#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE(x) \
((x) << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT)
/* CONCAT_ENABLE: Enable concatenation */
#define SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT (11)
#define SGPIO_MUX_CFGx_CONCAT_ENABLE \
(1 << SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT)
/* CONCAT_ORDER: Select concatenation order */
#define SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT (12)
#define SGPIO_MUX_CFGx_CONCAT_ORDER_MASK \
(0x3 << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT)
#define SGPIO_MUX_CFGx_CONCAT_ORDER(x) \
((x) << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT)
/* --- SGPIO_SLICE_MUX_CFG[0..15] values ---------------------------------- */
/* MATCH_MODE: Match mode */
#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE_SHIFT (0)
#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE \
(1 << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT)
/* CLK_CAPTURE_MODE: Capture clock mode */
#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT (1)
#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE \
(1 << SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT)
/* CLKGEN_MODE: Clock generation mode */
#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT (2)
#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE \
(1 << SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT)
/* INV_OUT_CLK: Invert output clock */
#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT (3)
#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK \
(1 << SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT)
/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */
#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT (4)
#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_MASK \
(0x3 << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE(x) \
((x) << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT)
/* PARALLEL_MODE: Parallel mode */
#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT (6)
#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_MASK \
(0x3 << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT)
#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE(x) \
((x) << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT)
/* INV_QUALIFIER: Inversion qualifier */
#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT (8)
#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER \
(1 << SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT)
/* --- SGPIO_POS[0..15] values -------------------------------------------- */
/* POS: Each time COUNT reaches 0x0 POS counts down */
#define SGPIO_POSx_POS_SHIFT (0)
#define SGPIO_POSx_POS_MASK (0xff << SGPIO_POSx_POS_SHIFT)
#define SGPIO_POSx_POS(x) ((x) << SGPIO_POSx_POS_SHIFT)
/* POS_RESET: Reload value for POS after POS reaches 0x0 */
#define SGPIO_POSx_POS_RESET_SHIFT (8)
#define SGPIO_POSx_POS_RESET_MASK (0xff << SGPIO_POSx_POS_RESET_SHIFT)
#define SGPIO_POSx_POS_RESET(x) ((x) << SGPIO_POSx_POS_RESET_SHIFT)
/* SGPIO structure for faster/better code generation (especially when optimized
* with -O2/-O3)
*/
/* This structure is compliant with LPC43xx User Manual UM10503 Rev.1.4 - 3
* September 2012
*/
typedef struct {
/* Pin multiplexer configuration registers. RW */
volatile uint32_t OUT_MUX_CFG[16];
/* SGPIO multiplexer configuration registers. RW */
volatile uint32_t SGPIO_MUX_CFG[16];
/* Slice multiplexer configuration registers. RW */
volatile uint32_t SLICE_MUX_CFG[16];
/* Slice data registers. RW */
volatile uint32_t REG[16];
/* Slice data shadow registers. Each time POS reaches 0x0 the contents
* of REG_SS is exchanged with the content of REG. RW
*/
volatile uint32_t REG_SS[16];
/* Reload registers. Counter reload value; loaded when COUNT reaches
* 0x0 RW
*/
volatile uint32_t PRESET[16];
/* Down counter registers, counts down each shift clock cycle. RW */
volatile uint32_t COUNT[16];
/* Position registers. POS Each time COUNT reaches 0x0 POS counts down.
* POS_RESET Reload value for POS after POS reaches 0x0. RW
*/
volatile uint32_t POS[16];
/* Slice A mask register. Mask for pattern match function of slice A.
* RW
*/
volatile uint32_t MASK_A;
/* Slice H mask register. Mask for pattern match function of slice H.
* RW
*/
volatile uint32_t MASK_H;
/* Slice I mask register. Mask for pattern match function of slice I.
* RW
*/
volatile uint32_t MASK_I;
/* Slice P mask register. Mask for pattern match function of slice P.
* RW
*/
volatile uint32_t MASK_P;
/* GPIO input status register. R */
volatile uint32_t GPIO_INREG;
/* GPIO output control register. RW */
volatile uint32_t GPIO_OUTREG;
/* GPIO output enable register. RW */
volatile uint32_t GPIO_OENREG;
/* Slice count enable register. RW */
volatile uint32_t CTRL_ENABLE;
/* Slice count disable register. RW */
volatile uint32_t CTRL_DISABLE;
volatile uint32_t RES0[823];
/* Shift clock interrupt clear mask register. W */
volatile uint32_t CLR_EN_0;
/* Shift clock interrupt set mask register. W */
volatile uint32_t SET_EN_0;
/* Shift clock interrupt enable register. R */
volatile uint32_t ENABLE_0;
/* Shift clock interrupt status register. R */
volatile uint32_t STATUS_0;
/* Shift clock interrupt clear status register. W */
volatile uint32_t CLR_STATUS_0;
/* Shift clock interrupt set status register. W */
volatile uint32_t SET_STATUS_0;
volatile uint32_t RES1[2];
/* Exchange clock interrupt clear mask register. W */
volatile uint32_t CLR_EN_1;
/* Exchange clock interrupt set mask register. W */
volatile uint32_t SET_EN_1;
/* Exchange clock interrupt enable. R */
volatile uint32_t ENABLE_1;
/* Exchange clock interrupt status register. R */
volatile uint32_t STATUS_1;
/* Exchange clock interrupt clear status register. W */
volatile uint32_t CLR_STATUS_1;
/* Exchange clock interrupt set status register. W */
volatile uint32_t SET_STATUS_1;
volatile uint32_t RES2[2];
/* Pattern match interrupt clear mask register. W */
volatile uint32_t CLR_EN_2;
/* Pattern match interrupt set mask register. W */
volatile uint32_t SET_EN_2;
/* Pattern match interrupt enable register. R */
volatile uint32_t ENABLE_2;
/* Pattern match interrupt status register. R */
volatile uint32_t STATUS_2;
/* Pattern match interrupt clear status register. W */
volatile uint32_t CLR_STATUS_2;
/* Pattern match interrupt set status register. W */
volatile uint32_t SET_STATUS_2;
volatile uint32_t RES3[2];
/* Input interrupt clear mask register. W */
volatile uint32_t CLR_EN_3;
/* Input bit match interrupt set mask register. W */
volatile uint32_t SET_EN_3;
/* Input bit match interrupt enable register. R */
volatile uint32_t ENABLE_3;
/* Input bit match interrupt status register. R */
volatile uint32_t STATUS_3;
/* Input bit match interrupt clear status register. W */
volatile uint32_t CLR_STATUS_3;
/* Input bit match interrupt set status register. W */
volatile uint32_t SET_STATUS_3;
} sgpio_t;
/* Global access to SGPIO structure */
#define SGPIO ((sgpio_t*)SGPIO_PORT_BASE)
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup spi_defines Serial Peripheral Interface Defines
@brief <b>Defined Constants and Types for the LPC43xx Serial Peripheral Interface</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2013 Jared Boone <jared@sharebrained.com>
@date 15 November 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Jared Boone <jared@sharebrained.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_SPI_H
#define LPC43XX_SPI_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* SPI port base addresses (for convenience) */
#define SPI (SPI_PORT_BASE)
/* --- SPI registers ----------------------------------------------------- */
/* Control Register */
#define SPI_CR MMIO32(SPI + 0x000)
/* Status Register */
#define SPI_SR MMIO32(SPI + 0x004)
/* Data Register */
#define SPI_DR MMIO32(SPI + 0x008)
/* Clock Counter Register */
#define SPI_CCR MMIO32(SPI + 0x00C)
/* Test Control Register */
#define SPI_TCR MMIO32(SPI + 0x010)
/* Test Status Register */
#define SPI_TSR MMIO32(SPI + 0x014)
/* Interrupt Flag */
#define SPI_INT MMIO32(SPI + 0x01C)
/* --- SPI_CR values -------------------------------------------- */
/* BITENABLE: Bit length enable */
#define SPI_CR_BITENABLE_SHIFT (2)
#define SPI_CR_BITENABLE_MASK (0x1 << SPI_CR_BITENABLE_SHIFT)
#define SPI_CR_BITENABLE(x) ((x) << SPI_CR_BITENABLE_SHIFT)
/* CPHA: Clock phase control */
#define SPI_CR_CPHA_SHIFT (3)
#define SPI_CR_CPHA_MASK (0x1 << SPI_CR_CPHA_SHIFT)
#define SPI_CR_CPHA(x) ((x) << SPI_CR_CPHA_SHIFT)
/* CPOL: Clock polarity control */
#define SPI_CR_CPOL_SHIFT (4)
#define SPI_CR_CPOL_MASK (0x1 << SPI_CR_CPOL_SHIFT)
#define SPI_CR_CPOL(x) ((x) << SPI_CR_CPOL_SHIFT)
/* MSTR: Master mode select */
#define SPI_CR_MSTR_SHIFT (5)
#define SPI_CR_MSTR_MASK (0x1 << SPI_CR_MSTR_SHIFT)
#define SPI_CR_MSTR(x) ((x) << SPI_CR_MSTR_SHIFT)
/* LSBF: LSB first */
#define SPI_CR_LSBF_SHIFT (6)
#define SPI_CR_LSBF_MASK (0x1 << SPI_CR_LSBF_SHIFT)
#define SPI_CR_LSBF(x) ((x) << SPI_CR_LSBF_SHIFT)
/* SPIE: Serial peripheral interrupt enable */
#define SPI_CR_SPIE_SHIFT (7)
#define SPI_CR_SPIE_MASK (0x1 << SPI_CR_SPIE_SHIFT)
#define SPI_CR_SPIE(x) ((x) << SPI_CR_SPIE_SHIFT)
/* BITS: Bits per transfer */
#define SPI_CR_BITS_SHIFT (8)
#define SPI_CR_BITS_MASK (0xf << SPI_CR_BITS_SHIFT)
#define SPI_CR_BITS(x) ((x) << SPI_CR_BITS_SHIFT)
/* SPIF: Interrupt */
#define SPI_CR_SPIF_SHIFT (0)
#define SPI_CR_SPIF_MASK (0x1 << SPI_CR_SPIF_SHIFT)
#define SPI_CR_SPIF(x) ((x) << SPI_CR_SPIF_SHIFT)
/* --- SPI_SR values -------------------------------------------- */
/* ABRT: Slave abort */
#define SPI_SR_ABRT_SHIFT (3)
#define SPI_SR_ABRT_MASK (0x1 << SPI_SR_ABRT_SHIFT)
#define SPI_SR_ABRT(x) ((x) << SPI_SR_ABRT_SHIFT)
/* MODF: Mode fault */
#define SPI_SR_MODF_SHIFT (4)
#define SPI_SR_MODF_MASK (0x1 << SPI_SR_MODF_SHIFT)
#define SPI_SR_MODF(x) ((x) << SPI_SR_MODF_SHIFT)
/* ROVR: Read overrun */
#define SPI_SR_ROVR_SHIFT (5)
#define SPI_SR_ROVR_MASK (0x1 << SPI_SR_ROVR_SHIFT)
#define SPI_SR_ROVR(x) ((x) << SPI_SR_ROVR_SHIFT)
/* WCOL: Write collision */
#define SPI_SR_WCOL_SHIFT (6)
#define SPI_SR_WCOL_MASK (0x1 << SPI_SR_WCOL_SHIFT)
#define SPI_SR_WCOL(x) ((x) << SPI_SR_WCOL_SHIFT)
/* SPIF: Transfer complete */
#define SPI_SR_SPIF_SHIFT (7)
#define SPI_SR_SPIF_MASK (0x1 << SPI_SR_SPIF_SHIFT)
#define SPI_SR_SPIF(x) ((x) << SPI_SR_SPIF_SHIFT)
/* --- SPI_DR values -------------------------------------------- */
/* DATA: Bi-directional data port */
#define SPI_DR_DATA_SHIFT (0)
#define SPI_DR_DATA_MASK (0xffff << SPI_DR_DATA_SHIFT)
#define SPI_DR_DATA(x) ((x) << SPI_DR_DATA_SHIFT)
/* --- SPI_CCR values ------------------------------------------- */
/* COUNTER: Clock counter setting */
#define SPI_CCR_COUNTER_SHIFT (0)
#define SPI_CCR_COUNTER_MASK (0xff << SPI_CCR_COUNTER_SHIFT)
#define SPI_CCR_COUNTER(x) ((x) << SPI_CCR_COUNTER_SHIFT)
/* --- SPI_TCR values ------------------------------------------- */
/* TEST: Test mode */
#define SPI_TCR_TEST_SHIFT (1)
#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT)
#define SPI_TCR_TEST(x) ((x) << SPI_TCR_TEST_SHIFT)
/* --- SPI_TSR values ------------------------------------------- */
/* ABRT: Slave abort */
#define SPI_TSR_ABRT_SHIFT (3)
#define SPI_TSR_ABRT_MASK (0x1 << SPI_TSR_ABRT_SHIFT)
#define SPI_TSR_ABRT(x) ((x) << SPI_TSR_ABRT_SHIFT)
/* MODF: Mode fault */
#define SPI_TSR_MODF_SHIFT (4)
#define SPI_TSR_MODF_MASK (0x1 << SPI_TSR_MODF_SHIFT)
#define SPI_TSR_MODF(x) ((x) << SPI_TSR_MODF_SHIFT)
/* ROVR: Read overrun */
#define SPI_TSR_ROVR_SHIFT (5)
#define SPI_TSR_ROVR_MASK (0x1 << SPI_TSR_ROVR_SHIFT)
#define SPI_TSR_ROVR(x) ((x) << SPI_TSR_ROVR_SHIFT)
/* WCOL: Write collision */
#define SPI_TSR_WCOL_SHIFT (6)
#define SPI_TSR_WCOL_MASK (0x1 << SPI_TSR_WCOL_SHIFT)
#define SPI_TSR_WCOL(x) ((x) << SPI_TSR_WCOL_SHIFT)
/* SPIF: Transfer complete */
#define SPI_TSR_SPIF_SHIFT (7)
#define SPI_TSR_SPIF_MASK (0x1 << SPI_TSR_SPIF_SHIFT)
#define SPI_TSR_SPIF(x) ((x) << SPI_TSR_SPIF_SHIFT)
BEGIN_DECLS
/*****/
END_DECLS
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup spifi_defines SPI Flash Interface (SPIFI) Defines
@brief <b>Defined Constants and Types for the LPC43xx SPI Flash Interface (SPIFI)</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2014 Jared Boone <jared@sharebrained.com>
@date 16 January 2014
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2014 Jared Boone <jared@sharebrained.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_SPIFI_H
#define LPC43XX_SPIFI_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* SPIFI port base addresses (for convenience) */
#define SPIFI (SPIFI_BASE)
/* --- SPIFI registers ----------------------------------------------------- */
/* Control Register */
#define SPIFI_CTRL MMIO32(SPIFI_BASE + 0x000)
/* Command Register */
#define SPIFI_CMD MMIO32(SPIFI_BASE + 0x004)
/* Address Register */
#define SPIFI_ADDR MMIO32(SPIFI_BASE + 0x008)
/* Intermediate Data Register */
#define SPIFI_IDATA MMIO32(SPIFI_BASE + 0x00C)
/* Cache Limit Register */
#define SPIFI_CLIMIT MMIO32(SPIFI_BASE + 0x010)
/* Data Register */
#define SPIFI_DATA MMIO32(SPIFI_BASE + 0x014)
#define SPIFI_DATA_BYTE MMIO8(SPIFI_BASE + 0x014)
/* Memory Command Register */
#define SPIFI_MCMD MMIO32(SPIFI_BASE + 0x018)
/* Status Register */
#define SPIFI_STAT MMIO32(SPIFI_BASE + 0x01C)
/* --- SPIFI_CTRL values ---------------------------------------- */
/* TIMEOUT: Memory mode idle timeout */
#define SPIFI_CTRL_TIMEOUT_SHIFT (0)
#define SPIFI_CTRL_TIMEOUT_MASK (0xffff << SPIFI_CTRL_TIMEOUT_SHIFT)
#define SPIFI_CTRL_TIMEOUT(x) ((x) << SPIFI_CTRL_TIMEOUT_SHIFT)
/* CSHIGH: Minimum CS# high time */
#define SPIFI_CTRL_CSHIGH_SHIFT (16)
#define SPIFI_CTRL_CSHIGH_MASK (0xf << SPIFI_CTRL_CSHIGH_SHIFT)
#define SPIFI_CTRL_CSHIGH(x) ((x) << SPIFI_CTRL_CSHIGH_SHIFT)
/* D_PRFTCH_DIS: Disable speculative prefetch */
#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21)
#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x1 << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)
#define SPIFI_CTRL_D_PRFTCH_DIS(x) ((x) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)
/* INTEN: Enable command end interrupt */
#define SPIFI_CTRL_INTEN_SHIFT (22)
#define SPIFI_CTRL_INTEN_MASK (0x1 << SPIFI_CTRL_INTEN_SHIFT)
#define SPIFI_CTRL_INTEN(x) ((x) << SPIFI_CTRL_INTEN_SHIFT)
/* MODE3: SPI mode 3 select */
#define SPIFI_CTRL_MODE3_SHIFT (23)
#define SPIFI_CTRL_MODE3_MASK (0x1 << SPIFI_CTRL_MODE3_SHIFT)
#define SPIFI_CTRL_MODE3(x) ((x) << SPIFI_CTRL_MODE3_SHIFT)
/* PRFTCH_DIS: Disable prefetching of cache lines */
#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27)
#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x1 << SPIFI_CTRL_PRFTCH_DIS_SHIFT)
#define SPIFI_CTRL_PRFTCH_DIS(x) ((x) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)
/* DUAL: Select dual protocol */
#define SPIFI_CTRL_DUAL_SHIFT (28)
#define SPIFI_CTRL_DUAL_MASK (0x1 << SPIFI_CTRL_DUAL_SHIFT)
#define SPIFI_CTRL_DUAL(x) ((x) << SPIFI_CTRL_DUAL_SHIFT)
/* RFCLK: Read data on falling edge */
#define SPIFI_CTRL_RFCLK_SHIFT (29)
#define SPIFI_CTRL_RFCLK_MASK (0x1 << SPIFI_CTRL_RFCLK_SHIFT)
#define SPIFI_CTRL_RFCLK(x) ((x) << SPIFI_CTRL_RFCLK_SHIFT)
/* FBCLK: Feedback clock select */
#define SPIFI_CTRL_FBCLK_SHIFT (30)
#define SPIFI_CTRL_FBCLK_MASK (0x1 << SPIFI_CTRL_FBCLK_SHIFT)
#define SPIFI_CTRL_FBCLK(x) ((x) << SPIFI_CTRL_FBCLK_SHIFT)
/* DMAEN: DMA request output enable */
#define SPIFI_CTRL_DMAEN_SHIFT (31)
#define SPIFI_CTRL_DMAEN_MASK (0x1 << SPIFI_CTRL_DMAEN_SHIFT)
#define SPIFI_CTRL_DMAEN(x) ((x) << SPIFI_CTRL_DMAEN_SHIFT)
/* --- SPIFI_CMD values ----------------------------------------- */
/* DATALEN: Data bytes in command */
#define SPIFI_CMD_DATALEN_SHIFT (0)
#define SPIFI_CMD_DATALEN_MASK (0x3fff << SPIFI_CMD_DATALEN_SHIFT)
#define SPIFI_CMD_DATALEN(x) ((x) << SPIFI_CMD_DATALEN_SHIFT)
/* POLL: Poll at end of command */
#define SPIFI_CMD_POLL_SHIFT (14)
#define SPIFI_CMD_POLL_MASK (0x1 << SPIFI_CMD_POLL_SHIFT)
#define SPIFI_CMD_POLL(x) ((x) << SPIFI_CMD_POLL_SHIFT)
/* DOUT: Data output to serial flash */
#define SPIFI_CMD_DOUT_SHIFT (15)
#define SPIFI_CMD_DOUT_MASK (0x1 << SPIFI_CMD_DOUT_SHIFT)
#define SPIFI_CMD_DOUT(x) ((x) << SPIFI_CMD_DOUT_SHIFT)
/* INTLEN: Intermediate bytes before data */
#define SPIFI_CMD_INTLEN_SHIFT (16)
#define SPIFI_CMD_INTLEN_MASK (0x7 << SPIFI_CMD_INTLEN_SHIFT)
#define SPIFI_CMD_INTLEN(x) ((x) << SPIFI_CMD_INTLEN_SHIFT)
/* FIELDFORM: Form of command fields */
#define SPIFI_CMD_FIELDFORM_SHIFT (19)
#define SPIFI_CMD_FIELDFORM_MASK (0x3 << SPIFI_CMD_FIELDFORM_SHIFT)
#define SPIFI_CMD_FIELDFORM(x) ((x) << SPIFI_CMD_FIELDFORM_SHIFT)
/* FRAMEFORM: Form of the opcode/address fields */
#define SPIFI_CMD_FRAMEFORM_SHIFT (21)
#define SPIFI_CMD_FRAMEFORM_MASK (0x7 << SPIFI_CMD_FRAMEFORM_SHIFT)
#define SPIFI_CMD_FRAMEFORM(x) ((x) << SPIFI_CMD_FRAMEFORM_SHIFT)
/* OPCODE: Command opcode */
#define SPIFI_CMD_OPCODE_SHIFT (24)
#define SPIFI_CMD_OPCODE_MASK (0xff << SPIFI_CMD_OPCODE_SHIFT)
#define SPIFI_CMD_OPCODE(x) ((x) << SPIFI_CMD_OPCODE_SHIFT)
/* --- SPIFI_ADDR values ---------------------------------------- */
/* ADDRESS: Address field value */
#define SPIFI_ADDR_ADDRESS_SHIFT (0)
#define SPIFI_ADDR_ADDRESS_MASK (0xffffffff << SPIFI_ADDR_ADDRESS_SHIFT)
#define SPIFI_ADDR_ADDRESS(x) ((x) << SPIFI_ADDR_ADDRESS_SHIFT)
/* --- SPIFI_IDATA values --------------------------------------- */
/* IDATA: Intermediate bytes value */
#define SPIFI_IDATA_IDATA_SHIFT (0)
#define SPIFI_IDATA_IDATA_MASK (0xffffffff << SPIFI_IDATA_IDATA_SHIFT)
#define SPIFI_IDATA_IDATA(x) ((x) << SPIFI_IDATA_IDATA_SHIFT)
/* --- SPIFI_CLIMIT values -------------------------------------- */
/* CLIMIT: Upper limit of cacheable memory */
#define SPIFI_CLIMIT_CLIMIT_SHIFT (0)
#define SPIFI_CLIMIT_CLIMIT_MASK (0xffffffff << SPIFI_CLIMIT_CLIMIT_SHIFT)
#define SPIFI_CLIMIT_CLIMIT(x) ((x) << SPIFI_CLIMIT_CLIMIT_SHIFT)
/* --- SPIFI_DATA values ---------------------------------------- */
/* DATA: Input or output data */
#define SPIFI_DATA_DATA_SHIFT (0)
#define SPIFI_DATA_DATA_MASK (0xffffffff << SPIFI_DATA_DATA_SHIFT)
#define SPIFI_DATA_DATA(x) ((x) << SPIFI_DATA_DATA_SHIFT)
/* --- SPIFI_MCMD values ---------------------------------------- */
/* POLL: Must be zero */
#define SPIFI_MCMD_POLL_SHIFT (14)
#define SPIFI_MCMD_POLL_MASK (0x1 << SPIFI_MCMD_POLL_SHIFT)
#define SPIFI_MCMD_POLL(x) ((x) << SPIFI_MCMD_POLL_SHIFT)
/* DOUT: Must be zero */
#define SPIFI_MCMD_DOUT_SHIFT (15)
#define SPIFI_MCMD_DOUT_MASK (0x1 << SPIFI_MCMD_DOUT_SHIFT)
#define SPIFI_MCMD_DOUT(x) ((x) << SPIFI_MCMD_DOUT_SHIFT)
/* INTLEN: Intermediate bytes before data */
#define SPIFI_MCMD_INTLEN_SHIFT (16)
#define SPIFI_MCMD_INTLEN_MASK (0x7 << SPIFI_MCMD_INTLEN_SHIFT)
#define SPIFI_MCMD_INTLEN(x) ((x) << SPIFI_MCMD_INTLEN_SHIFT)
/* FIELDFORM: Form of command fields */
#define SPIFI_MCMD_FIELDFORM_SHIFT (19)
#define SPIFI_MCMD_FIELDFORM_MASK (0x3 << SPIFI_MCMD_FIELDFORM_SHIFT)
#define SPIFI_MCMD_FIELDFORM(x) ((x) << SPIFI_MCMD_FIELDFORM_SHIFT)
/* FRAMEFORM: Form of the opcode/address fields */
#define SPIFI_MCMD_FRAMEFORM_SHIFT (21)
#define SPIFI_MCMD_FRAMEFORM_MASK (0x7 << SPIFI_MCMD_FRAMEFORM_SHIFT)
#define SPIFI_MCMD_FRAMEFORM(x) ((x) << SPIFI_MCMD_FRAMEFORM_SHIFT)
/* OPCODE: Command opcode */
#define SPIFI_MCMD_OPCODE_SHIFT (24)
#define SPIFI_MCMD_OPCODE_MASK (0xff << SPIFI_MCMD_OPCODE_SHIFT)
#define SPIFI_MCMD_OPCODE(x) ((x) << SPIFI_MCMD_OPCODE_SHIFT)
/* --- SPIFI_STAT values ---------------------------------------- */
/* MCINIT: Memory command initialized */
#define SPIFI_STAT_MCINIT_SHIFT (0)
#define SPIFI_STAT_MCINIT_MASK (0x1 << SPIFI_STAT_MCINIT_SHIFT)
#define SPIFI_STAT_MCINIT(x) ((x) << SPIFI_STAT_MCINIT_SHIFT)
/* CMD: Command active */
#define SPIFI_STAT_CMD_SHIFT (1)
#define SPIFI_STAT_CMD_MASK (0x1 << SPIFI_STAT_CMD_SHIFT)
#define SPIFI_STAT_CMD(x) ((x) << SPIFI_STAT_CMD_SHIFT)
/* RESET: Abort current command/memory mode */
#define SPIFI_STAT_RESET_SHIFT (4)
#define SPIFI_STAT_RESET_MASK (0x1 << SPIFI_STAT_RESET_SHIFT)
#define SPIFI_STAT_RESET(x) ((x) << SPIFI_STAT_RESET_SHIFT)
/* INTRQ: Interrupt request status */
#define SPIFI_STAT_INTRQ_SHIFT (5)
#define SPIFI_STAT_INTRQ_MASK (0x1 << SPIFI_STAT_INTRQ_SHIFT)
#define SPIFI_STAT_INTRQ(x) ((x) << SPIFI_STAT_INTRQ_SHIFT)
/* VERSION: Peripheral hardware version */
#define SPIFI_STAT_VERSION_SHIFT (24)
#define SPIFI_STAT_VERSION_MASK (0xff << SPIFI_STAT_VERSION_SHIFT)
#define SPIFI_STAT_VERSION(x) ((x) << SPIFI_STAT_VERSION_SHIFT)
BEGIN_DECLS
END_DECLS
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup ssp_defines Synchronous Serial Port
@brief <b>Defined Constants and Types for the LPC43xx Synchronous Serial
Port</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_SSP_H
#define LPC43XX_SSP_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* SSP port base addresses (for convenience) */
#define SSP0 SSP0_BASE
#define SSP1 SSP1_BASE
/* --- SSP registers ------------------------------------------------------- */
/* Control Register 0 */
#define SSP_CR0(port) MMIO32(port + 0x000)
#define SSP0_CR0 SSP_CR0(SSP0)
#define SSP1_CR0 SSP_CR0(SSP1)
/* Control Register 1 */
#define SSP_CR1(port) MMIO32(port + 0x004)
#define SSP0_CR1 SSP_CR1(SSP0)
#define SSP1_CR1 SSP_CR1(SSP1)
/* Data Register */
#define SSP_DR(port) MMIO32(port + 0x008)
#define SSP0_DR SSP_DR(SSP0)
#define SSP1_DR SSP_DR(SSP1)
/* Status Register */
#define SSP_SR(port) MMIO32(port + 0x00C)
#define SSP0_SR SSP_SR(SSP0)
#define SSP1_SR SSP_SR(SSP1)
#define SSP_SR_TFE BIT0
#define SSP_SR_TNF BIT1
#define SSP_SR_RNE BIT2
#define SSP_SR_RFF BIT3
#define SSP_SR_BSY BIT4
/* Clock Prescale Register */
#define SSP_CPSR(port) MMIO32(port + 0x010)
#define SSP0_CPSR SSP_CPSR(SSP0)
#define SSP1_CPSR SSP_CPSR(SSP1)
/* Interrupt Mask Set and Clear Register */
#define SSP_IMSC(port) MMIO32(port + 0x014)
#define SSP0_IMSC SSP_IMSC(SSP0)
#define SSP1_IMSC SSP_IMSC(SSP1)
/* Raw Interrupt Status Register */
#define SSP_RIS(port) MMIO32(port + 0x018)
#define SSP0_RIS SSP_RIS(SSP0)
#define SSP1_RIS SSP_RIS(SSP1)
/* Masked Interrupt Status Register */
#define SSP_MIS(port) MMIO32(port + 0x01C)
#define SSP0_MIS SSP_MIS(SSP0)
#define SSP1_MIS SSP_MIS(SSP1)
/* SSPICR Interrupt Clear Register */
#define SSP_ICR(port) MMIO32(port + 0x020)
#define SSP0_ICR SSP_ICR(SSP0)
#define SSP1_ICR SSP_ICR(SSP1)
/* SSP1 DMA control register */
#define SSP_DMACR(port) MMIO32(port + 0x024)
#define SSP0_DMACR SSP_DMACR(SSP0)
#define SSP1_DMACR SSP_DMACR(SSP1)
/* RXDMAE: Receive DMA enable */
#define SSP_DMACR_RXDMAE 0x1
/* RXDMAE: Transmit DMA enable */
#define SSP_DMACR_TXDMAE 0x2
typedef enum {
SSP0_NUM = 0x0,
SSP1_NUM = 0x1
} ssp_num_t;
/*
* SSP Control Register 0
*/
/* SSP Data Size Bits 0 to 3 */
typedef enum {
SSP_DATA_4BITS = 0x3,
SSP_DATA_5BITS = 0x4,
SSP_DATA_6BITS = 0x5,
SSP_DATA_7BITS = 0x6,
SSP_DATA_8BITS = 0x7,
SSP_DATA_9BITS = 0x8,
SSP_DATA_10BITS = 0x9,
SSP_DATA_11BITS = 0xA,
SSP_DATA_12BITS = 0xB,
SSP_DATA_13BITS = 0xC,
SSP_DATA_14BITS = 0xD,
SSP_DATA_15BITS = 0xE,
SSP_DATA_16BITS = 0xF
} ssp_datasize_t;
/* SSP Frame Format/Type Bits 4 & 5 */
typedef enum {
SSP_FRAME_SPI = 0x00,
SSP_FRAME_TI = BIT4,
SSP_FRAM_MICROWIRE = BIT5
} ssp_frame_format_t;
/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */
typedef enum {
SSP_CPOL_0_CPHA_0 = 0x0,
SSP_CPOL_1_CPHA_0 = BIT6,
SSP_CPOL_0_CPHA_1 = BIT7,
SSP_CPOL_1_CPHA_1 = (BIT6|BIT7)
} ssp_cpol_cpha_t;
/*
* SSP Control Register 1
*/
/* SSP Mode Bit0 */
typedef enum {
SSP_MODE_NORMAL = 0x0,
SSP_MODE_LOOPBACK = BIT0
} ssp_mode_t;
/* SSP Enable Bit1 */
#define SSP_ENABLE BIT1
/* SSP Master/Slave Mode Bit2 */
typedef enum {
SSP_MASTER = 0x0,
SSP_SLAVE = BIT2
} ssp_master_slave_t;
/*
* SSP Slave Output Disable Bit3
* Slave Output Disable. This bit is relevant only in slave mode
* (MS = 1). If it is 1, this blocks this SSP controller from driving the
* transmit data line (MISO).
*/
typedef enum {
SSP_SLAVE_OUT_ENABLE = 0x0,
SSP_SLAVE_OUT_DISABLE = BIT3
} ssp_slave_option_t; /* This option is relevant only in slave mode */
BEGIN_DECLS
void ssp_disable(ssp_num_t ssp_num);
/*
* SSP Init
* clk_prescale shall be in range 2 to 254 (even number only).
* Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale,
* SCR=serial_clock_rate
*/
void ssp_init(ssp_num_t ssp_num,
ssp_datasize_t data_size,
ssp_frame_format_t frame_format,
ssp_cpol_cpha_t cpol_cpha_format,
uint8_t serial_clock_rate,
uint8_t clk_prescale,
ssp_mode_t mode,
ssp_master_slave_t master_slave,
ssp_slave_option_t slave_option);
uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data);
END_DECLS
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup timer_defines Timer
@brief <b>Defined Constants and Types for the LPC43xx timer</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_TIMER_H
#define LPC43XX_TIMER_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* Timer base addresses */
#define TIMER0 TIMER0_BASE
#define TIMER1 TIMER1_BASE
#define TIMER2 TIMER2_BASE
#define TIMER3 TIMER3_BASE
/* --- Timer registers ----------------------------------------------------- */
/* Interrupt Register */
#define TIMER_IR(timer) MMIO32(timer + 0x000)
#define TIMER0_IR TIMER_IR(TIMER0)
#define TIMER1_IR TIMER_IR(TIMER1)
#define TIMER2_IR TIMER_IR(TIMER2)
#define TIMER3_IR TIMER_IR(TIMER3)
/* Timer Control Register */
#define TIMER_TCR(timer) MMIO32(timer + 0x004)
#define TIMER0_TCR TIMER_TCR(TIMER0)
#define TIMER1_TCR TIMER_TCR(TIMER1)
#define TIMER2_TCR TIMER_TCR(TIMER2)
#define TIMER3_TCR TIMER_TCR(TIMER3)
/* Timer Counter */
#define TIMER_TC(timer) MMIO32(timer + 0x008)
#define TIMER0_TC TIMER_TC(TIMER0)
#define TIMER1_TC TIMER_TC(TIMER1)
#define TIMER2_TC TIMER_TC(TIMER2)
#define TIMER3_TC TIMER_TC(TIMER3)
/* Prescale Register */
#define TIMER_PR(timer) MMIO32(timer + 0x00C)
#define TIMER0_PR TIMER_PR(TIMER0)
#define TIMER1_PR TIMER_PR(TIMER1)
#define TIMER2_PR TIMER_PR(TIMER2)
#define TIMER3_PR TIMER_PR(TIMER3)
/* Prescale Counter */
#define TIMER_PC(timer) MMIO32(timer + 0x010)
#define TIMER0_PC TIMER_PC(TIMER0)
#define TIMER1_PC TIMER_PC(TIMER1)
#define TIMER2_PC TIMER_PC(TIMER2)
#define TIMER3_PC TIMER_PC(TIMER3)
/* Match Control Register */
#define TIMER_MCR(timer) MMIO32(timer + 0x014)
#define TIMER0_MCR TIMER_MCR(TIMER0)
#define TIMER1_MCR TIMER_MCR(TIMER1)
#define TIMER2_MCR TIMER_MCR(TIMER2)
#define TIMER3_MCR TIMER_MCR(TIMER3)
/* Match Register 0 */
#define TIMER_MR0(timer) MMIO32(timer + 0x018)
#define TIMER0_MR0 TIMER_MR0(TIMER0)
#define TIMER1_MR0 TIMER_MR0(TIMER1)
#define TIMER2_MR0 TIMER_MR0(TIMER2)
#define TIMER3_MR0 TIMER_MR0(TIMER3)
/* Match Register 1 */
#define TIMER_MR1(timer) MMIO32(timer + 0x01C)
#define TIMER0_MR1 TIMER_MR1(TIMER0)
#define TIMER1_MR1 TIMER_MR1(TIMER1)
#define TIMER2_MR1 TIMER_MR1(TIMER2)
#define TIMER3_MR1 TIMER_MR1(TIMER3)
/* Match Register 2 */
#define TIMER_MR2(timer) MMIO32(timer + 0x020)
#define TIMER0_MR2 TIMER_MR2(TIMER0)
#define TIMER1_MR2 TIMER_MR2(TIMER1)
#define TIMER2_MR2 TIMER_MR2(TIMER2)
#define TIMER3_MR2 TIMER_MR2(TIMER3)
/* Match Register 3 */
#define TIMER_MR3(timer) MMIO32(timer + 0x024)
#define TIMER0_MR3 TIMER_MR3(TIMER0)
#define TIMER1_MR3 TIMER_MR3(TIMER1)
#define TIMER2_MR3 TIMER_MR3(TIMER2)
#define TIMER3_MR3 TIMER_MR3(TIMER3)
/* Capture Control Register */
#define TIMER_CCR(timer) MMIO32(timer + 0x028)
#define TIMER0_CCR TIMER_CCR(TIMER0)
#define TIMER1_CCR TIMER_CCR(TIMER1)
#define TIMER2_CCR TIMER_CCR(TIMER2)
#define TIMER3_CCR TIMER_CCR(TIMER3)
/* Capture Register 0 */
#define TIMER_CR0(timer) MMIO32(timer + 0x02C)
#define TIMER0_CR0 TIMER_CR0(TIMER0)
#define TIMER1_CR0 TIMER_CR0(TIMER1)
#define TIMER2_CR0 TIMER_CR0(TIMER2)
#define TIMER3_CR0 TIMER_CR0(TIMER3)
/* Capture Register 1 */
#define TIMER_CR1(timer) MMIO32(timer + 0x030)
#define TIMER0_CR1 TIMER_CR1(TIMER0)
#define TIMER1_CR1 TIMER_CR1(TIMER1)
#define TIMER2_CR1 TIMER_CR1(TIMER2)
#define TIMER3_CR1 TIMER_CR1(TIMER3)
/* Capture Register 2 */
#define TIMER_CR2(timer) MMIO32(timer + 0x034)
#define TIMER0_CR2 TIMER_CR2(TIMER0)
#define TIMER1_CR2 TIMER_CR2(TIMER1)
#define TIMER2_CR2 TIMER_CR2(TIMER2)
#define TIMER3_CR2 TIMER_CR2(TIMER3)
/* Capture Register 3 */
#define TIMER_CR3(timer) MMIO32(timer + 0x038)
#define TIMER0_CR3 TIMER_CR3(TIMER0)
#define TIMER1_CR3 TIMER_CR3(TIMER1)
#define TIMER2_CR3 TIMER_CR3(TIMER2)
#define TIMER3_CR3 TIMER_CR3(TIMER3)
/* External Match Register */
#define TIMER_EMR(timer) MMIO32(timer + 0x03C)
#define TIMER0_EMR TIMER_EMR(TIMER0)
#define TIMER1_EMR TIMER_EMR(TIMER1)
#define TIMER2_EMR TIMER_EMR(TIMER2)
#define TIMER3_EMR TIMER_EMR(TIMER3)
/* Count Control Register */
#define TIMER_CTCR(timer) MMIO32(timer + 0x070)
#define TIMER0_CTCR TIMER_CTCR(TIMER0)
#define TIMER1_CTCR TIMER_CTCR(TIMER1)
#define TIMER2_CTCR TIMER_CTCR(TIMER2)
#define TIMER3_CTCR TIMER_CTCR(TIMER3)
/* --- TIMERx_IR values ----------------------------------------------------- */
#define TIMER_IR_MR0INT (1 << 0)
#define TIMER_IR_MR1INT (1 << 1)
#define TIMER_IR_MR2INT (1 << 2)
#define TIMER_IR_MR3INT (1 << 3)
#define TIMER_IR_CR0INT (1 << 4)
#define TIMER_IR_CR1INT (1 << 5)
#define TIMER_IR_CR2INT (1 << 6)
#define TIMER_IR_CR3INT (1 << 7)
/* --- TIMERx_TCR values --------------------------------------------------- */
#define TIMER_TCR_CEN (1 << 0)
#define TIMER_TCR_CRST (1 << 1)
/* --- TIMERx_MCR values --------------------------------------------------- */
#define TIMER_MCR_MR0I (1 << 0)
#define TIMER_MCR_MR0R (1 << 1)
#define TIMER_MCR_MR0S (1 << 2)
#define TIMER_MCR_MR1I (1 << 3)
#define TIMER_MCR_MR1R (1 << 4)
#define TIMER_MCR_MR1S (1 << 5)
#define TIMER_MCR_MR2I (1 << 6)
#define TIMER_MCR_MR2R (1 << 7)
#define TIMER_MCR_MR2S (1 << 8)
#define TIMER_MCR_MR3I (1 << 9)
#define TIMER_MCR_MR3R (1 << 10)
#define TIMER_MCR_MR3S (1 << 11)
/* --- TIMERx_MCR values --------------------------------------------------- */
#define TIMER_CCR_CAP0RE (1 << 0)
#define TIMER_CCR_CAP0FE (1 << 1)
#define TIMER_CCR_CAP0I (1 << 2)
#define TIMER_CCR_CAP1RE (1 << 3)
#define TIMER_CCR_CAP1FE (1 << 4)
#define TIMER_CCR_CAP1I (1 << 5)
#define TIMER_CCR_CAP2RE (1 << 6)
#define TIMER_CCR_CAP2FE (1 << 7)
#define TIMER_CCR_CAP2I (1 << 8)
#define TIMER_CCR_CAP3RE (1 << 9)
#define TIMER_CCR_CAP3FE (1 << 10)
#define TIMER_CCR_CAP3I (1 << 11)
/* --- TIMERx_EMR values --------------------------------------------------- */
#define TIMER_EMR_EM0 (1 << 0)
#define TIMER_EMR_EM1 (1 << 1)
#define TIMER_EMR_EM2 (1 << 2)
#define TIMER_EMR_EM3 (1 << 3)
#define TIMER_EMR_EMC0_SHIFT 4
#define TIMER_EMR_EMC0_MASK (0x3 << TIMER_EMR_EMC0_SHIFT)
#define TIMER_EMR_EMC1_SHIFT 6
#define TIMER_EMR_EMC1_MASK (0x3 << TIMER_EMR_EMC1_SHIFT)
#define TIMER_EMR_EMC2_SHIFT 8
#define TIMER_EMR_EMC2_MASK (0x3 << TIMER_EMR_EMC2_SHIFT)
#define TIMER_EMR_EMC3_SHIFT 10
#define TIMER_EMR_EMC3_MASK (0x3 << TIMER_EMR_EMC3_SHIFT)
#define TIMER_EMR_EMC_NOTHING 0x0
#define TIMER_EMR_EMC_CLEAR 0x1
#define TIMER_EMR_EMC_SET 0x2
#define TIMER_EMR_EMC_TOGGLE 0x3
/* --- TIMERx_CTCR values -------------------------------------------------- */
#define TIMER_CTCR_MODE_TIMER (0x0 << 0)
#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0)
#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0)
#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0)
#define TIMER_CTCR_MODE_MASK (0x3 << 0)
#define TIMER_CTCR_CINSEL_CAPN_0 (0x0 << 2)
#define TIMER_CTCR_CINSEL_CAPN_1 (0x1 << 2)
#define TIMER_CTCR_CINSEL_CAPN_2 (0x2 << 2)
#define TIMER_CTCR_CINSEL_CAPN_3 (0x3 << 2)
#define TIMER_CTCR_CINSEL_MASK (0x3 << 2)
/* --- TIMER function prototypes ------------------------------------------- */
BEGIN_DECLS
void timer_reset(uint32_t timer_peripheral);
void timer_enable_counter(uint32_t timer_peripheral);
void timer_disable_counter(uint32_t timer_peripheral);
uint32_t timer_get_counter(uint32_t timer_peripheral);
void timer_set_counter(uint32_t timer_peripheral, uint32_t count);
uint32_t timer_get_prescaler(uint32_t timer_peripheral);
void timer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler);
void timer_set_mode(uint32_t timer_peripheral, uint32_t mode);
void timer_set_count_input(uint32_t timer_peripheral, uint32_t input);
END_DECLS
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_UART_H
#define LPC43XX_UART_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Convenience macros -------------------------------------------------- */
/* UART port base addresses (for convenience) */
#define UART0 USART0_BASE /* APB0 */
#define UART1 UART1_BASE /* APB0 */
#define UART2 USART2_BASE /* APB2 */
#define UART3 USART3_BASE /* APB2 */
/* --- UART registers ------------------------------------------------------- */
/* Receiver Buffer Register (DLAB=0) Read Only */
#define UART_RBR(port) MMIO32(port + 0x000) /* 8bits */
/* Transmitter Holding Register (DLAB=0) Write Only */
#define UART_THR(port) MMIO32(port + 0x000) /* 8bits */
/* Divisor Latch LSB Register (DLAB=1) */
#define UART_DLL(port) MMIO32(port + 0x000) /* 8bits */
/* Divisor Latch MSB Register (DLAB=1) */
#define UART_DLM(port) MMIO32(port + 0x004) /* 8bits */
/* Interrupt Enable Register (DLAB=0) */
#define UART_IER(port) MMIO32(port + 0x004)
/* Interrupt ID Register Read Only */
#define UART_IIR(port) MMIO32(port + 0x008)
/* FIFO Control Register Write Only */
#define UART_FCR(port) MMIO32(port + 0x008)
/* Line Control Register */
#define UART_LCR(port) MMIO32(port + 0x00C)
/* MCR only for UART1 */
/* Line Status Register */
#define UART_LSR(port) MMIO32(port + 0x014)
/* Auto Baud Control Register */
#define UART_ACR(port) MMIO32(port + 0x020)
/* IrDA Control Register only for UART0/2/3 */
#define UART_ICR(port) MMIO32(port + 0x024)
/* Fractional Divider Register */
#define UART_FDR(port) MMIO32(port + 0x028)
/* Oversampling Register only for UART0/2/3 */
#define UART_OSR(port) MMIO32(port + 0x02C)
/* Half-Duplex enable Register only for UART0/2/3 */
#define UART_HDEN(port) MMIO32(port + 0x040)
/* Smart card Interface Register Only for UART0/2/3 */
#define UART_SCICTRL(port) MMIO32(port + 0x048)
/* RS-485/EIA-485 Control Register */
#define UART_RS485CTRL(port) MMIO32(port + 0x04C)
/* RS-485/EIA-485 Address Match Register */
#define UART_RS485ADRMATCH(port) MMIO32(port + 0x050)
/* RS-485/EIA-485 Direction Control Delay Register */
#define UART_RS485DLY(port) MMIO32(port + 0x054)
/* Synchronous Mode Control Register only for UART0/2/3 */
#define UART_SYNCCTRL(port) MMIO32(port + 0x058)
/* Transmit Enable Register */
#define UART_TER(port) MMIO32(port + 0x05C)
/* --------------------- BIT DEFINITIONS ----------------------------------- */
/***********************************************************************
* Macro defines for Macro defines for UARTn Receiver Buffer Register
**********************************************************************/
/* UART Received Buffer mask bit (8 bits) */
#define UART_RBR_MASKBIT ((uint8_t)0xFF)
/***********************************************************************
* Macro defines for Macro defines for UARTn Transmit Holding Register
**********************************************************************/
/* UART Transmit Holding mask bit (8 bits) */
#define UART_THR_MASKBIT ((uint8_t)0xFF)
/***********************************************************************
* Macro defines for Macro defines for UARTn Divisor Latch LSB register
**********************************************************************/
/* Macro for loading least significant halfs of divisors */
#define UART_LOAD_DLL(div) ((div) & 0xFF)
/* Divisor latch LSB bit mask */
#define UART_DLL_MASKBIT ((uint8_t)0xFF)
/***********************************************************************
* Macro defines for Macro defines for UARTn Divisor Latch MSB register
**********************************************************************/
/* Divisor latch MSB bit mask */
#define UART_DLM_MASKBIT ((uint8_t)0xFF)
/* Macro for loading most significant halfs of divisors */
#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF)
/***********************************************************************
* Macro defines for Macro defines for UART interrupt enable register
**********************************************************************/
/* RBR Interrupt enable*/
#define UART_IER_RBRINT_EN (1 << 0)
/* THR Interrupt enable*/
#define UART_IER_THREINT_EN (1 << 1)
/* RX line status interrupt enable*/
#define UART_IER_RLSINT_EN (1 << 2)
/* Modem status interrupt enable */
#define UART1_IER_MSINT_EN (1 << 3)
/* CTS1 signal transition interrupt enable */
#define UART1_IER_CTSINT_EN (1 << 7)
/* Enables the end of auto-baud interrupt */
#define UART_IER_ABEOINT_EN (1 << 8)
/* Enables the auto-baud time-out interrupt */
#define UART_IER_ABTOINT_EN (1 << 9)
/* UART interrupt enable register bit mask */
#define UART_IER_BITMASK ((uint32_t)(0x307))
/* UART1 interrupt enable register bit mask */
#define UART1_IER_BITMASK ((uint32_t)(0x38F))
/**********************************************************************
* Macro defines for Macro defines for UART interrupt identification register
**********************************************************************/
/* Interrupt Status - Active low */
#define UART_IIR_INTSTAT_PEND (1 << 0)
/* Interrupt identification: Modem interrupt*/
#define UART1_IIR_INTID_MODEM (0 << 1)
/* Interrupt identification: THRE interrupt*/
#define UART_IIR_INTID_THRE (1 << 1)
/* Interrupt identification: Receive data available*/
#define UART_IIR_INTID_RDA (2 << 1)
/* Interrupt identification: Receive line status*/
#define UART_IIR_INTID_RLS (3 << 1)
/* Interrupt identification: Character time-out indicator*/
#define UART_IIR_INTID_CTI (6 << 1)
/* Interrupt identification: Interrupt ID mask */
#define UART_IIR_INTID_MASK (7 << 1)
/* These bits are equivalent to UnFCR[0] */
#define UART_IIR_FIFO_EN (3 << 6)
/* End of auto-baud interrupt */
#define UART_IIR_ABEO_INT (1 << 8)
/* Auto-baud time-out interrupt */
#define UART_IIR_ABTO_INT (1 << 9)
/* UART interrupt identification register bit mask */
#define UART_IIR_BITMASK ((uint32_t)(0x3CF))
/**********************************************************************
* Macro defines for Macro defines for UART FIFO control register
**********************************************************************/
/* UART FIFO enable */
#define UART_FCR_FIFO_EN (1 << 0)
/* UART FIFO RX reset */
#define UART_FCR_RX_RS (1 << 1)
/* UART FIFO TX reset */
#define UART_FCR_TX_RS (1 << 2)
/* UART DMA mode selection */
#define UART_FCR_DMAMODE_SEL (1 << 3)
/* UART FIFO trigger level 0: 1 character */
#define UART_FCR_TRG_LEV0 (0 << 6)
/* UART FIFO trigger level 1: 4 character */
#define UART_FCR_TRG_LEV1 (1 << 6)
/* UART FIFO trigger level 2: 8 character */
#define UART_FCR_TRG_LEV2 (2 << 6)
/* UART FIFO trigger level 3: 14 character */
#define UART_FCR_TRG_LEV3 (3 << 6)
/* UART FIFO control bit mask */
#define UART_FCR_BITMASK ((uint8_t)(0xCF))
#define UART_TX_FIFO_SIZE (16)
/**********************************************************************
* Macro defines for Macro defines for UART line control register
**********************************************************************/
/* UART 5 bit data mode */
#define UART_LCR_WLEN5 (0 << 0)
/* UART 6 bit data mode */
#define UART_LCR_WLEN6 (1 << 0)
/* UART 7 bit data mode */
#define UART_LCR_WLEN7 (2 << 0)
/* UART 8 bit data mode */
#define UART_LCR_WLEN8 (3 << 0)
/* UART One Stop Bits */
#define UART_LCR_ONE_STOPBIT (0 << 2)
/* UART Two Stop Bits */
#define UART_LCR_TWO_STOPBIT (1 << 2)
/* UART Parity Disabled / No Parity */
#define UART_LCR_NO_PARITY (0 << 3)
/* UART Parity Enable */
#define UART_LCR_PARITY_EN (1 << 3)
/* UART Odd Parity Select */
#define UART_LCR_PARITY_ODD (0 << 4)
/* UART Even Parity Select */
#define UART_LCR_PARITY_EVEN (1 << 4)
/* UART force 1 stick parity */
#define UART_LCR_PARITY_SP_1 (1 << 5)
/* UART force 0 stick parity */
#define UART_LCR_PARITY_SP_0 ((1 << 5) | (1 << 4))
/* UART Transmission Break enable */
#define UART_LCR_BREAK_EN (1 << 6)
/* UART Divisor Latches Access bit enable */
#define UART_LCR_DLAB_EN (1 << 7)
/* UART line control bit mask */
#define UART_LCR_BITMASK ((uint8_t)(0xFF))
/**********************************************************************
* Macro defines for Macro defines for UART line status register
**********************************************************************/
/* Line status register: Receive data ready */
#define UART_LSR_RDR (1 << 0)
/* Line status register: Overrun error */
#define UART_LSR_OE (1 << 1)
/* Line status register: Parity error */
#define UART_LSR_PE (1 << 2)
/* Line status register: Framing error */
#define UART_LSR_FE (1 << 3)
/* Line status register: Break interrupt */
#define UART_LSR_BI (1 << 4)
/* Line status register: Transmit holding register empty */
#define UART_LSR_THRE (1 << 5)
/* Line status register: Transmitter empty */
#define UART_LSR_TEMT (1 << 6)
/* Error in RX FIFO */
#define UART_LSR_RXFE (1 << 7)
/* UART Line status bit mask */
#define UART_LSR_BITMASK ((uint8_t)(0xFF))
#define UART_LSR_ERROR_MASK \
(UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE)
/**********************************************************************
* Macro defines for Macro defines for UART Scratch Pad Register
**********************************************************************/
/* UART Scratch Pad bit mask */
#define UART_SCR_BIMASK ((uint8_t)(0xFF))
/***********************************************************************
* Macro defines for Macro defines for UART Auto baudrate control register
**********************************************************************/
/* UART Auto-baud start */
#define UART_ACR_START (1 << 0)
/* UART Auto baudrate Mode 1 */
#define UART_ACR_MODE (1 << 1)
/* UART Auto baudrate restart */
#define UART_ACR_AUTO_RESTART (1 << 2)
/* UART End of auto-baud interrupt clear */
#define UART_ACR_ABEOINT_CLR (1 << 8)
/* UART Auto-baud time-out interrupt clear */
#define UART_ACR_ABTOINT_CLR (1 << 9)
/* UART Auto Baudrate register bit mask */
#define UART_ACR_BITMASK ((uint32_t)(0x307))
/*********************************************************************
* Macro defines for Macro defines for UART IrDA control register
**********************************************************************/
/* IrDA mode enable */
#define UART_ICR_IRDAEN (1 << 0)
/* IrDA serial input inverted */
#define UART_ICR_IRDAINV (1 << 1)
/* IrDA fixed pulse width mode */
#define UART_ICR_FIXPULSE_EN (1 << 2)
/* PulseDiv - Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3))
/* UART IRDA bit mask */
#define UART_ICR_BITMASK ((uint32_t)(0x3F))
/**********************************************************************
* Macro defines for Macro defines for UART half duplex register
**********************************************************************/
/* enable half-duplex mode*/
#define UART_HDEN_HDEN (1 << 0)
/**********************************************************************
* Macro defines for Macro defines for UART smart card interface control register
**********************************************************************/
/* enable asynchronous half-duplex smart card interface*/
#define UART_SCICTRL_SCIEN (1 << 0)
/* NACK response is inhibited*/
#define UART_SCICTRL_NACKDIS (1 << 1)
/* ISO7816-3 protocol T1 is selected*/
#define UART_SCICTRL_PROTSEL_T1 (1 << 2)
/* number of retransmission*/
#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5))
/* Extra guard time*/
#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8))
/*********************************************************************
* Macro defines for Macro defines for UART synchronous control register
**********************************************************************/
/* enable synchronous mode*/
#define UART_SYNCCTRL_SYNC (1 << 0)
/* synchronous master mode*/
#define UART_SYNCCTRL_CSRC_MASTER (1 << 1)
/* sample on falling edge*/
#define UART_SYNCCTRL_FES (1 << 2)
/* to be defined*/
#define UART_SYNCCTRL_TSBYPASS (1 << 3)
/* continuous running clock enable (master mode only) */
#define UART_SYNCCTRL_CSCEN (1 << 4)
/* Do not send start/stop bit */
#define UART_SYNCCTRL_NOSTARTSTOP (1 << 5)
/* stop continuous clock */
#define UART_SYNCCTRL_CCCLR (1 << 6)
/*********************************************************************
* Macro defines for Macro defines for UART Fractional divider register
**********************************************************************/
/* Baud-rate generation pre-scaler divisor */
#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F))
/* Baud-rate pre-scaler multiplier value */
#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0))
/* UART Fractional Divider register bit mask */
#define UART_FDR_BITMASK ((uint32_t)(0xFF))
/*********************************************************************
* Macro defines for Macro defines for UART Tx Enable register
**********************************************************************/
#define UART_TER_TXEN (1 << 0) /* Transmit enable bit */
/**********************************************************************
* Macro defines for Macro defines for UART FIFO Level register
**********************************************************************/
/* Reflects the current level of the UART receiver FIFO */
#define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F))
/* Reflects the current level of the UART transmitter FIFO */
#define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F))
/* UART FIFO Level Register bit mask */
#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F))
/*********************************************************************
* UART enum
**********************************************************************/
/*
* UART Databit type definitions
*/
typedef enum {
UART_DATABIT_5 = UART_LCR_WLEN5,/* UART 5 bit data mode */
UART_DATABIT_6 = UART_LCR_WLEN6,/* UART 6 bit data mode */
UART_DATABIT_7 = UART_LCR_WLEN7,/* UART 7 bit data mode */
UART_DATABIT_8 = UART_LCR_WLEN8/* UART 8 bit data mode */
} uart_databit_t;
/*
* UART Stop bit type definitions
*/
typedef enum {
/* UART 1 Stop Bits Select */
UART_STOPBIT_1 = UART_LCR_ONE_STOPBIT,
/* UART 2 Stop Bits Select */
UART_STOPBIT_2 = UART_LCR_TWO_STOPBIT
} uart_stopbit_t;
/*
* UART Parity type definitions
*/
typedef enum {
/* No parity */
UART_PARITY_NONE = UART_LCR_NO_PARITY,
/* Odd parity */
UART_PARITY_ODD = (UART_LCR_PARITY_ODD | UART_LCR_PARITY_EN),
/* Even parity */
UART_PARITY_EVEN = (UART_LCR_PARITY_EVEN | UART_LCR_PARITY_EN),
/* Forced 1 stick parity */
UART_PARITY_SP_1 = (UART_LCR_PARITY_SP_1 | UART_LCR_PARITY_EN),
/* Forced 0 stick parity */
UART_PARITY_SP_0 = (UART_LCR_PARITY_SP_0 | UART_LCR_PARITY_EN)
} uart_parity_t;
typedef enum {
UART0_NUM = UART0,
UART1_NUM = UART1,
UART2_NUM = UART2,
UART3_NUM = UART3
} uart_num_t;
typedef enum {
UART_NO_ERROR = 0,
UART_TIMEOUT_ERROR = 1
} uart_error_t;
typedef enum {
UART_RX_NO_DATA = 0,
UART_RX_DATA_READY = 1,
UART_RX_DATA_ERROR = 2
} uart_rx_data_ready_t;
/* function prototypes */
BEGIN_DECLS
/* Init UART and set PLL1 as clock source (PCLK) */
void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits,
uart_stopbit_t data_nb_stop, uart_parity_t data_parity,
uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval);
uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num);
uint8_t uart_read(uart_num_t uart_num);
uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles,
uart_error_t *error);
void uart_write(uart_num_t uart_num, uint8_t data);
END_DECLS
#ifdef __cplusplus
}
#endif
#endif

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/** @defgroup wwdt_defines Windowed Watchdog Timer
@brief <b>Defined Constants and Types for the LPC43xx Windowed Watchdog
Timer</b>
@ingroup LPC43xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
@date 10 March 2013
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_WWDT_H
#define LPC43XX_WWDT_H
/**@{*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/lpc43xx/memorymap.h>
#ifdef __cplusplus
extern "C" {
#endif
/* --- Windowed Watchdog Timer (WWDT) registers ---------------------------- */
/* Watchdog mode register */
#define WWDT_MOD MMIO32(WWDT_BASE + 0x000)
#define WWDT_MOD_WDEN (1<<0)
#define WWDT_MOD_WDRESET (1<<1)
#define WWDT_MOD_WDTOF (1<<2)
#define WWDT_MOD_WDINT (1<<3)
#define WWDT_MOD_WDPROTECT (1<<4)
/* Watchdog timer constant register */
#define WWDT_TC MMIO32(WWDT_BASE + 0x004)
/* Watchdog feed sequence register */
#define WWDT_FEED MMIO32(WWDT_BASE + 0x008)
#define WWDT_FEED_SEQUENCE WWDT_FEED = 0xAA; WWDT_FEED = 0x55
/* Watchdog timer value register */
#define WWDT_TV MMIO32(WWDT_BASE + 0x00C)
/* Watchdog warning interrupt register */
#define WWDT_WARNINT MMIO32(WWDT_BASE + 0x014)
/* Watchdog timer window register */
#define WWDT_WINDOW MMIO32(WWDT_BASE + 0x018)
/**@}*/
/* Reset LPC4330 in timeout*4 clock cycles (min 256, max 2^24) */
void wwdt_reset(uint32_t timeout);
#ifdef __cplusplus
}
#endif
#endif

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includeguard: LIBOPENCM3_SAM3N_NVIC_H
partname_humanreadable: Atmel SAM3N series
partname_doxygen: SAM3N
irqs:
- supc
- rstc
- rtc
- rtt
- wdg
- pmc
- eefc0
- reserved0
- uart0
- uart1
- reserved1
- pioa
- piob
- pioc
- usart0
- usart1
- reserved2
- reserved3
- reserved4
- twi0
- twi1
- spi
- reserved5
- tc0
- tc1
- tc2
- tc3
- tc4
- tc5
- adc
- dacc
- pwm

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM3N_MEMORYMAP_H
#define SAM3N_MEMORYMAP_H
#include <libopencm3/cm3/common.h>
/* --- SAM3N peripheral space -------------------------------------------- */
#define SPI_BASE (0x40008000)
#define TC0_BASE (0x40010000)
#define TC1_BASE (0x40010040)
#define TC2_BASE (0x40010080)
#define TC3_BASE (0x40014000)
#define TC4_BASE (0x40014040)
#define TC5_BASE (0x40014080)
#define TWI0_BASE (0x40018000)
#define TWI1_BASE (0x4001C000)
#define PWM_BASE (0x40020000)
#define USART0_BASE (0x40024000)
#define USART1_BASE (0x40028000)
#define ADC_BASE (0x40038000)
#define DACC_BASE (0x4003C000)
/* --- SAM3N system controller space ------------------------------------- */
#define SMC_BASE (0x400E0000)
#define MATRIX_BASE (0x400E0200)
#define PMC_BASE (0x400E0400)
#define UART0_BASE (0x400E0600)
#define CHIPID_BASE (0x400E0740)
#define UART1_BASE (0x400E0800)
#define EEFC_BASE (0x400E0A00)
#define PIOA_BASE (0x400E0E00)
#define PIOB_BASE (0x400E1000)
#define PIOC_BASE (0x400E1200)
#define RSTC_BASE (0x400E1400)
#define SUPC_BASE (0x400E1410)
#define RTT_BASE (0x400E1430)
#define WDT_BASE (0x400E1450)
#define RTC_BASE (0x400E1460)
#define GPBR_BASE (0x400E1490)
#endif

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includeguard: LIBOPENCM3_SAM3X_NVIC_H
partname_humanreadable: Atmel SAM3X series
partname_doxygen: SAM3X
irqs:
- supc
- rstc
- rtc
- rtt
- wdg
- pmc
- eefc0
- eefc1
- uart
- smc_sdramc
- sdramc
- pioa
- piob
- pioc
- piod
- pioe
- piof
- usart0
- usart1
- usart2
- usart3
- hsmci
- twi0
- twi1
- spi0
- spi1
- ssc
- tc0
- tc1
- tc2
- tc3
- tc4
- tc5
- tc6
- tc7
- tc8
- pwm
- adc
- dacc
- dmac
- uotghs
- trng
- emac
- can0
- can1

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM3X_MEMORYMAP_H
#define SAM3X_MEMORYMAP_H
#include <libopencm3/cm3/common.h>
/* --- SAM3X peripheral space -------------------------------------------- */
#define HSMCI_BASE (0x40000000)
#define SSC_BASE (0x40004000)
#define SPI0_BASE (0x40008000)
#define SPI1_BASE (0x4000C000)
#define TC0_BASE (0x40080000)
#define TC1_BASE (0x40080040)
#define TC2_BASE (0x40080080)
#define TC3_BASE (0x40084000)
#define TC4_BASE (0x40084040)
#define TC5_BASE (0x40084080)
#define TC6_BASE (0x40088000)
#define TC7_BASE (0x40088040)
#define TC8_BASE (0x40088080)
#define TWI0_BASE (0x4008C000)
#define TWI1_BASE (0x40090000)
#define PWM_BASE (0x40094000)
#define USART0_BASE (0x40098000)
#define USART1_BASE (0x4009C000)
#define USART2_BASE (0x400A0000)
#define USART3_BASE (0x400A4000)
#define UOTGHS_BASE (0x400AC000)
#define EMAC_BASE (0x400B0000)
#define CAN0_BASE (0x400B4000)
#define CAN1_BASE (0x400B8000)
#define TRNG_BASE (0x400BC000)
#define ADC_BASE (0x400C0000)
#define DMAC_BASE (0x400C4000)
/* --- SAM3X system controller space ------------------------------------- */
#define SMC_BASE (0x400E0000)
#define SDRAM_BASE (0x400E0200)
#define MATRIX_BASE (0x400E0400)
#define PMC_BASE (0x400E0600)
#define UART_BASE (0x400E0800)
#define CHIPID_BASE (0x400E0940)
#define EEFC0_BASE (0x400E0A00)
#define EEFC1_BASE (0x400E0C00)
#define PIOA_BASE (0x400E0E00)
#define PIOB_BASE (0x400E1000)
#define PIOC_BASE (0x400E1200)
#define PIOD_BASE (0x400E1400)
#define PIOE_BASE (0x400E1600)
#define PIOF_BASE (0x400E1800)
#define RSTC_BASE (0x400E1A00)
#define SUPC_BASE (0x400E1A10)
#define RTT_BASE (0x400E1A30)
#define WDT_BASE (0x400E1A50)
#define RTC_BASE (0x400E1A60)
#define GPBR_BASE (0x400E1A90)
#define RTC_BASE (0x400E1A60)
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM3X_EEFC_H
#define SAM3X_EEFC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/sam/memorymap.h>
/* --- Convenience macros ------------------------------------------------ */
#define EEFC EEFC_BASE
#define EEFC0 EEFC0_BASE
#define EEFC1 EEFC1_BASE
/* --- Enhanced Embedded Flash Controller (EEFC) registers --------------- */
#define EEFC_FMR(port) MMIO32((port) + 0x00)
#define EEFC_FCR(port) MMIO32((port) + 0x04)
#define EEFC_FSR(port) MMIO32((port) + 0x08)
#define EEFC_FRR(port) MMIO32((port) + 0x0C)
/* 0x0010 - Reserved */
/* EEFC Flash Mode Register (EEFC_FMR) */
/* Bit [31:25] - Reserved */
#define EEFC_FMR_FAM (0x01 << 24)
/* Bit [23:12] - Reserved */
#define EEFC_FMR_FWS_MASK (0x0F << 8)
/* Bit [7:1] - Reserved */
#define EEFC_FMR_FRDY (0x01 << 0)
/* EEFC Flash Command Register (EEFC_FCR) */
#define EEFC_FCR_FKEY (0x5A << 24)
#define EEFC_FCR_FARG_MASK (0xFFFF << 8)
#define EEFC_FCR_FCMD_MASK (0xFF << 0)
#define EEFC_FCR_FCMD_GETD (0x00 << 0)
#define EEFC_FCR_FCMD_WP (0x01 << 0)
#define EEFC_FCR_FCMD_WPL (0x02 << 0)
#define EEFC_FCR_FCMD_EWP (0x03 << 0)
#define EEFC_FCR_FCMD_EWPL (0x04 << 0)
#define EEFC_FCR_FCMD_EA (0x05 << 0)
#define EEFC_FCR_FCMD_SLB (0x08 << 0)
#define EEFC_FCR_FCMD_CLB (0x09 << 0)
#define EEFC_FCR_FCMD_GLB (0x0A << 0)
#define EEFC_FCR_FCMD_SGPB (0x0B << 0)
#define EEFC_FCR_FCMD_CGPB (0x0C << 0)
#define EEFC_FCR_FCMD_GGPB (0x0D << 0)
#define EEFC_FCR_FCMD_STUI (0x0E << 0)
#define EEFC_FCR_FCMD_SPUI (0x0F << 0)
/* EEFC Flash Status Register (EEFC_FSR) */
/* Bit [31:3] - Reserved */
#define EEFC_FSR_FLOCKE (0x01 << 2)
#define EEFC_FSR_FCMDE (0x01 << 1)
#define EEFC_FSR_FRDY (0x01 << 0)
static inline void eefc_set_latency(uint8_t wait)
{
#if defined(SAM3X)
EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
EEFC_FMR(EEFC1) = (EEFC_FMR(EEFC1) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
#elif defined(SAM3N)
EEFC_FMR(EEFC) = (EEFC_FMR(EEFC) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
#endif
}
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM3X_GPIO_H
#define SAM3X_GPIO_H
#include <libopencm3/sam/pio.h>
/* flags may be or'd together, but only contain one of
* GPOUTPUT, PERIPHA and PERIPHB */
enum gpio_flags {
GPIO_FLAG_GPINPUT = 0,
GPIO_FLAG_GPOUTPUT = 1,
GPIO_FLAG_PERIPHA = 2,
GPIO_FLAG_PERIPHB = 3,
GPIO_FLAG_OPEN_DRAIN = 4,
GPIO_FLAG_PULL_UP = 8,
};
void gpio_init(uint32_t gpioport, uint32_t pins, enum gpio_flags flags);
static inline void gpio_set(uint32_t gpioport, uint32_t gpios)
{
PIO_SODR(gpioport) = gpios;
}
static inline void gpio_clear(uint32_t gpioport, uint32_t gpios)
{
PIO_CODR(gpioport) = gpios;
}
void gpio_toggle(uint32_t gpioport, uint32_t gpios);
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM_MEMORYMAP_H
#define SAM_MEMORYMAP_H
#if defined(SAM3X)
# include <libopencm3/sam/3x/memorymap.h>
#elif defined(SAM3N)
# include <libopencm3/sam/3n/memorymap.h>
#else
# error "Processor family not defined."
#endif
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM_PIO_H
#define SAM_PIO_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/sam/memorymap.h>
/* --- Convenience macros ------------------------------------------------ */
/* GPIO port base addresses (for convenience) */
#define PIOA PIOA_BASE
#define PIOB PIOB_BASE
#define PIOC PIOC_BASE
#define PIOD PIOD_BASE
#define PIOE PIOE_BASE
#define PIOF PIOF_BASE
#define PIOG PIOG_BASE
#define PIOH PIOH_BASE
/* --- PIO registers ----------------------------------------------------- */
#define PIO_PER(port) MMIO32((port) + 0x0000)
#define PIO_PDR(port) MMIO32((port) + 0x0004)
#define PIO_PSR(port) MMIO32((port) + 0x0008)
/* 0x000C - Reserved */
#define PIO_OER(port) MMIO32((port) + 0x0010)
#define PIO_ODR(port) MMIO32((port) + 0x0014)
#define PIO_OSR(port) MMIO32((port) + 0x0018)
/* 0x001C - Reserved */
#define PIO_IFER(port) MMIO32((port) + 0x0020)
#define PIO_IFDR(port) MMIO32((port) + 0x0024)
#define PIO_IFSR(port) MMIO32((port) + 0x0028)
/* 0x002C - Reserved */
#define PIO_SODR(port) MMIO32((port) + 0x0030)
#define PIO_CODR(port) MMIO32((port) + 0x0034)
#define PIO_ODSR(port) MMIO32((port) + 0x0038)
#define PIO_PDSR(port) MMIO32((port) + 0x003C)
#define PIO_IER(port) MMIO32((port) + 0x0040)
#define PIO_IDR(port) MMIO32((port) + 0x0044)
#define PIO_IMR(port) MMIO32((port) + 0x0048)
#define PIO_ISR(port) MMIO32((port) + 0x004C)
#define PIO_MDER(port) MMIO32((port) + 0x0050)
#define PIO_MDDR(port) MMIO32((port) + 0x0054)
#define PIO_MDSR(port) MMIO32((port) + 0x0058)
/* 0x005C - Reserved */
#define PIO_PUDR(port) MMIO32((port) + 0x0060)
#define PIO_PUER(port) MMIO32((port) + 0x0064)
#define PIO_PUSR(port) MMIO32((port) + 0x0068)
/* 0x006C - Reserved */
#define PIO_ABSR(port) MMIO32((port) + 0x0070)
/* 0x0074-0x007C - Reserved */
#define PIO_SCIFSR(port) MMIO32((port) + 0x0080)
#define PIO_DIFSR(port) MMIO32((port) + 0x0084)
#define PIO_IFDGSR(port) MMIO32((port) + 0x0088)
#define PIO_SCDR(port) MMIO32((port) + 0x008C)
/* 0x0090-0x009C - Reserved */
#define PIO_OWER(port) MMIO32((port) + 0x00A0)
#define PIO_OWDR(port) MMIO32((port) + 0x00A4)
#define PIO_OWSR(port) MMIO32((port) + 0x00A8)
/* 0x00AC - Reserved */
#define PIO_AIMER(port) MMIO32((port) + 0x00B0)
#define PIO_AIMDR(port) MMIO32((port) + 0x00B4)
#define PIO_AIMMR(port) MMIO32((port) + 0x00B8)
/* 0x00BC - Reserved */
#define PIO_ESR(port) MMIO32((port) + 0x00C0)
#define PIO_LSR(port) MMIO32((port) + 0x00C4)
#define PIO_ELSR(port) MMIO32((port) + 0x00C8)
/* 0x00CC - Reserved */
#define PIO_FELLSR(port) MMIO32((port) + 0x00D0)
#define PIO_REHLSR(port) MMIO32((port) + 0x00D4)
#define PIO_FRLHSR(port) MMIO32((port) + 0x00D8)
/* 0x00DC - Reserved */
#define PIO_LOCKSR(port) MMIO32((port) + 0x00E0)
#define PIO_WPMR(port) MMIO32((port) + 0x00E4)
#define PIO_WPSR(port) MMIO32((port) + 0x00E8)
/* 0x00EC-0x0144 - Reserved */
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM3X_PMC_H
#define SAM3X_PMC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/sam/memorymap.h>
/* --- Power Management Controller (PMC) registers ----------------------- */
#define PMC_SCER MMIO32(PMC_BASE + 0x0000)
#define PMC_SCDR MMIO32(PMC_BASE + 0x0004)
#define PMC_SCSR MMIO32(PMC_BASE + 0x0008)
/* 0x000C - Reserved */
#define PMC_PCER0 MMIO32(PMC_BASE + 0x0010)
#define PMC_PCDR0 MMIO32(PMC_BASE + 0x0014)
#define PMC_PCSR0 MMIO32(PMC_BASE + 0x0018)
#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C)
#define CKGR_MOR MMIO32(PMC_BASE + 0x0020)
#define CKGR_MCFR MMIO32(PMC_BASE + 0x0024)
#define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028)
/* 0x002C - Reserved */
#define PMC_MCKR MMIO32(PMC_BASE + 0x0030)
/* 0x0034 - Reserved */
#define PMC_USB MMIO32(PMC_BASE + 0x0038)
/* 0x003C - Reserved */
#define PMC_PCK0 MMIO32(PMC_BASE + 0x0040)
#define PMC_PCK1 MMIO32(PMC_BASE + 0x0044)
#define PMC_PCK2 MMIO32(PMC_BASE + 0x0048)
/* 0x004C-0x005C - Reserved */
#define PMC_IER MMIO32(PMC_BASE + 0x0060)
#define PMC_IDR MMIO32(PMC_BASE + 0x0064)
#define PMC_SR MMIO32(PMC_BASE + 0x0068)
#define PMC_IMR MMIO32(PMC_BASE + 0x006C)
#define PMC_FSMR MMIO32(PMC_BASE + 0x0070)
#define PMC_FSPR MMIO32(PMC_BASE + 0x0074)
#define PMC_FOCR MMIO32(PMC_BASE + 0x0078)
/* 0x007C-0x00E0 - Reserved */
#define PMC_WPMR MMIO32(PMC_BASE + 0x00E4)
#define PMC_WPSR MMIO32(PMC_BASE + 0x00E8)
/* 0x00EC-0x00FC - Reserved */
#define PMC_PCER1 MMIO32(PMC_BASE + 0x0100)
#define PMC_PCDR1 MMIO32(PMC_BASE + 0x0104)
#define PMC_PCSR1 MMIO32(PMC_BASE + 0x0108)
#define PMC_PCR MMIO32(PMC_BASE + 0x010C)
/* PMC UTMI Clock Configuration Register (CKGR_UCKR) */
/* Bit [31:22] - Reserved */
#define CKGR_CKGR_UPLLCOUNT_MASK (0x0F << 20)
/* Bit [19:17] - Reserved */
#define CKGR_CKGR_UPLLEN (0x01 << 16)
/* Bit [15:0] - Reserved */
/* PMC Clock Generator Main Oscillator Register (CKGR_MOR) */
/* Bit [31:26] - Reserved */
#define CKGR_MOR_CFDEN (0x01 << 25)
#define CKGR_MOR_MOSCSEL (0x01 << 24)
#define CKGR_MOR_KEY (0x37 << 16)
#define CKGR_MOR_MOSCXTST_MASK (0xFF << 8)
/* Bit 7 - Reserved */
#define CKGR_MOR_MOSCRCF_MASK (0x07 << 4)
#define CKGR_MOR_MOSCRCEN (0x01 << 3)
/* Bit 2 - Reserved */
#define CKGR_MOR_MOSCXTBY (0x01 << 1)
#define CKGR_MOR_MOSCXTEN (0x01 << 0)
/* PMC Clock Generator PLLA Register (CKGR_PLLAR) */
#define CKGR_PLLAR_ONE (0x01 << 29)
#define CKGR_PLLAR_MULA_MASK (0x7FF << 16)
#define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << 8)
#define CKGR_PLLAR_DIVA_MASK (0xFF << 0)
/* PMC Master Clock Register (PMC_MCKR) */
/* Bit [31:14] - Reserved */
#define PMC_MCKR_UPLLDIV2 (0x01 << 13)
#define PMC_MCKR_PLLADIV2 (0x01 << 12)
/* Bit [11:7] - Reserved */
#define PMC_MCKR_PRES_MASK (0x07 << 4)
/* Bit [3:2] - Reserved */
#define PMC_MCKR_CSS_MASK (0x03 << 0)
#define PMC_MCKR_CSS_SLOW_CLK (0x00 << 0)
#define PMC_MCKR_CSS_MAIN_CLK (0x01 << 0)
#define PMC_MCKR_CSS_PLLA_CLK (0x02 << 0)
#define PMC_MCKR_CSS_UPLL_CLK (0x03 << 0)
/* PMC USB Clock Register (PMC_USB) */
/* Bit [31:12] - Reserved */
#define PMC_USB_USBDIV_MASK (0x0F << 8)
/* Bit [7:1] - Reserved */
#define PMC_USB_USBS (0x01 << 0)
/* PMC Status Register (PMC_SR) */
/* Bits [31:21] - Reserved */
#define PMC_SR_FOS (0x01 << 20)
#define PMC_SR_CFDS (0x01 << 19)
#define PMC_SR_CFDEV (0x01 << 18)
#define PMC_SR_MOSCRCS (0x01 << 17)
#define PMC_SR_MOSCSELS (0x01 << 16)
/* Bits [15:11] - Reserved */
#define PMC_SR_PCKRDY2 (0x01 << 10)
#define PMC_SR_PCKRDY1 (0x01 << 9)
#define PMC_SR_PCKRDY0 (0x01 << 8)
#define PMC_SR_OSCSELS (0x01 << 7)
#define PMC_SR_LOCKU (0x01 << 6)
/* Bits [5:4] - Reserved */
#define PMC_SR_MCKRDY (0x01 << 3)
/* Bit [2] - Reserved */
#define PMC_SR_LOCKA (0x01 << 1)
#define PMC_SR_MOSCXTS (0x01 << 0)
extern uint32_t pmc_mck_frequency;
enum mck_src {
MCK_SRC_SLOW = 0,
MCK_SRC_MAIN = 1,
MCK_SRC_PLLA = 2,
MCK_SRC_UPLL = 3,
};
void pmc_mck_set_source(enum mck_src src);
void pmc_xtal_enable(bool en, uint8_t startup_time);
void pmc_plla_config(uint8_t mul, uint8_t div);
void pmc_peripheral_clock_enable(uint8_t pid);
void pmc_peripheral_clock_disable(uint8_t pid);
void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void);
void pmc_clock_setup_in_rc_4mhz_out_84mhz(void);
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM3X_PWM_H
#define SAM3X_PWM_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/sam/memorymap.h>
/* --- Pulse Width Modulation (PWM) registers ----------------------- */
#define PWM_CLK MMIO32(PWM_BASE + 0x0000)
#define PWM_ENA MMIO32(PWM_BASE + 0x0004)
#define PWM_DIS MMIO32(PWM_BASE + 0x0008)
#define PWM_SR MMIO32(PWM_BASE + 0x000C)
#define PWM_IER1 MMIO32(PWM_BASE + 0x0010)
#define PWM_IDR1 MMIO32(PWM_BASE + 0x0014)
#define PWM_IMR1 MMIO32(PWM_BASE + 0x0018)
#define PWM_ISR1 MMIO32(PWM_BASE + 0x001C)
#define PWM_SCM MMIO32(PWM_BASE + 0x0020)
/* 0x0024 - Reserved */
#define PWM_SCUC MMIO32(PWM_BASE + 0x0028)
#define PWM_SCUP MMIO32(PWM_BASE + 0x002C)
#define PWM_SCUPUPD MMIO32(PWM_BASE + 0x0030)
#define PWM_IER2 MMIO32(PWM_BASE + 0x0034)
#define PWM_IDR2 MMIO32(PWM_BASE + 0x0038)
#define PWM_IMR2 MMIO32(PWM_BASE + 0x003C)
#define PWM_ISR2 MMIO32(PWM_BASE + 0x0040)
#define PWM_OOV MMIO32(PWM_BASE + 0x0044)
#define PWM_OS MMIO32(PWM_BASE + 0x0048)
#define PWM_OSS MMIO32(PWM_BASE + 0x004C)
#define PWM_OSC MMIO32(PWM_BASE + 0x0050)
#define PWM_OSSUPD MMIO32(PWM_BASE + 0x0054)
#define PWM_OSCUPD MMIO32(PWM_BASE + 0x0058)
#define PWM_FMR MMIO32(PWM_BASE + 0x005C)
#define PWM_FSR MMIO32(PWM_BASE + 0x0060)
#define PWM_FCR MMIO32(PWM_BASE + 0x0064)
#define PWM_FPV MMIO32(PWM_BASE + 0x0068)
#define PWM_FPE1 MMIO32(PWM_BASE + 0x006C)
#define PWM_FPE2 MMIO32(PWM_BASE + 0x0070)
/* 0x0074:0x0078 - Reserved */
#define PWM_ELMR0 MMIO32(PWM_BASE + 0x007C)
#define PWM_ELMR1 MMIO32(PWM_BASE + 0x0080)
/* 0x0084:0x00AC - Reserved */
#define PWM_SMMR MMIO32(PWM_BASE + 0x00B0)
/* 0x00B4:0x00E0 - Reserved */
#define PWM_WPCR MMIO32(PWM_BASE + 0x00E4)
#define PWM_WPSR MMIO32(PWM_BASE + 0x00E8)
/* 0x00EC:0x00FC - Reserved */
/* 0x0100:0x012C - Reserved */
#define PWM_CMPV(x) MMIO32(PWM_BASE + 0x0130 + 0x10*(x))
#define PWM_CMPVUPD(x) MMIO32(PWM_BASE + 0x0134 + 0x10*(x))
#define PWM_CMMV(x) MMIO32(PWM_BASE + 0x0138 + 0x10*(x))
#define PWM_CMMVUPD(x) MMIO32(PWM_BASE + 0x013C + 0x10*(x))
/* 0x01B0:0x01FC - Reserved */
#define PWM_CMR(x) MMIO32(PWM_BASE + 0x0200 + 0x20*(x))
#define PWM_CDTY(x) MMIO32(PWM_BASE + 0x0204 + 0x20*(x))
#if defined(SAM3X)
# define PWM_CDTYUPD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x))
# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x))
# define PWM_CPRDUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x))
# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x0214 + 0x20*(x))
# define PWM_DT(x) MMIO32(PWM_BASE + 0x0218 + 0x20*(x))
# define PWM_DTUPD(x) MMIO32(PWM_BASE + 0x021C + 0x20*(x))
#elif defined(SAM3N)
# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x))
# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x))
# define PWM_CUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x))
#else
# error "Processor family not defined."
#endif
static inline void pwm_set_period(int ch, uint32_t period)
{
PWM_CPRD(ch) = period;
}
static inline void pwm_set_duty(int ch, uint32_t duty)
{
PWM_CDTY(ch) = duty;
}
static inline void pwm_enable(int ch)
{
PWM_ENA = 1 << ch;
}
static inline void pwm_disable(int ch)
{
PWM_DIS = 1 << ch;
}
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM3X_TC_H
#define SAM3X_TC_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/sam/memorymap.h>
/* --- Timer Counter (TC) registers -------------------------------------- */
#define TC_CCR(x) MMIO32(TC_BASE + 0x00 + 0x40*(x))
#define TC_CMR(x) MMIO32(TC_BASE + 0x04 + 0x40*(x))
#define TC_SMMR(x) MMIO32(TC_BASE + 0x08 + 0x40*(x))
/* 0x0C + 0x40*channel - Reserved */
#define TC_CV(x) MMIO32(TC_BASE + 0x10 + 0x40*(x))
#define TC_RA(x) MMIO32(TC_BASE + 0x14 + 0x40*(x))
#define TC_RB(x) MMIO32(TC_BASE + 0x18 + 0x40*(x))
#define TC_RC(x) MMIO32(TC_BASE + 0x1C + 0x40*(x))
#define TC_SR(x) MMIO32(TC_BASE + 0x20 + 0x40*(x))
#define TC_IER(x) MMIO32(TC_BASE + 0x24 + 0x40*(x))
#define TC_IDR(x) MMIO32(TC_BASE + 0x28 + 0x40*(x))
#define TC_IMR(x) MMIO32(TC_BASE + 0x2C + 0x40*(x))
#define TC_BCR MMIO32(TC_BASE + 0xC0)
#define TC_BMR MMIO32(TC_BASE + 0xC4)
#define TC_QIER MMIO32(TC_BASE + 0xC8)
#define TC_QIDR MMIO32(TC_BASE + 0xCC)
#define TC_QIMR MMIO32(TC_BASE + 0xD0)
#define TC_QISR MMIO32(TC_BASE + 0xD4)
#define TC_FMR MMIO32(TC_BASE + 0xD8)
/* 0x00DC:0x00E0 - Undocumented */
#define TC_WPMR MMIO32(TC_BASE + 0xE4)
/* 0x00E8:0x00F8 - Undocumented */
/* 0x00FC - Reserved */
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM3X_UART_H
#define SAM3X_UART_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/sam/memorymap.h>
/* --- Universal Asynchronous Receiver Transmitter (UART) registers ------- */
#define UART_CR MMIO32(UART_BASE + 0x0000)
#define UART_MR MMIO32(UART_BASE + 0x0004)
#define UART_IER MMIO32(UART_BASE + 0x0008)
#define UART_IDR MMIO32(UART_BASE + 0x000C)
#define UART_IMR MMIO32(UART_BASE + 0x0010)
#define UART_SR MMIO32(UART_BASE + 0x0014)
#define UART_RHR MMIO32(UART_BASE + 0x0018)
#define UART_THR MMIO32(UART_BASE + 0x001C)
#define UART_BRGR MMIO32(UART_BASE + 0x0020)
/* 0x0024:0x003C - Reserved */
/* 0x004C:0x00FC - Reserved */
/* 0x0100:0x0124 - PDC Area */
/* UART Control Register (UART_CR) */
/* Bits [31:9] - Reserved */
#define UART_CR_RSTSTA (0x01 << 8)
#define UART_CR_TXDIS (0x01 << 7)
#define UART_CR_TXEN (0x01 << 6)
#define UART_CR_RXDIS (0x01 << 5)
#define UART_CR_RXEN (0x01 << 4)
#define UART_CR_RSTTX (0x01 << 3)
#define UART_CR_RSTRX (0x01 << 2)
/* Bit [1:0] - Reserved */
/* UART Mode Register (UART_MR) */
/* Bits [31:16] - Reserved */
#define UART_MR_CHMODE_MASK (0x03 << 14)
#define UART_MR_CHMODE_NORMAL (0x00 << 14)
#define UART_MR_CHMODE_AUTOMATIC (0x01 << 14)
#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14)
#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14)
/* Bits [13:12] - Reserved */
#define UART_MR_PAR_MASK (0x07 << 9)
#define UART_MR_PAR_EVEN (0x00 << 9)
#define UART_MR_PAR_ODD (0x01 << 9)
#define UART_MR_PAR_SPACE (0x02 << 9)
#define UART_MR_PAR_MARK (0x03 << 9)
#define UART_MR_PAR_NO (0x04 << 9)
/* Bits [8:0] - Reserved */
/* UART Status Register (UART_SR) */
/* Bits [31:13] - Reserved */
#define UART_SR_RXBUFF (0x01 << 12)
#define UART_SR_TXBUFF (0x01 << 11)
/* Bit [10] - Reserved */
#define UART_SR_TXEMPTY (0x01 << 9)
/* Bit [8] - Reserved */
#define UART_SR_PARE (0x01 << 7)
#define UART_SR_FRAME (0x01 << 6)
#define UART_SR_OVRE (0x01 << 5)
#define UART_SR_ENDTX (0x01 << 4)
#define UART_SR_ENDRX (0x01 << 3)
/* Bit [2] - Reserved */
#define UART_SR_TXRDY (0x01 << 1)
#define UART_SR_RXRDY (0x01 << 0)
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM3X_USART_H
#define SAM3X_USART_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/sam/memorymap.h>
#define USART0 USART0_BASE
#define USART1 USART1_BASE
#define USART2 USART2_BASE
#define USART3 USART3_BASE
/* --- Universal Synchronous Asynchronous Receiver Transmitter (USART) */
#define USART_CR(x) MMIO32((x) + 0x0000)
#define USART_MR(x) MMIO32((x) + 0x0004)
#define USART_IER(x) MMIO32((x) + 0x0008)
#define USART_IDR(x) MMIO32((x) + 0x000C)
#define USART_IMR(x) MMIO32((x) + 0x0010)
#define USART_CSR(x) MMIO32((x) + 0x0014)
#define USART_RHR(x) MMIO32((x) + 0x0018)
#define USART_THR(x) MMIO32((x) + 0x001C)
#define USART_BRGR(x) MMIO32((x) + 0x0020)
#define USART_RTOR(x) MMIO32((x) + 0x0024)
#define USART_TTGR(x) MMIO32((x) + 0x0028)
/* 0x002C:0x003C - Reserved */
#define USART_FIDI(x) MMIO32((x) + 0x0040)
#define USART_NER(x) MMIO32((x) + 0x0044)
#define USART_NER(x) MMIO32((x) + 0x0044)
/* 0x0048 - Reserved */
#define USART_IF(x) MMIO32((x) + 0x004C)
#define USART_MAN(x) MMIO32((x) + 0x0050)
#define USART_LINMR(x) MMIO32((x) + 0x0054)
#define USART_LINIR(x) MMIO32((x) + 0x0058)
/* 0x005C:0x00E0 - Reserved */
#define USART_WPMR(x) MMIO32((x) + 0x00E4)
#define USART_WPSR(x) MMIO32((x) + 0x00E8)
/* 0x00EC:0x00F8 - Reserved */
#define USART_VERSION(x) MMIO32((x) + 0x00FC)
/* 0x0100:0x0124 - PDC Area */
/* USART Control Register (USART_CR) */
/* Bits [31:22] - Reserved */
#define USART_CR_LINWKUP (0x01 << 21)
#define USART_CR_LINABT (0x01 << 20)
#define USART_CR_RTSDIS (0x01 << 19)
#define USART_CR_RCS (0x01 << 19)
#define USART_CR_RTSEN (0x01 << 18)
#define USART_CR_FCS (0x01 << 18)
/* Bits [17:16] - Reserved */
#define USART_CR_RETTO (0x01 << 15)
#define USART_CR_RSTNACK (0x01 << 14)
#define USART_CR_RSTIT (0x01 << 13)
#define USART_CR_SENDA (0x01 << 12)
#define USART_CR_STTTO (0x01 << 11)
#define USART_CR_STPBRK (0x01 << 10)
#define USART_CR_STTBRK (0x01 << 9)
#define USART_CR_RSTSTA (0x01 << 8)
#define USART_CR_TXDIS (0x01 << 7)
#define USART_CR_TXEN (0x01 << 6)
#define USART_CR_RXDIS (0x01 << 5)
#define USART_CR_RXEN (0x01 << 4)
#define USART_CR_RSTTX (0x01 << 3)
#define USART_CR_RSTRX (0x01 << 2)
/* Bits [1:0] - Reserved */
/* USART Mode Register (USART_MR) */
#define USART_MR_ONEBIT (0x01 << 31)
#define USART_MR_MODSYNC (0x01 << 30)
#define USART_MR_MAN (0x01 << 29)
#define USART_MR_FILTER (0x01 << 28)
/* Bit [27] - Reserved */
#define USART_MR_MAX_ITERATION_MASK (0x07 << 24)
#define USART_MR_INVDATA (0x01 << 23)
#define USART_MR_VAR_SYNC (0x01 << 22)
#define USART_MR_DSNACK (0x01 << 21)
#define USART_MR_INACK (0x01 << 20)
#define USART_MR_OVER (0x01 << 19)
#define USART_MR_CLKO (0x01 << 18)
#define USART_MR_MODE9 (0x01 << 17)
#define USART_MR_MSBF (0x01 << 16)
#define USART_MR_CPOL (0x01 << 16)
#define USART_MR_CHMODE_MASK (0x03 << 14)
#define USART_MR_CHMODE_NORMAL (0x00 << 14)
#define USART_MR_CHMODE_AUTOMATIC (0x01 << 14)
#define USART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14)
#define USART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14)
#define USART_MR_NBSTOP_MASK (0x03 << 12)
#define USART_MR_NBSTOP_1_BIT (0x00 << 12)
#define USART_MR_NBSTOP_1_5_BIT (0x01 << 12)
#define USART_MR_NBSTOP_2_BIT (0x02 << 12)
/* Bits [13:12] - Reserved */
#define USART_MR_PAR_MASK (0x07 << 9)
#define USART_MR_PAR_EVEN (0x00 << 9)
#define USART_MR_PAR_ODD (0x01 << 9)
#define USART_MR_PAR_SPACE (0x02 << 9)
#define USART_MR_PAR_MARK (0x03 << 9)
#define USART_MR_PAR_NO (0x04 << 9)
/* Bits [8:0] - Reserved */
#define USART_MR_SYNC (0x01 << 8)
#define USART_MR_CPHA (0x01 << 8)
#define USART_MR_CHRL_MASK (0x03 << 6)
#define USART_MR_CHRL_5BIT (0x00 << 6)
#define USART_MR_CHRL_6BIT (0x01 << 6)
#define USART_MR_CHRL_7BIT (0x02 << 6)
#define USART_MR_CHRL_8BIT (0x03 << 6)
#define USART_MR_USCLKS_MASK (0x03 << 4)
#define USART_MR_USCLKS_MCK (0x00 << 4)
#define USART_MR_USCLKS_DIV (0x01 << 4)
#define USART_MR_USCLKS_SCK (0x03 << 4)
#define USART_MR_MODE_MASK (0x0F << 0)
#define USART_MR_MODE_NORMAL (0x00 << 0)
#define USART_MR_MODE_RS485 (0x01 << 0)
#define USART_MR_MODE_HW_HANDSHAKING (0x02 << 0)
#define USART_MR_MODE_ISO7816_T_0 (0x03 << 0)
#define USART_MR_MODE_ISO7816_T_1 (0x04 << 0)
#define USART_MR_MODE_IRDA (0x06 << 0)
#define USART_MR_MODE_LIN_MASTER (0x0A << 0)
#define USART_MR_MODE_LIN_SLAVE (0x0B << 0)
#define USART_MR_MODE_SPI_MASTER (0x0E << 0)
#define USART_MR_MODE_SPI_SLAVE (0x0F << 0)
/* USART Status Register (USART_CSR) */
/* Bits [31:30] - Reserved */
#define USART_CSR_LINSNRE (0x01 << 29)
#define USART_CSR_LINCE (0x01 << 28)
#define USART_CSR_LINIPE (0x01 << 27)
#define USART_CSR_LINSFE (0x01 << 26)
#define USART_CSR_LINBE (0x01 << 25)
#define USART_CSR_MANERR (0x01 << 24)
#define USART_CSR_CTS (0x01 << 23)
#define USART_CSR_LINBLS (0x01 << 23)
/* Bits [22:20] - Reserved */
#define USART_CSR_CTSIC (0x01 << 19)
/* Bits [18:16] - Reserved */
#define USART_CSR_LINTC (0x01 << 15)
#define USART_CSR_LINID (0x01 << 14)
#define USART_CSR_NACK (0x01 << 13)
#define USART_CSR_LINBK (0x01 << 13)
#define USART_CSR_RXBUFF (0x01 << 12)
#define USART_CSR_TXBUFE (0x01 << 11)
/* Bit [10] - Reserved */
#define USART_CSR_TXEMPTY (0x01 << 9)
/* Bit [8] - Reserved */
#define USART_CSR_PARE (0x01 << 7)
#define USART_CSR_FRAME (0x01 << 6)
#define USART_CSR_OVRE (0x01 << 5)
#define USART_CSR_ENDTX (0x01 << 4)
#define USART_CSR_ENDRX (0x01 << 3)
/* Bit [2] - Reserved */
#define USART_CSR_TXRDY (0x01 << 1)
#define USART_CSR_RXRDY (0x01 << 0)
enum usart_stopbits {
USART_STOPBITS_1,
USART_STOPBITS_1_5,
USART_STOPBITS_2,
};
enum usart_parity {
USART_PARITY_EVEN,
USART_PARITY_ODD,
USART_PARITY_SPACE,
USART_PARITY_MARK,
USART_PARITY_NONE,
USART_PARITY_MULTIDROP,
};
enum usart_mode {
USART_MODE_DISABLED,
USART_MODE_RX,
USART_MODE_TX,
USART_MODE_TX_RX,
};
enum usart_flowcontrol {
USART_FLOWCONTROL_NONE,
USART_FLOWCONTROL_RTS_CTS,
};
void usart_set_baudrate(uint32_t usart, uint32_t baud);
void usart_set_databits(uint32_t usart, int bits);
void usart_set_stopbits(uint32_t usart, enum usart_stopbits);
void usart_set_parity(uint32_t usart, enum usart_parity);
void usart_set_mode(uint32_t usart, enum usart_mode);
void usart_set_flow_control(uint32_t usart, enum usart_flowcontrol);
void usart_enable(uint32_t usart);
void usart_disable(uint32_t usart);
void usart_send(uint32_t usart, uint16_t data);
uint16_t usart_recv(uint32_t usart);
void usart_wait_send_ready(uint32_t usart);
void usart_wait_recv_ready(uint32_t usart);
void usart_send_blocking(uint32_t usart, uint16_t data);
uint16_t usart_recv_blocking(uint32_t usart);
void usart_enable_rx_interrupt(uint32_t usart);
void usart_disable_rx_interrupt(uint32_t usart);
#endif

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SAM3X_WDT_H
#define SAM3X_WDT_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/sam/memorymap.h>
/* --- WDT registers ----------------------------------------------------- */
#define WDT_CR MMIO32(WDT_BASE + 0x00)
#define WDT_MR MMIO32(WDT_BASE + 0x04)
#define WDT_SR MMIO32(WDT_BASE + 0x08)
/* --- WDT_CR values ------------------------------------------------------ */
#define WDT_CR_KEY (0xA5 << 24)
/* Bits [23:1]: Reserved. */
#define WDT_CR_WDRSTT (1 << 0)
/* --- WDT_MR values ------------------------------------------------------ */
/* Bits [31:32]: Reserved. */
#define WDT_MR_WDIDLEHLT (1 << 29)
#define WDT_MR_WDDBGHLT (1 << 28)
#define WDT_MR_WDD_MASK (0xFFF << 16)
#define WDT_MR_WDDIS (1 << 15)
#define WDT_MR_WDRPROC (1 << 14)
#define WDT_MR_WDRSTEN (1 << 13)
#define WDT_MR_WDFIEN (1 << 12)
#define WDT_MR_WDV_MASK (0xFFF << 0)
/* --- WDT_SR values ------------------------------------------------------ */
/* Bits [31:2]: Reserved. */
#define WDT_SR_WDERR (1 << 1)
#define WDT_SR_WDUNF (1 << 0)
#endif

31
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/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(STM32F0)
# include <libopencm3/stm32/f0/adc.h>
#elif defined(STM32F1)
# include <libopencm3/stm32/f1/adc.h>
#elif defined(STM32F3)
# include <libopencm3/stm32/f3/adc.h>
#elif defined(STM32F4)
# include <libopencm3/stm32/f4/adc.h>
#else
# error "stm32 family not defined."
#endif

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/** @defgroup can_defines CAN defines
@ingroup STM32F_defines
@brief <b>libopencm3 Defined Constants and Types for STM32 CAN </b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
@date 12 November 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CAN_H
#define LIBOPENCM3_CAN_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/**@{*/
/* --- Convenience macros -------------------------------------------------- */
/* CAN register base addresses (for convenience) */
/*****************************************************************************/
/** @defgroup can_reg_base CAN register base address
@ingroup can_defines
@{*/
#define CAN1 BX_CAN1_BASE
#define CAN2 BX_CAN2_BASE
/**@}*/
/* --- CAN registers ------------------------------------------------------- */
/* CAN master control register (CAN_MCR) */
#define CAN_MCR(can_base) MMIO32(can_base + 0x000)
/* CAN master status register (CAN_MSR) */
#define CAN_MSR(can_base) MMIO32(can_base + 0x004)
/* CAN transmit status register (CAN_TSR) */
#define CAN_TSR(can_base) MMIO32(can_base + 0x008)
/* CAN receive FIFO 0 register (CAN_RF0R) */
#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C)
/* CAN receive FIFO 1 register (CAN_RF1R) */
#define CAN_RF1R(can_base) MMIO32(can_base + 0x010)
/* CAN interrupt enable register (CAN_IER) */
#define CAN_IER(can_base) MMIO32(can_base + 0x014)
/* CAN error status register (CAN_ESR) */
#define CAN_ESR(can_base) MMIO32(can_base + 0x018)
/* CAN bit timing register (CAN_BTR) */
#define CAN_BTR(can_base) MMIO32(can_base + 0x01C)
/* Registers in the offset range 0x020 to 0x17F are reserved. */
/* --- CAN mailbox registers ----------------------------------------------- */
/* CAN mailbox / FIFO register offsets */
#define CAN_MBOX0 0x180
#define CAN_MBOX1 0x190
#define CAN_MBOX2 0x1A0
#define CAN_FIFO0 0x1B0
#define CAN_FIFO1 0x1C0
/* CAN TX mailbox identifier register (CAN_TIxR) */
#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0)
#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)
#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)
#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)
/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */
#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4)
#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0)
#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1)
#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2)
/* CAN mailbox data low register (CAN_TDLxR) */
#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8)
#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0)
#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1)
#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2)
/* CAN mailbox data high register (CAN_TDHxR) */
#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC)
#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0)
#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1)
#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2)
/* CAN RX FIFO identifier register (CAN_RIxR) */
#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0)
#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0)
#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1)
/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */
#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4)
#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0)
#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1)
/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */
#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8)
#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0)
#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1)
/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */
#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC)
#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0)
#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1)
/* --- CAN filter registers ------------------------------------------------ */
/* CAN filter master register (CAN_FMR) */
#define CAN_FMR(can_base) MMIO32(can_base + 0x200)
/* CAN filter mode register (CAN_FM1R) */
#define CAN_FM1R(can_base) MMIO32(can_base + 0x204)
/* Register offset 0x208 is reserved. */
/* CAN filter scale register (CAN_FS1R) */
#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C)
/* Register offset 0x210 is reserved. */
/* CAN filter FIFO assignement register (CAN_FFA1R) */
#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214)
/* Register offset 0x218 is reserved. */
/* CAN filter activation register (CAN_FA1R) */
#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C)
/* Register offset 0x220 is reserved. */
/* Registers with offset 0x224 to 0x23F are reserved. */
/* CAN filter bank registers (CAN_FiRx) */
/*
* Connectivity line devices have 28 banks so the bank ID spans 0..27
* all other devices have 14 banks so the bank ID spans 0..13.
*/
#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + \
(bank * 0x8) + 0x0)
#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + \
(bank * 0x8) + 0x4)
/* --- CAN_MCR values ------------------------------------------------------ */
/* 31:17 Reserved, forced by hardware to 0 */
/* DBF: Debug freeze */
#define CAN_MCR_DBF (1 << 16)
/* RESET: bxCAN software master reset */
#define CAN_MCR_RESET (1 << 15)
/* 14:8 Reserved, forced by hardware to 0 */
/* TTCM: Time triggered communication mode */
#define CAN_MCR_TTCM (1 << 7)
/* ABOM: Automatic bus-off management */
#define CAN_MCR_ABOM (1 << 6)
/* AWUM: Automatic wakeup mode */
#define CAN_MCR_AWUM (1 << 5)
/* NART: No automatic retransmission */
#define CAN_MCR_NART (1 << 4)
/* RFLM: Receive FIFO locked mode */
#define CAN_MCR_RFLM (1 << 3)
/* TXFP: Transmit FIFO priority */
#define CAN_MCR_TXFP (1 << 2)
/* SLEEP: Sleep mode request */
#define CAN_MCR_SLEEP (1 << 1)
/* INRQ: Initialization request */
#define CAN_MCR_INRQ (1 << 0)
/* --- CAN_MSR values ------------------------------------------------------ */
/* 31:12 Reserved, forced by hardware to 0 */
/* RX: CAN Rx signal */
#define CAN_MSR_RX (1 << 11)
/* SAMP: Last sample point */
#define CAN_MSR_SAMP (1 << 10)
/* RXM: Receive mode */
#define CAN_MSR_RXM (1 << 9)
/* TXM: Transmit mode */
#define CAN_MSR_TXM (1 << 8)
/* 7:5 Reserved, forced by hardware to 0 */
/* SLAKI: Sleep acknowledge interrupt */
#define CAN_MSR_SLAKI (1 << 4)
/* WKUI: Wakeup interrupt */
#define CAN_MSR_WKUI (1 << 3)
/* ERRI: Error interrupt */
#define CAN_MSR_ERRI (1 << 2)
/* SLAK: Sleep acknowledge */
#define CAN_MSR_SLAK (1 << 1)
/* INAK: Initialization acknowledge */
#define CAN_MSR_INAK (1 << 0)
/* --- CAN_TSR values ------------------------------------------------------ */
/* LOW2: Lowest priority flag for mailbox 2 */
#define CAN_TSR_LOW2 (1 << 31)
/* LOW1: Lowest priority flag for mailbox 1 */
#define CAN_TSR_LOW1 (1 << 30)
/* LOW0: Lowest priority flag for mailbox 0 */
#define CAN_TSR_LOW0 (1 << 29)
/* TME2: Transmit mailbox 2 empty */
#define CAN_TSR_TME2 (1 << 28)
/* TME1: Transmit mailbox 1 empty */
#define CAN_TSR_TME1 (1 << 27)
/* TME0: Transmit mailbox 0 empty */
#define CAN_TSR_TME0 (1 << 26)
/* CODE[1:0]: Mailbox code */
#define CAN_TSR_CODE_MASK (0x3 << 24)
/* ABRQ2: Abort request for mailbox 2 */
#define CAN_TSR_TABRQ2 (1 << 23)
/* 22:20 Reserved, forced by hardware to 0 */
/* TERR2: Transmission error for mailbox 2 */
#define CAN_TSR_TERR2 (1 << 19)
/* ALST2: Arbitration lost for mailbox 2 */
#define CAN_TSR_ALST2 (1 << 18)
/* TXOK2: Transmission OK for mailbox 2 */
#define CAN_TSR_TXOK2 (1 << 17)
/* RQCP2: Request completed mailbox 2 */
#define CAN_TSR_RQCP2 (1 << 16)
/* ABRQ1: Abort request for mailbox 1 */
#define CAN_TSR_ABRQ1 (1 << 15)
/* 14:12 Reserved, forced by hardware to 0 */
/* TERR1: Transmission error for mailbox 1 */
#define CAN_TSR_TERR1 (1 << 11)
/* ALST1: Arbitration lost for mailbox 1 */
#define CAN_TSR_ALST1 (1 << 10)
/* TXOK1: Transmission OK for mailbox 1 */
#define CAN_TSR_TXOK1 (1 << 9)
/* RQCP1: Request completed mailbox 1 */
#define CAN_TSR_RQCP1 (1 << 8)
/* ABRQ0: Abort request for mailbox 0 */
#define CAN_TSR_ABRQ0 (1 << 7)
/* 6:4 Reserved, forced by hardware to 0 */
/* TERR0: Transmission error for mailbox 0 */
#define CAN_TSR_TERR0 (1 << 3)
/* ALST0: Arbitration lost for mailbox 0 */
#define CAN_TSR_ALST0 (1 << 2)
/* TXOK0: Transmission OK for mailbox 0 */
#define CAN_TSR_TXOK0 (1 << 1)
/* RQCP0: Request completed mailbox 0 */
#define CAN_TSR_RQCP0 (1 << 0)
/* --- CAN_RF0R values ----------------------------------------------------- */
/* 31:6 Reserved, forced by hardware to 0 */
/* RFOM0: Release FIFO 0 output mailbox */
#define CAN_RF0R_RFOM0 (1 << 5)
/* FOVR0: FIFO 0 overrun */
#define CAN_RF0R_FAVR0 (1 << 4)
/* FULL0: FIFO 0 full */
#define CAN_RF0R_FULL0 (1 << 3)
/* 2 Reserved, forced by hardware to 0 */
/* FMP0[1:0]: FIFO 0 message pending */
#define CAN_RF0R_FMP0_MASK (0x3 << 0)
/* --- CAN_RF1R values ----------------------------------------------------- */
/* 31:6 Reserved, forced by hardware to 0 */
/* RFOM1: Release FIFO 1 output mailbox */
#define CAN_RF1R_RFOM1 (1 << 5)
/* FOVR1: FIFO 1 overrun */
#define CAN_RF1R_FAVR1 (1 << 4)
/* FULL1: FIFO 1 full */
#define CAN_RF1R_FULL1 (1 << 3)
/* 2 Reserved, forced by hardware to 0 */
/* FMP1[1:0]: FIFO 1 message pending */
#define CAN_RF1R_FMP1_MASK (0x3 << 0)
/* --- CAN_IER values ------------------------------------------------------ */
/* 32:18 Reserved, forced by hardware to 0 */
/* SLKIE: Sleep interrupt enable */
#define CAN_IER_SLKIE (1 << 17)
/* WKUIE: Wakeup interrupt enable */
#define CAN_IER_WKUIE (1 << 16)
/* ERRIE: Error interrupt enable */
#define CAN_IER_ERRIE (1 << 15)
/* 14:12 Reserved, forced by hardware to 0 */
/* LECIE: Last error code interrupt enable */
#define CAN_IER_LECIE (1 << 11)
/* BOFIE: Bus-off interrupt enable */
#define CAN_IER_BOFIE (1 << 10)
/* EPVIE: Error passive interrupt enable */
#define CAN_IER_EPVIE (1 << 9)
/* EWGIE: Error warning interrupt enable */
#define CAN_IER_EWGIE (1 << 8)
/* 7 Reserved, forced by hardware to 0 */
/* FOVIE1: FIFO overrun interrupt enable */
#define CAN_IER_FOVIE1 (1 << 6)
/* FFIE1: FIFO full interrupt enable */
#define CAN_IER_FFIE1 (1 << 5)
/* FMPIE1: FIFO message pending interrupt enable */
#define CAN_IER_FMPIE1 (1 << 4)
/* FOVIE0: FIFO overrun interrupt enable */
#define CAN_IER_FOVIE0 (1 << 3)
/* FFIE0: FIFO full interrupt enable */
#define CAN_IER_FFIE0 (1 << 2)
/* FMPIE0: FIFO message pending interrupt enable */
#define CAN_IER_FMPIE0 (1 << 1)
/* TMEIE: Transmit mailbox empty interrupt enable */
#define CAN_IER_TMEIE (1 << 0)
/* --- CAN_ESR values ------------------------------------------------------ */
/* REC[7:0]: Receive error counter */
#define CAN_ESR_REC_MASK (0xF << 24)
/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */
#define CAN_ESR_TEC_MASK (0xF << 16)
/* 15:7 Reserved, forced by hardware to 0 */
/* LEC[2:0]: Last error code */
#define CAN_ESR_LEC_NO_ERROR (0x0 << 4)
#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4)
#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4)
#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4)
#define CAN_ESR_LEC_REC_ERROR (0x4 << 4)
#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4)
#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4)
#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4)
#define CAN_ESR_LEC_MASK (0x7 << 4)
/* 3 Reserved, forced by hardware to 0 */
/* BOFF: Bus-off flag */
#define CAN_ESR_BOFF (1 << 2)
/* EPVF: Error passive flag */
#define CAN_ESR_EPVF (1 << 1)
/* EWGF: Error warning flag */
#define CAN_ESR_EWGF (1 << 0)
/* --- CAN_BTR values ------------------------------------------------------ */
/* SILM: Silent mode (debug) */
#define CAN_BTR_SILM (1 << 31)
/* LBKM: Loop back mode (debug) */
#define CAN_BTR_LBKM (1 << 30)
/* 29:26 Reserved, forced by hardware to 0 */
/* SJW[1:0]: Resynchronization jump width */
#define CAN_BTR_SJW_1TQ (0x0 << 24)
#define CAN_BTR_SJW_2TQ (0x1 << 24)
#define CAN_BTR_SJW_3TQ (0x2 << 24)
#define CAN_BTR_SJW_4TQ (0x3 << 24)
#define CAN_BTR_SJW_MASK (0x3 << 24)
#define CAN_BTR_SJW_SHIFT 24
/* 23 Reserved, forced by hardware to 0 */
/* TS2[2:0]: Time segment 2 */
#define CAN_BTR_TS2_1TQ (0x0 << 20)
#define CAN_BTR_TS2_2TQ (0x1 << 20)
#define CAN_BTR_TS2_3TQ (0x2 << 20)
#define CAN_BTR_TS2_4TQ (0x3 << 20)
#define CAN_BTR_TS2_5TQ (0x4 << 20)
#define CAN_BTR_TS2_6TQ (0x5 << 20)
#define CAN_BTR_TS2_7TQ (0x6 << 20)
#define CAN_BTR_TS2_8TQ (0x7 << 20)
#define CAN_BTR_TS2_MASK (0x7 << 20)
#define CAN_BTR_TS2_SHIFT 20
/* TS1[3:0]: Time segment 1 */
#define CAN_BTR_TS1_1TQ (0x0 << 16)
#define CAN_BTR_TS1_2TQ (0x1 << 16)
#define CAN_BTR_TS1_3TQ (0x2 << 16)
#define CAN_BTR_TS1_4TQ (0x3 << 16)
#define CAN_BTR_TS1_5TQ (0x4 << 16)
#define CAN_BTR_TS1_6TQ (0x5 << 16)
#define CAN_BTR_TS1_7TQ (0x6 << 16)
#define CAN_BTR_TS1_8TQ (0x7 << 16)
#define CAN_BTR_TS1_9TQ (0x8 << 16)
#define CAN_BTR_TS1_10TQ (0x9 << 16)
#define CAN_BTR_TS1_11TQ (0xA << 16)
#define CAN_BTR_TS1_12TQ (0xB << 16)
#define CAN_BTR_TS1_13TQ (0xC << 16)
#define CAN_BTR_TS1_14TQ (0xD << 16)
#define CAN_BTR_TS1_15TQ (0xE << 16)
#define CAN_BTR_TS1_16TQ (0xF << 16)
#define CAN_BTR_TS1_MASK (0xF << 16)
#define CAN_BTR_TS1_SHIFT 16
/* 15:10 Reserved, forced by hardware to 0 */
/* BRP[9:0]: Baud rate prescaler */
#define CAN_BTR_BRP_MASK (0x1FFUL << 0)
/* --- CAN_TIxR values ------------------------------------------------------ */
/* STID[10:0]: Standard identifier */
#define CAN_TIxR_STID_MASK (0x7FF << 21)
#define CAN_TIxR_STID_SHIFT 21
/* EXID[15:0]: Extended identifier */
#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3)
#define CAN_TIxR_EXID_SHIFT 3
/* IDE: Identifier extension */
#define CAN_TIxR_IDE (1 << 2)
/* RTR: Remote transmission request */
#define CAN_TIxR_RTR (1 << 1)
/* TXRQ: Transmit mailbox request */
#define CAN_TIxR_TXRQ (1 << 0)
/* --- CAN_TDTxR values ----------------------------------------------------- */
/* TIME[15:0]: Message time stamp */
#define CAN_TDTxR_TIME_MASK (0xFFFF << 15)
#define CAN_TDTxR_TIME_SHIFT 15
/* 15:6 Reserved, forced by hardware to 0 */
/* TGT: Transmit global time */
#define CAN_TDTxR_TGT (1 << 5)
/* 7:4 Reserved, forced by hardware to 0 */
/* DLC[3:0]: Data length code */
#define CAN_TDTxR_DLC_MASK (0xF << 0)
#define CAN_TDTxR_DLC_SHIFT 0
/* --- CAN_TDLxR values ----------------------------------------------------- */
/* DATA3[7:0]: Data byte 3 */
/* DATA2[7:0]: Data byte 2 */
/* DATA1[7:0]: Data byte 1 */
/* DATA0[7:0]: Data byte 0 */
/* --- CAN_TDHxR values ----------------------------------------------------- */
/* DATA7[7:0]: Data byte 7 */
/* DATA6[7:0]: Data byte 6 */
/* DATA5[7:0]: Data byte 5 */
/* DATA4[7:0]: Data byte 4 */
/* --- CAN_RIxR values ------------------------------------------------------ */
/* STID[10:0]: Standard identifier */
#define CAN_RIxR_STID_MASK (0x7FF)
#define CAN_RIxR_STID_SHIFT 21
/* EXID[15:0]: Extended identifier */
#define CAN_RIxR_EXID_MASK (0x1FFFFFFF)
#define CAN_RIxR_EXID_SHIFT 3
/* IDE: Identifier extension */
#define CAN_RIxR_IDE (1 << 2)
/* RTR: Remote transmission request */
#define CAN_RIxR_RTR (1 << 1)
/* 0 Reserved */
/* --- CAN_RDTxR values ----------------------------------------------------- */
/* TIME[15:0]: Message time stamp */
#define CAN_RDTxR_TIME_MASK (0xFFFF << 15)
#define CAN_RDTxR_TIME_SHIFT 15
/* FMI[7:0]: Filter match index */
#define CAN_RDTxR_FMI_MASK (0xFF << 8)
#define CAN_RDTxR_FMI_SHIFT 8
/* 7:4 Reserved, forced by hardware to 0 */
/* DLC[3:0]: Data length code */
#define CAN_RDTxR_DLC_MASK (0xF << 0)
#define CAN_RDTxR_DLC_SHIFT 0
/* --- CAN_RDLxR values ----------------------------------------------------- */
/* DATA3[7:0]: Data byte 3 */
/* DATA2[7:0]: Data byte 2 */
/* DATA1[7:0]: Data byte 1 */
/* DATA0[7:0]: Data byte 0 */
/* --- CAN_RDHxR values ----------------------------------------------------- */
/* DATA7[7:0]: Data byte 7 */
/* DATA6[7:0]: Data byte 6 */
/* DATA5[7:0]: Data byte 5 */
/* DATA4[7:0]: Data byte 4 */
/* --- CAN_FMR values ------------------------------------------------------- */
/* 31:14 Reserved, forced to reset value */
/*
* CAN2SB[5:0]: CAN2 start bank
* (only on connectivity line devices otherwise reserved)
*/
#define CAN_FMR_CAN2SB_MASK (0x3F << 8)
#define CAN_FMR_CAN2SB_SHIFT 15
/* 7:1 Reserved, forced to reset value */
/* FINIT: Filter init mode */
#define CAN_FMR_FINIT (1 << 0)
/* --- CAN_FM1R values ------------------------------------------------------ */
/* 31:28 Reserved, forced by hardware to 0 */
/*
* FBMx: Filter mode
* x is 0..27 should be calculated by a helper function making so many macros
* seems like an overkill?
*/
/* --- CAN_FS1R values ------------------------------------------------------ */
/* 31:28 Reserved, forced by hardware to 0 */
/*
* FSCx: Filter scale configuration
* x is 0..27 should be calculated by a helper function making so many macros
* seems like an overkill?
*/
/* --- CAN_FFA1R values ----------------------------------------------------- */
/* 31:28 Reserved, forced by hardware to 0 */
/*
* FFAx: Filter scale configuration
* x is 0..27 should be calculated by a helper function making so many macros
* seems like an overkill?
*/
/* --- CAN_FA1R values ------------------------------------------------------ */
/* 31:28 Reserved, forced by hardware to 0 */
/*
* FACTx: Filter active
* x is 0..27 should be calculated by a helper function making so many macros
* seems like an overkill?
*/
/* --- CAN_FiRx values ------------------------------------------------------ */
/* FB[31:0]: Filter bits */
/* --- CAN functions -------------------------------------------------------- */
BEGIN_DECLS
void can_reset(uint32_t canport);
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2,
uint32_t brp, bool loopback, bool silent);
void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit,
bool id_list_mode, uint32_t fr1, uint32_t fr2,
uint32_t fifo, bool enable);
void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1,
uint16_t mask1, uint16_t id2,
uint16_t mask2, uint32_t fifo, bool enable);
void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id,
uint32_t mask, uint32_t fifo, bool enable);
void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1,
uint16_t id2, uint16_t id3, uint16_t id4,
uint32_t fifo, bool enable);
void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1,
uint32_t id2, uint32_t fifo, bool enable);
void can_enable_irq(uint32_t canport, uint32_t irq);
void can_disable_irq(uint32_t canport, uint32_t irq);
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr,
uint8_t length, uint8_t *data);
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id,
bool *ext, bool *rtr, uint32_t *fmi, uint8_t *length,
uint8_t *data);
void can_fifo_release(uint32_t canport, uint8_t fifo);
bool can_available_mailbox(uint32_t canport);
END_DECLS
#endif

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/* This provides unification of code over STM32F subfamilies */
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#if defined(STM32F0)
# include <libopencm3/stm32/f0/cec.h>
#else
# error "stm32 family not defined."
#endif

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/** @addtogroup crc_defines
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H
The order of header inclusion is important. crc.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_CRC_H
/** @endcond */
#ifndef LIBOPENCM3_CRC_COMMON_ALL_H
#define LIBOPENCM3_CRC_COMMON_ALL_H
/**@{*/
#include <libopencm3/cm3/common.h>
/* --- CRC registers ------------------------------------------------------- */
/* Data register (CRC_DR) */
#define CRC_DR MMIO32(CRC_BASE + 0x00)
/* Independent data register (CRC_IDR) */
#define CRC_IDR MMIO32(CRC_BASE + 0x04)
/* Control register (CRC_CR) */
#define CRC_CR MMIO32(CRC_BASE + 0x08)
/* --- CRC_DR values ------------------------------------------------------- */
/* Bits [31:0]: Data register */
/* --- CRC_IDR values ------------------------------------------------------ */
/* Bits [31:8]: Reserved */
/* Bits [7:0]: General-purpose 8-bit data register bits */
/* --- CRC_CR values ------------------------------------------------------- */
/* Bits [31:1]: Reserved */
/* RESET bit */
#define CRC_CR_RESET (1 << 0)
/* --- CRC function prototypes --------------------------------------------- */
BEGIN_DECLS
/* TODO */
/**
* Reset the CRC calculator to initial values.
*/
void crc_reset(void);
/**
* Add a word to the CRC calculator and return the result.
* @param data new word to add to the CRC calculator
* @return final CRC calculator value
*/
uint32_t crc_calculate(uint32_t data);
/**
* Add a block of data to the CRC calculator and return the final result
* @param datap pointer to the start of a block of 32bit data words
* @param size length of data, in 32bit increments
* @return final CRC calculator value
*/
uint32_t crc_calculate_block(uint32_t *datap, int size);
END_DECLS
/**@}*/
#endif
/** @cond */
#else
#warning "crc_common_all.h should not be included explicitly, only via crc.h"
#endif
/** @endcond */

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/** @addtogroup crypto_defines
*
* @warning The CRYP subsystem is present only in a limited set of devices,
* see next section for list of supported devices.
*
* @section crypto_api_supported Supported devices
*
* - STM32F205
* - STM32F207
* - STM32F215
* - STM32F217
* - STM32F405
* - STM32F407
* - STM32F415
* - STM32F417 <i>(tested)</i>
* - STM32F427
* - STM32F437
*
* @section crypto_api_theory Theory of operation
*
*
*
* @section crypto_api_basic Basic handling API
*
*
* @b Example @b 1: Blocking mode
*
* @code
* //[enable-clocks]
* crypto_set_key(CRYPTO_KEY_128BIT,key);
* crypto_set_iv(iv); // only in CBC or CTR mode
* crypto_set_datatype(CRYPTO_DATA_16BIT);
* crypto_set_algorithm(ENCRYPT_AES_ECB);
* crypto_start();
* foreach(block in blocks)
* crypto_process_block(plaintext,ciphertext,blocksize);
* crypto_stop();
* @endcode
*
* @section crypto_api_interrupt Interrupt supported handling API
*
* @warning This operation mode is currently not supported.
*
* @b Example @b 2: Interrupt mode
*
* @code
* //[enable-clocks]
* crypto_set_key(CRYPTO_KEY_128BIT,key);
* crypto_set_iv(iv); // only in CBC or CTR mode
* crypto_set_datatype(CRYPTO_DATA_16BIT);
* crypto_set_algorithm(ENCRYPT_AES_ECB);
* crypto_start();
* [... API to be described later ...]
* crypto_stop();
* @endcode
*
* @section crypto_api_dma DMA handling API
*
* @warning This operation mode is currently not supported.
*
* @b Example @b 3: DMA mode
*
* @code
* //[enable-clocks]
* crypto_set_key(CRYPTO_KEY_128BIT,key);
* crypto_set_iv(iv); // only in CBC or CTR mode
* crypto_set_datatype(CRYPTO_DATA_16BIT);
* crypto_set_algorithm(ENCRYPT_AES_ECB);
* crypto_start();
* [... API to be described later ...]
* crypto_stop();
* @endcode
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRYP.H
The order of header inclusion is important. cryp.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_CRYPTO_H
/** @endcond */
#ifndef LIBOPENCM3_CRYPTO_COMMON_F24_H
#define LIBOPENCM3_CRYPTO_COMMON_F24_H
#include <libopencm3/cm3/common.h>
/**@{*/
/* --- CRYP registers ------------------------------------------------------ */
/** @defgroup crypto_registers_gen Registers (Generic)
*
* @brief Register access to the CRYP controller. (All chips)
*
* @ingroup crypto_defines
*/
/**@{*/
#define CRYP CRYP_BASE
/* CRYP Control Register (CRYP_CR) */
#define CRYP_CR MMIO32(CRYP_BASE + 0x00)
/* CRYP Status Register (CRYP_SR) */
#define CRYP_SR MMIO32(CRYP_BASE + 0x04)
/* CRYP Data Input Register (CRYP_DIN) */
#define CRYP_DIN MMIO32(CRYP_BASE + 0x08)
/** CRYP Data Output Register (CRYP_DOUT) @see blablabla */
#define CRYP_DOUT MMIO32(CRYP_BASE + 0x0C)
/* CRYP DMA Control Register (CRYP_DMACR) */
#define CRYP_DMACR MMIO32(CRYP_BASE + 0x10)
/* CRYP Interrupt mask set/clear register (CRYP_IMSCR) */
#define CRYP_IMSCR MMIO32(CRYP_BASE + 0x14)
/* CRYP Raw Interrupt status register (CRYP_RISR) */
#define CRYP_RISR MMIO32(CRYP_BASE + 0x18)
/* CRYP Masked Interrupt status register (CRYP_MISR) */
#define CRYP_MISR MMIO32(CRYP_BASE + 0x1C)
/* CRYP Key registers (CRYP_KxLR) x=0..3 */
#define CRYP_KR(i) MMIO64(CRYP_BASE + 0x20 + (i) * 8)
/* CRYP Initialization Vector Registers (CRYP_IVxLR) x=0..1 */
#define CRYP_IVR(i) MMIO32(CRYP_BASE + 0x40 + (i) * 8)
/* --- CRYP_CR values ------------------------------------------------------ */
/* ALGODIR: Algorithm direction */
#define CRYP_CR_ALGODIR (1 << 2)
/* ALGOMODE: Algorithm mode */
#define CRYP_CR_ALGOMODE_SHIFT 3
#define CRYP_CR_ALGOMODE (7 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_TDES_ECB (0 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_TDES_CBC (1 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_DES_ECB (2 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_DES_CBC (3 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_AES_ECB (4 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_AES_CBC (5 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_AES_CTR (6 << CRYP_CR_ALGOMODE_SHIFT)
#define CRYP_CR_ALGOMODE_AES_PREP (7 << CRYP_CR_ALGOMODE_SHIFT)
/* DATATYPE: Data type selection */
#define CRYP_CR_DATATYPE_SHIFT 6
#define CRYP_CR_DATATYPE (3 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_32 (0 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_16 (1 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_8 (2 << CRYP_CR_DATATYPE_SHIFT)
#define CRYP_CR_DATATYPE_BIT (3 << CRYP_CR_DATATYPE_SHIFT)
/* KEYSIZE: Key size selection (AES mode only)*/
#define CRYP_CR_KEYSIZE_SHIFT 8
#define CRYP_CR_KEYSIZE (3 << CRYP_CR_KEYSIZE_SHIFT)
#define CRYP_CR_KEYSIZE_128 (0 << CRYP_CR_KEYSIZE_SHIFT)
#define CRYP_CR_KEYSIZE_192 (1 << CRYP_CR_KEYSIZE_SHIFT)
#define CRYP_CR_KEYSIZE_256 (2 << CRYP_CR_KEYSIZE_SHIFT)
/* FFLUSH: FIFO Flush */
#define CRYP_CR_FFLUSH (1 << 14)
/* CRYPEN: Cryptographic processor enable*/
#define CRYP_CR_CRYPEN (1 << 15)
/* --- CRYP_SR values ------------------------------------------------------ */
/* IFEM: Input FIFO empty */
#define CRYP_SR_IFEM (1 << 0)
/* IFNF: Input FIFO not full */
#define CRYP_SR_IFNF (1 << 1)
/* OFNE: Output FIFO not empty */
#define CRYP_SR_OFNE (1 << 2)
/* OFFU: Output FIFO full */
#define CRYP_SR_OFFU (1 << 3)
/* BUSY: Busy bit */
#define CRYP_SR_BUSY (1 << 4)
/* --- CRYP_DMACR values --------------------------------------------------- */
/* DIEN: DMA input enable */
#define CRYP_DMACR_DIEN (1 << 0)
/* DOEN: DMA output enable */
#define CRYP_DMACR_DOEN (1 << 1)
/* --- CRYP_IMSCR values --------------------------------------------------- */
/* INIM: Input FIFO service interrupt mask */
#define CRYP_IMSCR_INIM (1 << 0)
/* OUTIM: Output FIFO service interrupt mask */
#define CRYP_IMSCR_OUTIM (1 << 1)
/* --- CRYP_RISR values ---------------------------------------------------- */
/* INRIS: Input FIFO service raw interrupt status */
#define CRYP_RISR_INRIS (1 << 0)
/* OUTRIS: Output FIFO service raw data */
#define CRYP_RISR_OUTRIS (1 << 0)
/* --- CRYP_MISR values ---------------------------------------------------- */
/* INMIS: Input FIFO service masked interrupt status */
#define CRYP_MISR_INMIS (1 << 0)
/* OUTMIS: Output FIFO service masked interrupt status */
#define CRYP_MISR_OUTMIS (1 << 0)
/**@}*/
/** @defgroup crypto_api_gen API (Generic)
*
* @brief API for the CRYP controller
*
* @ingroup crypto_defines
*/
/**@{*/
enum crypto_mode {
ENCRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB,
ENCRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC,
ENCRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB,
ENCRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC,
ENCRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB,
ENCRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC,
ENCRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR,
DECRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGODIR,
DECRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGODIR,
DECRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB | CRYP_CR_ALGODIR,
DECRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC | CRYP_CR_ALGODIR,
DECRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR,
DECRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR,
DECRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR,/* XOR is same ENC as DEC */
};
enum crypto_keysize {
CRYPTO_KEY_128BIT = 0,
CRYPTO_KEY_192BIT,
CRYPTO_KEY_256BIT,
};
enum crypto_datatype {
CRYPTO_DATA_32BIT = 0,
CRYPTO_DATA_16BIT,
CRYPTO_DATA_8BIT,
CRYPTO_DATA_BIT,
};
BEGIN_DECLS
void crypto_wait_busy(void);
void crypto_set_key(enum crypto_keysize keysize, uint64_t key[]);
void crypto_set_iv(uint64_t iv[]);
void crypto_set_datatype(enum crypto_datatype datatype);
void crypto_set_algorithm(enum crypto_mode mode);
void crypto_start(void);
void crypto_stop(void);
uint32_t crypto_process_block(uint32_t *inp, uint32_t *outp, uint32_t length);
END_DECLS
/**@}*/
/**@}*/
#endif
/** @cond */
#else
#warning "crypto_common_f24.h should not be included explicitly, "
"only via crypto.h"
#endif
/** @endcond */

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/** @addtogroup dac_defines
@author @htmlonly &copy; @endhtmlonly 2012
Felix Held <felix-libopencm3@felixheld.de>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H
The order of header inclusion is important. dac.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_DAC_H
/** @endcond */
#ifndef LIBOPENCM3_DAC_COMMON_ALL_H
#define LIBOPENCM3_DAC_COMMON_ALL_H
#include <libopencm3/cm3/common.h>
/* --- DAC registers ------------------------------------------------------- */
/* DAC control register (DAC_CR) */
#define DAC_CR MMIO32(DAC_BASE + 0x00)
/* DAC software trigger register (DAC_SWTRIGR) */
#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04)
/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08)
/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C)
/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10)
/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14)
/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18)
/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C)
/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20)
/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24)
/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28)
/* DAC channel1 data output register (DAC_DOR1) */
#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C)
/* DAC channel2 data output register (DAC_DOR2) */
#define DAC_DOR2 MMIO32(DAC_BASE + 0x30)
/* --- DAC_CR values ------------------------------------------------------- */
/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
/* doesn't exist in most members of the STM32F1 family */
#define DAC_CR_DMAUDRIE2 (1 << 29)
/* DMAEN2: DAC channel2 DMA enable */
#define DAC_CR_DMAEN2 (1 << 28)
/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
/* DAC_CR_MAMP2_n:
* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
*/
#define DAC_CR_MAMP2_SHIFT 24
/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude
values
@ingroup dac_defines
Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
@{*/
#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
/**@}*/
/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
/* Legend:
* DIS: wave generation disabled
* NOISE: Noise wave generation enabled
* TRI: Triangle wave generation enabled
*
* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
*/
#define DAC_CR_WAVE2_SHIFT 22
#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT)
/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
@ingroup dac_defines
@li NOISE: Noise wave generation enabled
@li TRI: Triangle wave generation enabled
@note: only used if bit TEN2 is set (DAC channel2 trigger enabled)
@{*/
#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
/**@}*/
/* TSEL2[2:0]: DAC channel2 trigger selection */
/* Legend:
*
* T6: Timer 6 TRGO event
* T3: Timer 3 TRGO event
* T8: Timer 8 TRGO event
* T7: Timer 7 TRGO event
* T5: Timer 5 TRGO event
* T15: Timer 15 TRGO event
* T2: Timer 2 TRGO event
* T4: Timer 4 TRGO event
* E9: External line9
* SW: Software trigger
*
* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
* Note: T3 == T8; T5 == T15; not both present on one device
* Note: this is *not* valid for the STM32L1 family
*/
#define DAC_CR_TSEL2_SHIFT 19
/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
@ingroup dac_defines
@li T6: Timer 6 TRGO event
@li T3: Timer 3 TRGO event
@li T8: Timer 8 TRGO event
@li T7: Timer 7 TRGO event
@li T5: Timer 5 TRGO event
@li T15: Timer 15 TRGO event
@li T2: Timer 2 TRGO event
@li T4: Timer 4 TRGO event
@li E9: External line9
@li SW: Software trigger
@note: Refer to the timer documentation for details of the TRGO event.
@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
@note: this is <b>not</b> valid for the STM32L1 family.
@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
@{*/
#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
/**@}*/
/* TEN2: DAC channel2 trigger enable */
#define DAC_CR_TEN2 (1 << 18)
/* BOFF2: DAC channel2 output buffer disable */
#define DAC_CR_BOFF2 (1 << 17)
/* EN2: DAC channel2 enable */
#define DAC_CR_EN2 (1 << 16)
/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
/* doesn't exist in most members of the STM32F1 family */
#define DAC_CR_DMAUDRIE1 (1 << 13)
/* DMAEN1: DAC channel1 DMA enable */
#define DAC_CR_DMAEN1 (1 << 12)
/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
/* DAC_CR_MAMP1_n:
* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
*/
#define DAC_CR_MAMP1_SHIFT 8
/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude
values
@ingroup dac_defines
Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
@{*/
#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
/**@}*/
/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
/* Legend:
* DIS: wave generation disabled
* NOISE: Noise wave generation enabled
* TRI: Triangle wave generation enabled
*
* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
*/
#define DAC_CR_WAVE1_SHIFT 6
#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT)
/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
@ingroup dac_defines
@li DIS: wave generation disabled
@li NOISE: Noise wave generation enabled
@li TRI: Triangle wave generation enabled
@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
@{*/
#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
/**@}*/
/* TSEL1[2:0]: DAC channel1 trigger selection */
/* Legend:
*
* T6: Timer 6 TRGO event
* T3: Timer 3 TRGO event in connectivity line devices
* T8: Timer 8 TRGO event in high-density and XL-density devices
* T7: Timer 7 TRGO event
* T5: Timer 5 TRGO event
* T15: Timer 15 TRGO event
* T2: Timer 2 TRGO event
* T4: Timer 4 TRGO event
* E9: External line9
* SW: Software trigger
*
* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
* Note: T3 == T8; T5 == T15; not both present on one device
* Note: this is *not* valid for the STM32L1 family
*/
#define DAC_CR_TSEL1_SHIFT 3
/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
@ingroup dac_defines
@li T6: Timer 6 TRGO event
@li T3: Timer 3 TRGO event
@li T8: Timer 8 TRGO event
@li T7: Timer 7 TRGO event
@li T5: Timer 5 TRGO event
@li T15: Timer 15 TRGO event
@li T2: Timer 2 TRGO event
@li T4: Timer 4 TRGO event
@li E9: External line 9
@li SW: Software trigger
@note: Refer to the timer documentation for details of the TRGO event.
@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
@note: this is <b>not</b> valid for the STM32L1 family.
@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled).
@{*/
#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
/**@}*/
/* TEN1: DAC channel1 trigger enable */
#define DAC_CR_TEN1 (1 << 2)
/* BOFF1: DAC channel1 output buffer disable */
#define DAC_CR_BOFF1 (1 << 1)
/* EN1: DAC channel1 enable */
#define DAC_CR_EN1 (1 << 0)
/* --- DAC_SWTRIGR values -------------------------------------------------- */
/* SWTRIG2: DAC channel2 software trigger */
#define DAC_SWTRIGR_SWTRIG2 (1 << 1)
/* SWTRIG1: DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
/* --- DAC_DHR12R1 values -------------------------------------------------- */
#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0)
#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0)
/* --- DAC_DHR12L1 values -------------------------------------------------- */
#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4)
#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4)
/* --- DAC_DHR8R1 values --------------------------------------------------- */
#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0)
#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0)
/* --- DAC_DHR12R2 values -------------------------------------------------- */
#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0)
#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0)
/* --- DAC_DHR12L2 values -------------------------------------------------- */
#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4)
#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4)
/* --- DAC_DHR8R2 values --------------------------------------------------- */
#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0)
#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0)
/* --- DAC_DHR12RD values -------------------------------------------------- */
#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16)
#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16)
#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0)
#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0)
/* --- DAC_DHR12LD values -------------------------------------------------- */
#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16)
#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20)
#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0)
#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4)
/* --- DAC_DHR8RD values --------------------------------------------------- */
#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8)
#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8)
#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0)
#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0)
/* --- DAC_DOR1 values ----------------------------------------------------- */
#define DAC_DOR1_DACC1DOR_LSB (1 << 0)
#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0)
/* --- DAC_DOR2 values ----------------------------------------------------- */
#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
/** DAC channel identifier */
typedef enum {
CHANNEL_1, CHANNEL_2, CHANNEL_D
} data_channel;
/** DAC data size (8/12 bits), alignment (right/left) */
typedef enum {
RIGHT8, RIGHT12, LEFT12
} data_align;
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void dac_enable(data_channel dac_channel);
void dac_disable(data_channel dac_channel);
void dac_buffer_enable(data_channel dac_channel);
void dac_buffer_disable(data_channel dac_channel);
void dac_dma_enable(data_channel dac_channel);
void dac_dma_disable(data_channel dac_channel);
void dac_trigger_enable(data_channel dac_channel);
void dac_trigger_disable(data_channel dac_channel);
void dac_set_trigger_source(uint32_t dac_trig_src);
void dac_set_waveform_generation(uint32_t dac_wave_ens);
void dac_disable_waveform_generation(data_channel dac_channel);
void dac_set_waveform_characteristics(uint32_t dac_mamp);
void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format,
data_channel dac_channel);
void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2,
data_align dac_data_format);
void dac_software_trigger(data_channel dac_channel);
END_DECLS
#endif
/** @cond */
#else
#warning "dac_common_all.h should not be included explicitly, only via dac.h"
#endif
/** @endcond */
/**@}*/

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/** @addtogroup dma_defines
@author @htmlonly &copy; @endhtmlonly 2011
Fergus Noble <fergusnoble@gmail.com>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H
The order of header inclusion is important. dma.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_DMA_H
/** @endcond */
#ifndef LIBOPENCM3_DMA_COMMON_F24_H
#define LIBOPENCM3_DMA_COMMON_F24_H
/**@{*/
#include <libopencm3/cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */
/* DMA controller base addresses (for convenience) */
#define DMA1 DMA1_BASE
#define DMA2 DMA2_BASE
/* DMA stream base addresses (for API parameters) */
/** @defgroup dma_st_number DMA Stream Number
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_STREAM0 0
#define DMA_STREAM1 1
#define DMA_STREAM2 2
#define DMA_STREAM3 3
#define DMA_STREAM4 4
#define DMA_STREAM5 5
#define DMA_STREAM6 6
#define DMA_STREAM7 7
/**@}*/
#define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n)))
#define DMA1_STREAM(n) DMA_STREAM(DMA1, n)
#define DMA2_STREAM(n) DMA_STREAM(DMA2, n)
#define DMA1_STREAM0 DMA1_STREAM(0)
#define DMA1_STREAM1 DMA1_STREAM(1)
#define DMA1_STREAM2 DMA1_STREAM(2)
#define DMA1_STREAM3 DMA1_STREAM(3)
#define DMA1_STREAM4 DMA1_STREAM(4)
#define DMA1_STREAM5 DMA1_STREAM(5)
#define DMA1_STREAM6 DMA1_STREAM(6)
#define DMA1_STREAM7 DMA1_STREAM(7)
#define DMA2_STREAM0 DMA2_STREAM(0)
#define DMA2_STREAM1 DMA2_STREAM(1)
#define DMA2_STREAM2 DMA2_STREAM(2)
#define DMA2_STREAM3 DMA2_STREAM(3)
#define DMA2_STREAM4 DMA2_STREAM(4)
#define DMA2_STREAM5 DMA2_STREAM(5)
#define DMA2_STREAM6 DMA2_STREAM(6)
#define DMA2_STREAM7 DMA2_STREAM(7)
/* --- DMA controller registers -------------------------------------------- */
/* DMA low interrupt status register (DMAx_LISR) */
#define DMA_LISR(port) MMIO32(port + 0x00)
#define DMA1_LISR DMA_LISR(DMA1)
#define DMA2_LISR DMA_LISR(DMA2)
/* DMA high interrupt status register (DMAx_HISR) */
#define DMA_HISR(port) MMIO32(port + 0x04)
#define DMA1_HISR DMA_HISR(DMA1)
#define DMA2_HISR DMA_HISR(DMA2)
/* DMA low interrupt flag clear register (DMAx_LIFCR) */
#define DMA_LIFCR(port) MMIO32(port + 0x08)
#define DMA1_LIFCR DMA_LIFCR(DMA1)
#define DMA2_LIFCR DMA_LIFCR(DMA2)
/* DMA high interrupt flag clear register (DMAx_HIFCR) */
#define DMA_HIFCR(port) MMIO32(port + 0x0C)
#define DMA1_HIFCR DMA_HIFCR(DMA1)
#define DMA2_HIFCR DMA_HIFCR(DMA2)
/* --- DMA stream registers ------------------------------------------------ */
/* DMA Stream x configuration register (DMA_SxCR) */
#define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00)
#define DMA1_SCR(n) DMA_SCR(DMA1, n)
#define DMA2_SCR(n) DMA_SCR(DMA2, n)
#define DMA1_S0CR DMA1_SCR(0)
#define DMA1_S1CR DMA1_SCR(1)
#define DMA1_S2CR DMA1_SCR(2)
#define DMA1_S3CR DMA1_SCR(3)
#define DMA1_S4CR DMA1_SCR(4)
#define DMA1_S5CR DMA1_SCR(5)
#define DMA1_S6CR DMA1_SCR(6)
#define DMA1_S7CR DMA1_SCR(7)
#define DMA2_S0CR DMA2_SCR(0)
#define DMA2_S1CR DMA2_SCR(1)
#define DMA2_S2CR DMA2_SCR(2)
#define DMA2_S3CR DMA2_SCR(3)
#define DMA2_S4CR DMA2_SCR(4)
#define DMA2_S5CR DMA2_SCR(5)
#define DMA2_S6CR DMA2_SCR(6)
#define DMA2_S7CR DMA2_SCR(7)
/* DMA Stream x number of data register (DMA_SxNDTR) */
#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04)
#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n)
#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n)
#define DMA1_S0NDTR DMA1_SNDTR(0)
#define DMA1_S1NDTR DMA1_SNDTR(1)
#define DMA1_S2NDTR DMA1_SNDTR(2)
#define DMA1_S3NDTR DMA1_SNDTR(3)
#define DMA1_S4NDTR DMA1_SNDTR(4)
#define DMA1_S5NDTR DMA1_SNDTR(5)
#define DMA1_S6NDTR DMA1_SNDTR(6)
#define DMA1_S7NDTR DMA1_SNDTR(7)
#define DMA2_S0NDTR DMA2_SNDTR(0)
#define DMA2_S1NDTR DMA2_SNDTR(1)
#define DMA2_S2NDTR DMA2_SNDTR(2)
#define DMA2_S3NDTR DMA2_SNDTR(3)
#define DMA2_S4NDTR DMA2_SNDTR(4)
#define DMA2_S5NDTR DMA2_SNDTR(5)
#define DMA2_S6NDTR DMA2_SNDTR(6)
#define DMA2_S7NDTR DMA2_SNDTR(7)
/* DMA Stream x peripheral address register (DMA_SxPAR) */
#define DMA_SPAR(port, n) (*(volatile void **)\
(DMA_STREAM(port, n) + 0x08))
#define DMA1_SPAR(n) DMA_SPAR(DMA1, n)
#define DMA2_SPAR(n) DMA_SPAR(DMA2, n)
#define DMA1_S0PAR DMA1_SPAR(0)
#define DMA1_S1PAR DMA1_SPAR(1)
#define DMA1_S2PAR DMA1_SPAR(2)
#define DMA1_S3PAR DMA1_SPAR(3)
#define DMA1_S4PAR DMA1_SPAR(4)
#define DMA1_S5PAR DMA1_SPAR(5)
#define DMA1_S6PAR DMA1_SPAR(6)
#define DMA1_S7PAR DMA1_SPAR(7)
#define DMA2_S0PAR DMA2_SPAR(0)
#define DMA2_S1PAR DMA2_SPAR(1)
#define DMA2_S2PAR DMA2_SPAR(2)
#define DMA2_S3PAR DMA2_SPAR(3)
#define DMA2_S4PAR DMA2_SPAR(4)
#define DMA2_S5PAR DMA2_SPAR(5)
#define DMA2_S6PAR DMA2_SPAR(6)
#define DMA2_S7PAR DMA2_SPAR(7)
/* DMA Stream x memory address 0 register (DMA_SxM0AR) */
#define DMA_SM0AR(port, n) (*(volatile void **) \
(DMA_STREAM(port, n) + 0x0c))
#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n)
#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n)
#define DMA1_S0M0AR DMA1_SM0AR(0)
#define DMA1_S1M0AR DMA1_SM0AR(1)
#define DMA1_S2M0AR DMA1_SM0AR(2)
#define DMA1_S3M0AR DMA1_SM0AR(3)
#define DMA1_S4M0AR DMA1_SM0AR(4)
#define DMA1_S5M0AR DMA1_SM0AR(5)
#define DMA1_S6M0AR DMA1_SM0AR(6)
#define DMA1_S7M0AR DMA1_SM0AR(7)
#define DMA2_S0M0AR DMA2_SM0AR(0)
#define DMA2_S1M0AR DMA2_SM0AR(1)
#define DMA2_S2M0AR DMA2_SM0AR(2)
#define DMA2_S3M0AR DMA2_SM0AR(3)
#define DMA2_S4M0AR DMA2_SM0AR(4)
#define DMA2_S5M0AR DMA2_SM0AR(5)
#define DMA2_S6M0AR DMA2_SM0AR(6)
#define DMA2_S7M0AR DMA2_SM0AR(7)
/* DMA Stream x memory address 1 register (DMA_SxM1AR) */
#define DMA_SM1AR(port, n) (*(volatile void **)\
(DMA_STREAM(port, n) + 0x10))
#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n)
#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n)
#define DMA1_S0M1AR DMA1_SM1AR(0)
#define DMA1_S1M1AR DMA1_SM1AR(1)
#define DMA1_S2M1AR DMA1_SM1AR(2)
#define DMA1_S3M1AR DMA1_SM1AR(3)
#define DMA1_S4M1AR DMA1_SM1AR(4)
#define DMA1_S5M1AR DMA1_SM1AR(5)
#define DMA1_S6M1AR DMA1_SM1AR(6)
#define DMA1_S7M1AR DMA1_SM1AR(7)
#define DMA2_S0M1AR DMA2_SM1AR(0)
#define DMA2_S1M1AR DMA2_SM1AR(1)
#define DMA2_S2M1AR DMA2_SM1AR(2)
#define DMA2_S3M1AR DMA2_SM1AR(3)
#define DMA2_S4M1AR DMA2_SM1AR(4)
#define DMA2_S5M1AR DMA2_SM1AR(5)
#define DMA2_S6M1AR DMA2_SM1AR(6)
#define DMA2_S7M1AR DMA2_SM1AR(7)
/* DMA Stream x FIFO control register (DMA_SxFCR) */
#define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x14)
#define DMA1_SFCR(n) DMA_SFCR(DMA1, n)
#define DMA2_SFCR(n) DMA_SFCR(DMA2, n)
#define DMA1_S0FCR DMA1_SFCR(0)
#define DMA1_S1FCR DMA1_SFCR(1)
#define DMA1_S2FCR DMA1_SFCR(2)
#define DMA1_S3FCR DMA1_SFCR(3)
#define DMA1_S4FCR DMA1_SFCR(4)
#define DMA1_S5FCR DMA1_SFCR(5)
#define DMA1_S6FCR DMA1_SFCR(6)
#define DMA1_S7FCR DMA1_SFCR(7)
#define DMA2_S0FCR DMA2_SFCR(0)
#define DMA2_S1FCR DMA2_SFCR(1)
#define DMA2_S2FCR DMA2_SFCR(2)
#define DMA2_S3FCR DMA2_SFCR(3)
#define DMA2_S4FCR DMA2_SFCR(4)
#define DMA2_S5FCR DMA2_SFCR(5)
#define DMA2_S6FCR DMA2_SFCR(6)
#define DMA2_S7FCR DMA2_SFCR(7)
/* --- DMA Interrupt Flag offset values ------------------------------------- */
/* For API parameters. These are based on every interrupt flag and flag clear
being at the same relative location */
/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group.
@ingroup dma_defines
@{*/
/** Transfer Complete Interrupt Flag */
#define DMA_TCIF (1 << 5)
/** Half Transfer Interrupt Flag */
#define DMA_HTIF (1 << 4)
/** Transfer Error Interrupt Flag */
#define DMA_TEIF (1 << 3)
/** Direct Mode Error Interrupt Flag */
#define DMA_DMEIF (1 << 2)
/** FIFO Error Interrupt Flag */
#define DMA_FEIF (1 << 0)
/**@}*/
/* Offset within interrupt status register to start of stream interrupt flag
* field
*/
#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1))
#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \
DMA_FEIF)
#define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream))
/* --- DMA_LISR values ----------------------------------------------------- */
#define DMA_LISR_FEIF0 (1 << 0)
#define DMA_LISR_DMEIF0 (1 << 2)
#define DMA_LISR_TEIF0 (1 << 3)
#define DMA_LISR_HTIF0 (1 << 4)
#define DMA_LISR_TCIF0 (1 << 5)
#define DMA_LISR_FEIF1 (1 << 6)
#define DMA_LISR_DMEIF1 (1 << 8)
#define DMA_LISR_TEIF1 (1 << 9)
#define DMA_LISR_HTIF1 (1 << 10)
#define DMA_LISR_TCIF1 (1 << 11)
#define DMA_LISR_FEIF2 (1 << 16)
#define DMA_LISR_DMEIF2 (1 << 18)
#define DMA_LISR_TEIF2 (1 << 19)
#define DMA_LISR_HTIF2 (1 << 20)
#define DMA_LISR_TCIF2 (1 << 21)
#define DMA_LISR_FEIF3 (1 << 22)
#define DMA_LISR_DMEIF3 (1 << 24)
#define DMA_LISR_TEIF3 (1 << 25)
#define DMA_LISR_HTIF3 (1 << 26)
#define DMA_LISR_TCIF3 (1 << 27)
/* --- DMA_HISR values ----------------------------------------------------- */
#define DMA_HISR_FEIF4 (1 << 0)
#define DMA_HISR_DMEIF4 (1 << 2)
#define DMA_HISR_TEIF4 (1 << 3)
#define DMA_HISR_HTIF4 (1 << 4)
#define DMA_HISR_TCIF4 (1 << 5)
#define DMA_HISR_FEIF5 (1 << 6)
#define DMA_HISR_DMEIF5 (1 << 8)
#define DMA_HISR_TEIF5 (1 << 9)
#define DMA_HISR_HTIF5 (1 << 10)
#define DMA_HISR_TCIF5 (1 << 11)
#define DMA_HISR_FEIF6 (1 << 16)
#define DMA_HISR_DMEIF6 (1 << 18)
#define DMA_HISR_TEIF6 (1 << 19)
#define DMA_HISR_HTIF6 (1 << 20)
#define DMA_HISR_TCIF6 (1 << 21)
#define DMA_HISR_FEIF7 (1 << 22)
#define DMA_HISR_DMEIF7 (1 << 24)
#define DMA_HISR_TEIF7 (1 << 25)
#define DMA_HISR_HTIF7 (1 << 26)
#define DMA_HISR_TCIF7 (1 << 27)
/* --- DMA_LIFCR values ----------------------------------------------------- */
#define DMA_LIFCR_CFEIF0 (1 << 0)
#define DMA_LIFCR_CDMEIF0 (1 << 2)
#define DMA_LIFCR_CTEIF0 (1 << 3)
#define DMA_LIFCR_CHTIF0 (1 << 4)
#define DMA_LIFCR_CTCIF0 (1 << 5)
#define DMA_LIFCR_CFEIF1 (1 << 6)
#define DMA_LIFCR_CDMEIF1 (1 << 8)
#define DMA_LIFCR_CTEIF1 (1 << 9)
#define DMA_LIFCR_CHTIF1 (1 << 10)
#define DMA_LIFCR_CTCIF1 (1 << 11)
#define DMA_LIFCR_CFEIF2 (1 << 16)
#define DMA_LIFCR_CDMEIF2 (1 << 18)
#define DMA_LIFCR_CTEIF2 (1 << 19)
#define DMA_LIFCR_CHTIF2 (1 << 20)
#define DMA_LIFCR_CTCIF2 (1 << 21)
#define DMA_LIFCR_CFEIF3 (1 << 22)
#define DMA_LIFCR_CDMEIF3 (1 << 24)
#define DMA_LIFCR_CTEIF3 (1 << 25)
#define DMA_LIFCR_CHTIF3 (1 << 26)
#define DMA_LIFCR_CTCIF3 (1 << 27)
/* --- DMA_HIFCR values ----------------------------------------------------- */
#define DMA_HIFCR_CFEIF4 (1 << 0)
#define DMA_HIFCR_CDMEIF4 (1 << 2)
#define DMA_HIFCR_CTEIF4 (1 << 3)
#define DMA_HIFCR_CHTIF4 (1 << 4)
#define DMA_HIFCR_CTCIF4 (1 << 5)
#define DMA_HIFCR_CFEIF5 (1 << 6)
#define DMA_HIFCR_CDMEIF5 (1 << 8)
#define DMA_HIFCR_CTEIF5 (1 << 9)
#define DMA_HIFCR_CHTIF5 (1 << 10)
#define DMA_HIFCR_CTCIF5 (1 << 11)
#define DMA_HIFCR_CFEIF6 (1 << 16)
#define DMA_HIFCR_CDMEIF6 (1 << 18)
#define DMA_HIFCR_CTEIF6 (1 << 19)
#define DMA_HIFCR_CHTIF6 (1 << 20)
#define DMA_HIFCR_CTCIF6 (1 << 21)
#define DMA_HIFCR_CFEIF7 (1 << 22)
#define DMA_HIFCR_CDMEIF7 (1 << 24)
#define DMA_HIFCR_CTEIF7 (1 << 25)
#define DMA_HIFCR_CHTIF7 (1 << 26)
#define DMA_HIFCR_CTCIF7 (1 << 27)
/* --- DMA_SxCR values ----------------------------------------------------- */
/* EN: Stream enable */
#define DMA_SxCR_EN (1 << 0)
/* DMEIE: Direct Mode error interrupt enable */
#define DMA_SxCR_DMEIE (1 << 1)
/* TEIE: Transfer error interrupt enable */
#define DMA_SxCR_TEIE (1 << 2)
/* HTIE: Half transfer interrupt enable */
#define DMA_SxCR_HTIE (1 << 3)
/* TCIE: Transfer complete interrupt enable */
#define DMA_SxCR_TCIE (1 << 4)
/* PFCTRL: Peripheral Flow Controller */
#define DMA_SxCR_PFCTRL (1 << 5)
/* DIR[7:6]: Data transfer direction */
/** @defgroup dma_st_dir DMA Stream Data transfer direction
@ingroup dma_defines
@{*/
#define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0 << 6)
#define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1 << 6)
#define DMA_SxCR_DIR_MEM_TO_MEM (2 << 6)
/**@}*/
#define DMA_SxCR_DIR_SHIFT 6
#define DMA_SxCR_DIR_MASK (3 << 6)
/* CIRC: Circular mode */
#define DMA_SxCR_CIRC (1 << 8)
/* PINC: Peripheral increment mode */
#define DMA_SxCR_PINC (1 << 9)
/* MINC: Memory increment mode */
#define DMA_SxCR_MINC (1 << 10)
/* PSIZE[12:11]: Peripheral size */
/** @defgroup dma_st_perwidth DMA Stream Peripheral Word Width
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_SxCR_PSIZE_8BIT (0 << 11)
#define DMA_SxCR_PSIZE_16BIT (1 << 11)
#define DMA_SxCR_PSIZE_32BIT (2 << 11)
/**@}*/
#define DMA_SxCR_PSIZE_SHIFT 11
#define DMA_SxCR_PSIZE_MASK (3 << 11)
/* MSIZE[14:13]: Memory size */
/** @defgroup dma_st_memwidth DMA Stream Memory Word Width
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_SxCR_MSIZE_8BIT (0 << 13)
#define DMA_SxCR_MSIZE_16BIT (1 << 13)
#define DMA_SxCR_MSIZE_32BIT (2 << 13)
/**@}*/
#define DMA_SxCR_MSIZE_SHIFT 13
#define DMA_SxCR_MSIZE_MASK (3 << 13)
/* PINCOS: Peripheral increment offset size */
#define DMA_SxCR_PINCOS (1 << 15)
/* PL[17:16]: Stream priority level */
/** @defgroup dma_st_pri DMA Stream Priority Levels
@ingroup dma_defines
@{*/
#define DMA_SxCR_PL_LOW (0 << 16)
#define DMA_SxCR_PL_MEDIUM (1 << 16)
#define DMA_SxCR_PL_HIGH (2 << 16)
#define DMA_SxCR_PL_VERY_HIGH (3 << 16)
/**@}*/
#define DMA_SxCR_PL_SHIFT 16
#define DMA_SxCR_PL_MASK (3 << 16)
/* DBM: Double buffered mode */
#define DMA_SxCR_DBM (1 << 18)
/* CT: Current target (in double buffered mode) */
#define DMA_SxCR_CT (1 << 19)
/* Bit 20 reserved */
/* PBURST[13:12]: Peripheral Burst Configuration */
/** @defgroup dma_pburst DMA Peripheral Burst Length
@ingroup dma_defines
@{*/
#define DMA_SxCR_PBURST_SINGLE (0 << 21)
#define DMA_SxCR_PBURST_INCR4 (1 << 21)
#define DMA_SxCR_PBURST_INCR8 (2 << 21)
#define DMA_SxCR_PBURST_INCR16 (3 << 21)
/**@}*/
#define DMA_SxCR_PBURST_SHIFT 21
#define DMA_SxCR_PBURST_MASK (3 << 21)
/* MBURST[13:12]: Memory Burst Configuration */
/** @defgroup dma_mburst DMA Memory Burst Length
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_SxCR_MBURST_SINGLE (0 << 23)
#define DMA_SxCR_MBURST_INCR4 (1 << 23)
#define DMA_SxCR_MBURST_INCR8 (2 << 23)
#define DMA_SxCR_MBURST_INCR16 (3 << 23)
/**@}*/
#define DMA_SxCR_MBURST_SHIFT 23
#define DMA_SxCR_MBURST_MASK (3 << 23)
/* CHSEL[25:27]: Channel Select */
/** @defgroup dma_ch_sel DMA Channel Select
@ingroup dma_defines
@{*/
#define DMA_SxCR_CHSEL_0 (0 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_1 (1 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_2 (2 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_3 (3 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_4 (4 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_5 (5 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_6 (6 << DMA_SxCR_CHSEL_SHIFT)
#define DMA_SxCR_CHSEL_7 (7 << DMA_SxCR_CHSEL_SHIFT)
/**@}*/
#define DMA_SxCR_CHSEL_SHIFT 25
#define DMA_SxCR_CHSEL_MASK (7 << 25)
#define DMA_SxCR_CHSEL(n) (n << DMA_SxCR_CHSEL_SHIFT)
/* Reserved [31:28] */
/* --- DMA_SxNDTR values --------------------------------------------------- */
/* DMA_SxNDTR[15:0]: Number of data register. */
/* --- DMA_SxPAR values ---------------------------------------------------- */
/* DMA_SxPAR[31:0]: Peripheral address register. */
/* --- DMA_SxM0AR values --------------------------------------------------- */
/* DMA_SxM0AR[31:0]: Memory 0 address register. */
/* --- DMA_SxM1AR values --------------------------------------------------- */
/* DMA_SxM1AR[31:0]: Memory 1 address register. */
/* --- DMA_SxFCR values ---------------------------------------------------- */
/* FTH[1:0]: FIFO Threshold selection */
/** @defgroup dma_fifo_thresh FIFO Threshold selection
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_SxFCR_FTH_1_4_FULL (0 << 0)
#define DMA_SxFCR_FTH_2_4_FULL (1 << 0)
#define DMA_SxFCR_FTH_3_4_FULL (2 << 0)
#define DMA_SxFCR_FTH_4_4_FULL (3 << 0)
/**@}*/
#define DMA_SxFCR_FTH_SHIFT 0
#define DMA_SxFCR_FTH_MASK (3 << 0)
/* DMDIS: Direct Mode disable */
#define DMA_SxFCR_DMDIS (1 << 2)
/* FS[5:3]: FIFO Status */
/** @defgroup dma_fifo_status FIFO Status
@ingroup STM32F4xx_dma_defines
@{*/
#define DMA_SxFCR_FS_LT_1_4_FULL (0 << 0)
#define DMA_SxFCR_FS_LT_2_4_FULL (1 << 0)
#define DMA_SxFCR_FS_LT_3_4_FULL (2 << 0)
#define DMA_SxFCR_FS_LT_4_4_FULL (3 << 0)
#define DMA_SxFCR_FS_FULL (4 << 3)
#define DMA_SxFCR_FS_EMPTY (5 << 3)
/**@}*/
#define DMA_SxFCR_FS_SHIFT 3
#define DMA_SxFCR_FS_MASK (7 << 3)
/* [6]: reserved */
/* FEIE[7]: FIFO error interrupt enable */
#define DMA_SxFCR_FEIE (1 << 7)
/* [31:8]: Reserved */
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
/*
* Note: The F2 and F4 series have a completely new DMA peripheral with
* different configuration options.
*/
void dma_stream_reset(uint32_t dma, uint8_t stream);
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream,
uint32_t interrupts);
bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt);
void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction);
void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio);
void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size);
void dma_set_peripheral_size(uint32_t dma, uint8_t stream,
uint32_t peripheral_size);
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream);
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream);
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream);
void dma_enable_circular_mode(uint32_t dma, uint8_t stream);
void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel);
void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst);
void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst);
void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory);
uint8_t dma_get_target(uint32_t dma, uint8_t stream);
void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream);
void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream);
void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream);
void dma_set_dma_flow_control(uint32_t dma, uint8_t stream);
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream);
uint32_t dma_fifo_status(uint32_t dma, uint8_t stream);
void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream);
void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream);
void dma_enable_direct_mode(uint32_t dma, uint8_t stream);
void dma_enable_fifo_mode(uint32_t dma, uint8_t stream);
void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold);
void dma_enable_stream(uint32_t dma, uint8_t stream);
void dma_disable_stream(uint32_t dma, uint8_t stream);
void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address);
void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address);
void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address);
void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number);
END_DECLS
/**@}*/
#endif
/** @cond */
#else
#warning "dma_common_f24.h should not be included explicitly, only via dma.h"
#endif
/** @endcond */

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/** @addtogroup dma_defines
@author @htmlonly &copy; @endhtmlonly 2010
Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012
Piotr Esden-Tempski <piotr@esden.net>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H
The order of header inclusion is important. dma.h includes the device
specific memorymap.h header before including this header file.*/
/** @cond */
#ifdef LIBOPENCM3_DMA_H
/** @endcond */
#ifndef LIBOPENCM3_DMA_COMMON_F13_H
#define LIBOPENCM3_DMA_COMMON_F13_H
#include <libopencm3/cm3/common.h>
/* --- Convenience macros -------------------------------------------------- */
/* DMA register base adresses (for convenience) */
#define DMA1 DMA1_BASE
#define DMA2 DMA2_BASE
/* --- DMA registers ------------------------------------------------------- */
/* DMA interrupt status register (DMAx_ISR) */
#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00)
#define DMA1_ISR DMA_ISR(DMA1)
#define DMA2_ISR DMA_ISR(DMA2)
/* DMA interrupt flag clear register (DMAx_IFCR) */
#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04)
#define DMA1_IFCR DMA_IFCR(DMA1)
#define DMA2_IFCR DMA_IFCR(DMA2)
/* DMA channel configuration register (DMAx_CCRy) */
#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \
(0x14 * ((channel) - 1)))
#define DMA1_CCR(channel) DMA_CCR(DMA1, channel)
#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1)
#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2)
#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3)
#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4)
#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5)
#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6)
#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7)
#define DMA2_CCR(channel) DMA_CCR(DMA2, channel)
#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1)
#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2)
#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3)
#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4)
#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5)
/* DMA number of data register (DMAx_CNDTRy) */
#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \
(0x14 * ((channel) - 1)))
#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel)
#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1)
#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2)
#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3)
#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4)
#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5)
#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6)
#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7)
#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel)
#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1)
#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2)
#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3)
#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4)
#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5)
/* DMA peripheral address register (DMAx_CPARy) */
#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \
(0x14 * ((channel) - 1)))
#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel)
#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1)
#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2)
#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3)
#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4)
#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5)
#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6)
#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7)
#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel)
#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1)
#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2)
#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3)
#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4)
#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5)
/* DMA memory address register (DMAx_CMARy) */
#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \
(0x14 * ((channel) - 1)))
#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel)
#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1)
#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2)
#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3)
#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4)
#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5)
#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6)
#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7)
#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel)
#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1)
#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2)
#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3)
#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4)
#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5)
/* --- DMA_ISR values ------------------------------------------------------ */
/* --- DMA Interrupt Flag offset values ------------------------------------- */
/* These are based on every interrupt flag and flag clear being at the same
* relative location
*/
/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag
group.
@ingroup dma_defines
@{*/
/** Transfer Error Interrupt Flag */
#define DMA_TEIF (1 << 3)
/** Half Transfer Interrupt Flag */
#define DMA_HTIF (1 << 2)
/** Transfer Complete Interrupt Flag */
#define DMA_TCIF (1 << 1)
/** Global Interrupt Flag */
#define DMA_GIF (1 << 0)
/**@}*/
/* Offset within interrupt status register to start of channel interrupt flag
* field
*/
#define DMA_FLAG_OFFSET(channel) (4*(channel - 1))
#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \
DMA_GIF)
#define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel))
/* TEIF: Transfer error interrupt flag */
#define DMA_ISR_TEIF_BIT DMA_TEIF
#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)
#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)
#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3)
#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4)
#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5)
#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6)
#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7)
/* HTIF: Half transfer interrupt flag */
#define DMA_ISR_HTIF_BIT DMA_HTIF
#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)
#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)
#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3)
#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4)
#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5)
#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6)
#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7)
/* TCIF: Transfer complete interrupt flag */
#define DMA_ISR_TCIF_BIT DMA_TCIF
#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)
#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)
#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3)
#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4)
#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5)
#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6)
#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7)
/* GIF: Global interrupt flag */
#define DMA_ISR_GIF_BIT DMA_GIF
#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)
#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)
#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3)
#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4)
#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5)
#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6)
#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7)
/* --- DMA_IFCR values ----------------------------------------------------- */
/* CTEIF: Transfer error clear */
#define DMA_IFCR_CTEIF_BIT DMA_TEIF
#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3)
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4)
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5)
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6)
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7)
/* CHTIF: Half transfer clear */
#define DMA_IFCR_CHTIF_BIT DMA_HTIF
#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3)
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4)
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5)
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6)
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7)
/* CTCIF: Transfer complete clear */
#define DMA_IFCR_CTCIF_BIT DMA_TCIF
#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3)
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4)
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5)
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6)
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7)
/* CGIF: Global interrupt clear */
#define DMA_IFCR_CGIF_BIT DMA_GIF
#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3)
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4)
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5)
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6)
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7)
/* Clear interrupts mask */
#define DMA_IFCR_CIF_BIT 0xF
#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << \
(DMA_FLAG_OFFSET(channel)))
#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1)
#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2)
#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3)
#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4)
#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5)
#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6)
#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7)
/* --- DMA_CCRx generic values --------------------------------------------- */
/* MEM2MEM: Memory to memory mode */
#define DMA_CCR_MEM2MEM (1 << 14)
/* PL[13:12]: Channel priority level */
/** @defgroup dma_ch_pri DMA Channel Priority Levels
@ingroup dma_defines
@{*/
#define DMA_CCR_PL_LOW (0x0 << 12)
#define DMA_CCR_PL_MEDIUM (0x1 << 12)
#define DMA_CCR_PL_HIGH (0x2 << 12)
#define DMA_CCR_PL_VERY_HIGH (0x3 << 12)
/**@}*/
#define DMA_CCR_PL_MASK (0x3 << 12)
#define DMA_CCR_PL_SHIFT 12
/* MSIZE[11:10]: Memory size */
/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width
@ingroup dma_defines
@{*/
#define DMA_CCR_MSIZE_8BIT (0x0 << 10)
#define DMA_CCR_MSIZE_16BIT (0x1 << 10)
#define DMA_CCR_MSIZE_32BIT (0x2 << 10)
/**@}*/
#define DMA_CCR_MSIZE_MASK (0x3 << 10)
#define DMA_CCR_MSIZE_SHIFT 10
/* PSIZE[9:8]: Peripheral size */
/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width
@ingroup dma_defines
@{*/
#define DMA_CCR_PSIZE_8BIT (0x0 << 8)
#define DMA_CCR_PSIZE_16BIT (0x1 << 8)
#define DMA_CCR_PSIZE_32BIT (0x2 << 8)
/**@}*/
#define DMA_CCR_PSIZE_MASK (0x3 << 8)
#define DMA_CCR_PSIZE_SHIFT 8
/* MINC: Memory increment mode */
#define DMA_CCR_MINC (1 << 7)
/* PINC: Peripheral increment mode */
#define DMA_CCR_PINC (1 << 6)
/* CIRC: Circular mode */
#define DMA_CCR_CIRC (1 << 5)
/* DIR: Data transfer direction */
#define DMA_CCR_DIR (1 << 4)
/* TEIE: Transfer error interrupt enable */
#define DMA_CCR_TEIE (1 << 3)
/* HTIE: Half transfer interrupt enable */
#define DMA_CCR_HTIE (1 << 2)
/* TCIE: Transfer complete interrupt enable */
#define DMA_CCR_TCIE (1 << 1)
/* EN: Channel enable */
#define DMA_CCR_EN (1 << 0)
/* --- DMA_CNDTRx values --------------------------------------------------- */
/* NDT[15:0]: Number of data to transfer */
/* --- DMA_CPARx values ---------------------------------------------------- */
/* PA[31:0]: Peripheral address */
/* --- DMA_CMARx values ---------------------------------------------------- */
/* MA[31:0]: Memory address */
/* --- Generic values ------------------------------------------------------ */
/** @defgroup dma_ch DMA Channel Number
@ingroup dma_defines
@{*/
#define DMA_CHANNEL1 1
#define DMA_CHANNEL2 2
#define DMA_CHANNEL3 3
#define DMA_CHANNEL4 4
#define DMA_CHANNEL5 5
#define DMA_CHANNEL6 6
#define DMA_CHANNEL7 7
/**@}*/
/* --- function prototypes ------------------------------------------------- */
BEGIN_DECLS
void dma_channel_reset(uint32_t dma, uint8_t channel);
void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel,
uint32_t interrupts);
bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupts);
void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel);
void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio);
void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size);
void dma_set_peripheral_size(uint32_t dma, uint8_t channel,
uint32_t peripheral_size);
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_circular_mode(uint32_t dma, uint8_t channel);
void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel);
void dma_set_read_from_memory(uint32_t dma, uint8_t channel);
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel);
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel);
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel);
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel);
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel);
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel);
void dma_enable_channel(uint32_t dma, uint8_t channel);
void dma_disable_channel(uint32_t dma, uint8_t channel);
void dma_set_peripheral_address(uint32_t dma, uint8_t channel,
uint32_t address);
void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address);
void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number);
END_DECLS
#endif
/** @cond */
#else
#warning "dma_common_f13.h should not be included explicitly, only via dma.h"
#endif
/** @endcond */
/**@}*/

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @cond */
#if defined(LIBOPENCM3_EXTI_H)
/** @endcond */
#ifndef LIBOPENCM3_EXTI_COMMON_ALL_H
#define LIBOPENCM3_EXTI_COMMON_ALL_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/* --- EXTI registers ------------------------------------------------------ */
#define EXTI_IMR MMIO32(EXTI_BASE + 0x00)
#define EXTI_EMR MMIO32(EXTI_BASE + 0x04)
#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08)
#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c)
#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10)
#define EXTI_PR MMIO32(EXTI_BASE + 0x14)
/* EXTI number definitions */
#define EXTI0 (1 << 0)
#define EXTI1 (1 << 1)
#define EXTI2 (1 << 2)
#define EXTI3 (1 << 3)
#define EXTI4 (1 << 4)
#define EXTI5 (1 << 5)
#define EXTI6 (1 << 6)
#define EXTI7 (1 << 7)
#define EXTI8 (1 << 8)
#define EXTI9 (1 << 9)
#define EXTI10 (1 << 10)
#define EXTI11 (1 << 11)
#define EXTI12 (1 << 12)
#define EXTI13 (1 << 13)
#define EXTI14 (1 << 14)
#define EXTI15 (1 << 15)
#define EXTI16 (1 << 16)
#define EXTI17 (1 << 17)
#define EXTI18 (1 << 18)
#define EXTI19 (1 << 19)
/* Trigger types */
enum exti_trigger_type {
EXTI_TRIGGER_RISING,
EXTI_TRIGGER_FALLING,
EXTI_TRIGGER_BOTH,
};
BEGIN_DECLS
void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig);
void exti_enable_request(uint32_t extis);
void exti_disable_request(uint32_t extis);
void exti_reset_request(uint32_t extis);
void exti_select_source(uint32_t exti, uint32_t gpioport);
uint32_t exti_get_flag_status(uint32_t exti);
END_DECLS
#endif
/** @cond */
#else
#warning "exti_common_all.h should not be included directly, only via exti.h"
#endif
/** @endcond */

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @cond */
#if defined(LIBOPENCM3_EXTI_H)
/** @endcond */
#ifndef LIBOPENCM3_EXTI_COMMON_F24_H
#define LIBOPENCM3_EXTI_COMMON_F24_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/common/exti_common_all.h>
/* EXTI number definitions */
#define EXTI20 (1 << 20)
#define EXTI21 (1 << 21)
#define EXTI22 (1 << 22)
#endif
/** @cond */
#else
#warning "exti_common_f24.h should not be included directly, only via exti.h"
#endif
/** @endcond */

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/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* For details see:
* PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming
* September 2011, Doc ID 018520 Rev 1
* https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf
*/
/** @cond */
#ifdef LIBOPENCM3_FLASH_H
/** @endcond */
#ifndef LIBOPENCM3_FLASH_COMMON_F234_H
#define LIBOPENCM3_FLASH_COMMON_F234_H
#include <libopencm3/cm3/common.h>
/* --- FLASH registers ----------------------------------------------------- */
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
/* --- FLASH_ACR values ---------------------------------------------------- */
#define FLASH_ACR_LATENCY_0WS 0x00
#define FLASH_ACR_LATENCY_1WS 0x01
#define FLASH_ACR_LATENCY_2WS 0x02
#define FLASH_ACR_LATENCY_3WS 0x03
#define FLASH_ACR_LATENCY_4WS 0x04
#define FLASH_ACR_LATENCY_5WS 0x05
#define FLASH_ACR_LATENCY_6WS 0x06
#define FLASH_ACR_LATENCY_7WS 0x07
/* --- FLASH_SR values ----------------------------------------------------- */
/* --- FLASH_CR values ----------------------------------------------------- */
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
/* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS
void flash_set_ws(uint32_t ws);
void flash_unlock(void);
void flash_lock(void);
void flash_clear_pgperr_flag(void);
void flash_clear_eop_flag(void);
void flash_clear_bsy_flag(void);
void flash_clear_status_flags(void);
void flash_wait_for_last_operation(void);
END_DECLS
#endif
/** @cond */
#else
#warning "flash_common_f234.h should not be included direcitly,"
#warning "only via flash.h"
#endif
/** @endcond */

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