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This commit is contained in:
RocketGod
2022-09-22 09:26:57 -07:00
parent fee0ab05fd
commit 957ea3d712
4511 changed files with 1943182 additions and 0 deletions
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18
Software/portapack-mayhem/hackrf/firmware/cpld/README Normal file
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The primary CPLD image is: sgpio_if/default.xsvf
This is a binary file built from HDL source in sgpio_if. You do not need
Xilinx tools unless you want to make your own modifications.
CPLD images are automatically included in HackRF firmware. You do not normally
need to update the bitstream stored in the CPLD's flash memory as it is
superseded by the image loaded into SRAM by the firmware.
If you want to update the bitstream in CPLD flash for some reason, first update
the firmware, libhackrf, and hackrf-tools.
Then:
$ hackrf_cpldjtag -x sgpio_if/default.xsvf
After a few seconds, three LEDs should start blinking. This indicates that the
CPLD has been programmed successfully. Reset the HackRF device by pressing the
RESET button or by unplugging it and plugging it back in.

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Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_debug/Makefile Normal file
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# xst -intstyle ise -ifn top.xst -ofn top.syr
# ngdbuild -intstyle ise -dd _ngo -uc top.ucf -p xc2c64a-VQ100-7 top.ngc top.ngd
# cpldfit -intstyle ise -p xc2c64a-7-VQ100 -ofmt vhdl -optimize density -loc on -slew slow -init low -inputs 32 -pterms 28 -unused pullup -terminate float -iostd LVCMOS33 top.ngd
# tsim -intstyle ise top top.nga
# taengine -intstyle ise -f top -l top.tim -e {taengine.err}
# hprep6 -s IEEE1149 -i top
# vhdtdtfi -prj sgpio_debug -o top.vhi -module top -template /opt/Xilinx/14.7/ISE_DS/ISE/data/vhdlinst.tft -deleteonerror -lib work top.vhd
DESIGN=top
DEVICE=xc2c64a
DEVICE_SPEED=7
DEVICE_PACKAGE=VQ100
OUTFILES_XST=$(DESIGN).ngc $(DESIGN).syr $(DESIGN).ngr $(DESIGN)_xst.xrpt $(DESIGN).lso _xmsgs/xst.xmsgs
OUTFILES_NGDBUILD=$(DESIGN).ngd $(DESIGN).bld $(DESIGN)_ngdbuild.xrpt _xmsgs/ngdbuild.xmsgs _ngo/netlist.lst xlnx_auto_0_xdb/cst.xbcd
OUTFILES_CPLDFIT=$(DESIGN).vm6 $(DESIGN).tspec t6.phd t6.dat t55.phd t55.dat t1.phd t1.dat $(DESIGN).log $(DESIGN).chk $(DESIGN).rpt $(DESIGN).xml $(DESIGN)_build.xml $(DESIGN).pad $(DESIGN)_pad.csv $(DESIGN).pnx $(DESIGN).mfd $(DESIGN).cxt $(DESIGN).gyd _xmsgs/cpldfit.xmsgs
OUTFILES_HPREP6=$(DESIGN).jed tmperr.err _xmsgs/hprep6.xmsgs
OUTFILES_IMPACT_SVF=default.svf _impactbatch.log
OUTFILES_IMPACT_XSVF=default.xsvf _impactbatch.log
all: default.svf default.xsvf
$(DESIGN).ngc: $(DESIGN).xst $(DESIGN).prj
mkdir -p xst/projnav.tmp
xst -intstyle ise -ifn $(DESIGN).xst -ofn $(DESIGN).syr
$(DESIGN).ngd: $(DESIGN).ngc $(DESIGN).ucf
ngdbuild -intstyle ise -dd _ngo -uc $(DESIGN).ucf -p $(DEVICE)-$(DEVICE_PACKAGE)-$(DEVICE_SPEED) $(DESIGN).ngc $(DESIGN).ngd
$(DESIGN).vm6: $(DESIGN).ngd
cpldfit -intstyle ise -p $(DEVICE)-$(DEVICE_SPEED)-$(DEVICE_PACKAGE) -ofmt vhdl -optimize speed -loc on -slew slow -init low -inputs 32 -pterms 36 -unused pullup -terminate float -iostd LVCMOS33 $(DESIGN).ngd
$(DESIGN).jed: $(DESIGN).vm6
hprep6 -s IEEE1149 -i $(DESIGN).vm6
default.svf: $(DESIGN).jed batch_svf
impact -batch batch_svf
default.xsvf: $(DESIGN).jed batch_xsvf
impact -batch batch_xsvf
.PHONY: clean
clean:
rm -f $(OUTFILES_XST) $(OUTFILES_NGDBUILD) $(OUTFILES_CPLDFIT) $(OUTFILES_HPREP6) $(OUTFILES_IMPACT_SVF) $(OUTFILES_IMPACT_XSVF)
rm -rf xlnx_auto_0_xdb/ _ngo/ _xmsgs/ xst/

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Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_debug/README.md Normal file
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CPLD interface between LPC43xx microcontroller SGPIO peripheral and MAX5864
RF codec.
CPLD-based triggered capture
============================
To build this VHDL project and produce an SVF file for flashing the CPLD:
* Xilinx WebPACK 13.4 for Windows or Linux.
Generate an XSVF
================
After generating a programming file:
* In the ISE Project Navigator, "Processes: top - Behavioral" pane, double-click "Configure Target Device".
* Click "OK" to open iMPACT.
* Ctrl-N to create a "New Project".
* "Yes" to automatically create and save a project file.
* Select "Prepare a Boundary-Scan File", choose "XSVF".
* Select file name "default.xsvf".
* Click "OK" to start adding devices.
* Assign new configuration file: "top.jed".
* Right-click the "xc2c64a top.jed" icon and select "Erase". Accept defaults.
* Right-click the "xc2c64a top.jed" icon and select "Program".
* Right-click the "xc2c64a top.jed" icon and select "Verify".
* Choose menu "Output" -> "XSVF File" -> "Stop Writing to XSVF File".
* Close iMPACT.
To Program
==========
$ hackrf_cpldjtag -x default.xsvf

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Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_debug/batch_svf Normal file
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setMode -bscan
setCable -port svf -file default.svf
addDevice -p 1 -file top.jed
Erase -p 1
Program -p 1 -e -v
Verify -p 1
quit

7
Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_debug/batch_xsvf Normal file
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setMode -bscan
setCable -port xsvf -file default.xsvf
addDevice -p 1 -file top.jed
Erase -p 1
Program -p 1 -e -v
Verify -p 1
quit

BIN
Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_debug/default.xsvf Normal file
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Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_debug/sgpio_debug.xise Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="36" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="Default.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc2c64a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="CoolRunner2 CPLDs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-7" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS33" xil_pn:valueState="non-default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Speed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|Behavioral" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Output Slew Rate" xil_pn:value="Slow" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="top" xil_pn:valueState="default"/>
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<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/top_tb" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="top.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Pullup" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="E:/Xilinx/14.1/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|top_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="sgpio_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xbr" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-04-29T12:49:49" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8998E598855F452AB5BAE34A005D4FD5" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

757
Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_debug/top.jed Normal file
View File

@ -0,0 +1,757 @@
Programmer Jedec Bit Map
Date Extracted: Mon Jan 20 17:17:07 2020
QF25812*
QP100*
QV0*
F0*
X0*
J0 0*
N VERSION P.20131013*
N DEVICE XC2C64A-7-VQ100*
Note Block 0 *
Note Block 0 ZIA *
L000000 1110110011111111*
L000016 1110101011111111*
L000032 1110101011111111*
L000048 1110101011111111*
L000064 1110110011111111*
L000080 1110101011111111*
L000096 1110101011111111*
L000112 1110011011111111*
L000128 1110101011111111*
L000144 1110101011111111*
L000160 1110011011111111*
L000176 1111111111111111*
L000192 1110110011111111*
L000208 1110101011111111*
L000224 1110110011111111*
L000240 1111111011110011*
L000256 1110101011111111*
L000272 1111111111111111*
L000288 1111111111111111*
L000304 1110110011111111*
L000320 1110110011111111*
L000336 1111111011010111*
L000352 1111111011100111*
L000368 1111111111111111*
L000384 1111111011100111*
L000400 1111111111111111*
L000416 1110110011111111*
L000432 1110110011111111*
L000448 1111111111111111*
L000464 1111111111111111*
L000480 1111111111111111*
L000496 1111111111111111*
L000512 1111111011010111*
L000528 1111111111111111*
L000544 1111111111111111*
L000560 1111111011010111*
L000576 1111111111111111*
L000592 1111111111111111*
L000608 1111111111111111*
L000624 1111111111111111*
Note Block 0 PLA AND array *
L000640 11111111111111111111111110111111111111111111111111111111111111111111111011111111*
L000720 11111110101111111111111111111111111111111111111111111111111111111111110111111111*
L000800 10111111111111111111111111111111111111111111111111111111111111111111111111111111*
L000880 10111111111111111111111111110111111111111111111111111111111111111111110111111111*
L000960 01111111111111111111111111111011111111111111111111111111111111111111110111111111*
L001040 11111111111111110111111111111111111111111111111111111111111111111111111011111111*
L001120 01111111111111111111111111110111111111111111111111111111111111111111110111111111*
L001200 11111111111101111111111111111111111111111111111111111111111111111111111011111111*
L001280 01111111111111111111111111110111111111011111111111111111111111111111110111111111*
L001360 11111111111111111111111111011111111111111111111111111111111111111111111011111111*
L001440 01101111111111111111111111111111111111111111111111111111111111111111111111111111*
L001520 11111111111111110111111111111011111111111111111111111111111111111111111111111111*
L001600 11111111111111111011111111110111111111111111111111111111111111111111111111111111*
L001680 11111111111111111111111111111111111111111101111111111111111111111111111111111111*
L001760 11111111111101111111111111111111111111101111111111111111111111111111111111111111*
L001840 11111111111110111111111111111111111111011111111111111111111111111111111111111111*
L001920 11111111111111111111111111111111111111111111111111111111111111110111111111111111*
L002000 11111111111111111111111111011111111111111011111111111111111111111111111111111111*
L002080 11111111111111111111111111101111111111110111111111111111111111111111111111111111*
L002160 11111111111111111111111111111111111111111111111101111111111111111111111111111111*
L002240 11111111111111101101111111111111111111111111111111111111111111111111111111111111*
L002320 01111111111111111111111111110111111111010111111111111111111111111111110111111111*
L002400 11111111111111111111111111111111111111111111011111111111111111111111111111111111*
L002480 11111111111111111101111111111111111111111111111111111111111111111111111011111111*
L002560 01111111111111011111111111110111111111010111111111111111111111111111110111111111*
L002640 11111111111111111111111111111101111111111111111111111111111111111111111111111111*
L002720 11110111111111111111111111111111111111111111111111111111111111111111111011111111*
L002800 01111111111111011111011111110111111111010111111111111111111111111111110111111111*
L002880 11111111111111111111111111111111111111111111111111110111111111111111111011111111*
L002960 01111111110111011111011111110111111111010111111111111111111111111111110111111111*
L003040 11111111111111111111111111111111111111111111111111111101111111111111111011111111*
L003120 11111111111111111111111111111111011111111111111111111111111111111111110111111111*
L003200 10011111111111111111111111111111111111111111111111111111111111111111111111111111*
L003280 11111111111111011110111111111111111111111111111111111111111111111111111111111111*
L003360 11111111110111111111111111111111111111111111111111111111111111111111110111111111*
L003440 11110111111111111111101111111111111111111111111111111111111111111111111111111111*
L003520 11111011111111111111011111111111111111111111111111111111111111111111111111111111*
L003600 11111111111111111111011111111111111111111111111111111111111111111111110111111111*
L003680 11111111111011111111111111111111111111111111111111110111111111111111111111111111*
L003760 11111111110111111111111111111111111111111111111111111011111111111111111111111111*
L003840 11111111111111011111111111111111111111111111111111111111111111111111110111111111*
L003920 11111111111111111111111111111111101111111111111111111101111111111111111111111111*
L004000 11111111111111111111111111111111011111111111111111111110111111111111111111111111*
L004080 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004160 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004240 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004320 11111111111111111111111111111111111111110111111111111111111111111111110111111111*
L004400 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004480 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004560 11111111111111111111111111111111111111011111111111111111111111111111110111111111*
L004640 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004720 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004800 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004880 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004960 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L005040 11111111111111111111111111111111111111111111111111111111111111111111110111111111*
Note Block 0 PLA OR array *
L005120 0111111111111111*
L005136 0111111111111111*
L005152 1111111111111110*
L005168 1111111111111101*
L005184 1111111111111101*
L005200 1111111111111101*
L005216 1111111111111011*
L005232 1111111111111011*
L005248 1111111111110111*
L005264 1111111111110111*
L005280 1111111111101111*
L005296 1111111111101111*
L005312 1111111111101111*
L005328 1111111111111111*
L005344 1111111111101111*
L005360 1111111111101111*
L005376 1111111111111111*
L005392 1111111111101111*
L005408 1111111111101111*
L005424 1111111111111111*
L005440 1111111111101111*
L005456 1111111111011111*
L005472 1111111111111111*
L005488 1111111111011111*
L005504 1111111110111111*
L005520 1111111111111111*
L005536 1111111110111111*
L005552 1111111101111111*
L005568 1111111101111111*
L005584 1111111011111111*
L005600 1111111011111111*
L005616 1111111111111111*
L005632 1111110111111111*
L005648 1111110111111111*
L005664 1111111111111111*
L005680 1111110111111111*
L005696 1111110111111111*
L005712 1111111111111111*
L005728 1111110111111111*
L005744 1111110111111111*
L005760 1111111111111111*
L005776 1111110111111111*
L005792 1111110111111111*
L005808 1111111111111111*
L005824 1111111111111111*
L005840 1111111111111111*
L005856 1111111111111111*
L005872 1111111111111111*
L005888 1111111111111111*
L005904 1111111111111111*
L005920 1111111111111111*
L005936 1111111111111111*
L005952 1111111111111111*
L005968 1111111111111111*
L005984 1111111111111111*
L006000 1111111111111111*
Note Block 0 I/O Macrocell Configuration 27 bits *
N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 RegCom Oe:4 Tm Slw Pu*
L006016 010101111001110101100000011*
L006043 010101111001110111011111101*
L006070 010101111001110111011111101*
L006097 010101111001110111011111101*
L006124 010101111001110111011111101*
L006151 010101111001110111011111101*
L006178 000001111001100110011111101*
L006205 010101111001110111011111101*
L006232 010101111001110111011111101*
L006259 010101111001110111011111101*
L006286 010101111001110111011111101*
L006313 000001111001100110011111101*
L006340 010101111001110111011111101*
L006367 010101111001110111011111101*
L006394 010101111001110110011111101*
L006421 010101111111110110011111101*
Note Block 1 *
Note Block 1 ZIA *
L006448 1110101011111111*
L006464 1111111011010111*
L006480 1111111011010111*
L006496 1111111111111111*
L006512 1111111011010111*
L006528 1110101011111111*
L006544 1110110011111111*
L006560 1110011011111111*
L006576 1111111011010111*
L006592 1111111011100111*
L006608 1110011011111111*
L006624 1111111111111111*
L006640 1111111111111111*
L006656 1111111111111111*
L006672 1110110011111111*
L006688 1111111111111111*
L006704 1110101011111111*
L006720 1111111111111111*
L006736 1110110011111111*
L006752 1110110011111111*
L006768 1110110011111111*
L006784 1111111111111111*
L006800 1111111111111111*
L006816 1111111111111111*
L006832 1111111111111111*
L006848 1111111111111111*
L006864 1111111011010111*
L006880 1111111111111111*
L006896 1111111111111111*
L006912 1111111111111111*
L006928 1111111111111111*
L006944 1111111111111111*
L006960 1111111111111111*
L006976 1111111111111111*
L006992 1111111111111111*
L007008 1111111111111111*
L007024 1111111111111111*
L007040 1111111111111111*
L007056 1111111111111111*
L007072 1111111111111111*
Note Block 1 PLA AND array *
L007088 01111111111111111111111111111111111101111111111111110111111111111111111111111111*
L007168 10111111111111111111111111111111111110111111111111110111111111111111111111111111*
L007248 01111111111111111111111111110111111111111111111111110111111111111111111111111111*
L007328 10111111111111111111111111111011111111111111111111110111111111111111111111111111*
L007408 01111111111111111111111111111111111111011111111111110111111111111111111111111111*
L007488 10111111111111111111111111111111111111101111111111110111111111111111111111111111*
L007568 01111111111111111111111111111111111111110111111111110111111111111111111111111111*
L007648 10111111111111111111111111111111111111111011111111110111111111111111111111111111*
L007728 01111111111111011111111111111111111111111111111111110111111111111111111111111111*
L007808 10111111111111101111111111111111111111111111111111110111111111111111111111111111*
L007888 11111111111101110111111111111111111111111111111111111111111111111111111111111111*
L007968 01111111111111111111011111111111111111111111111111110111111111111111111111111111*
L008048 10111111111111111111101111111111111111111111111111110111111111111111111111111111*
L008128 11111111111111111101111111111111111111111111111111111111111111111111111111111111*
L008208 01111111110111111111111111111111111111111111111111110111111111111111111111111111*
L008288 10111111111011111111111111111111111111111111111111110111111111111111111111111111*
L008368 11011111111111111111111111111111111111111111111111111111111111111111111111111111*
L008448 01111111111111111111111111111111011111111111111111110111111111111111111111111111*
L008528 10111111111111111111111111111111101111111111111111110111111111111111111111111111*
L008608 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008688 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008768 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008848 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008928 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009008 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009088 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009168 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009248 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009328 11110111111111111111111111111111111111111111111111111111111111111111111111111111*
L009408 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009488 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009568 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009648 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009728 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009808 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009888 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009968 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010048 11111111011111111111111111111111111111111111111111111111111111111111111111111111*
L010128 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010208 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010288 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010368 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010448 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010528 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010608 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010688 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010768 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010848 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010928 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011008 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011088 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011168 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011248 10111111111111111111111111111111111111111111111111110111111111111111111111111111*
L011328 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011408 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011488 10111111111111111111111111111111111111111111111111110111111111111111111111111111*
Note Block 1 PLA OR array *
L011568 1111111111111011*
L011584 1111111111111011*
L011600 1111111111110111*
L011616 1111111111110111*
L011632 1111111111101111*
L011648 1111111111101111*
L011664 1111111111011111*
L011680 1111111111011111*
L011696 1111111101111111*
L011712 1111111101111111*
L011728 1111111111111111*
L011744 1111101111111111*
L011760 1111101111111111*
L011776 1111111111111111*
L011792 1111011111111111*
L011808 1111011111111111*
L011824 1111111111111111*
L011840 1110111111111111*
L011856 1110111111111111*
L011872 1111111111111111*
L011888 1111111111111111*
L011904 1111111111111111*
L011920 1111111111111111*
L011936 1111111111111111*
L011952 1111111111111111*
L011968 1111111111111111*
L011984 1111111111111111*
L012000 1111111111111111*
L012016 1111111111111111*
L012032 1111111111111111*
L012048 1111111111111111*
L012064 1111111111111111*
L012080 1111111111111111*
L012096 1111111111111111*
L012112 1111111111111111*
L012128 1111111111111111*
L012144 1111111111111111*
L012160 1111111111111111*
L012176 1111111111111111*
L012192 1111111111111111*
L012208 1111111111111111*
L012224 1111111111111111*
L012240 1111111111111111*
L012256 1111111111111111*
L012272 1111111111111111*
L012288 1111111111111111*
L012304 1111111111111111*
L012320 1111111111111111*
L012336 1111111111111111*
L012352 1111111111111111*
L012368 1111111111111111*
L012384 1111111111111111*
L012400 1111111111111111*
L012416 1111111111111111*
L012432 1111111111111111*
L012448 1111111111111111*
Note Block 1 I/O Macrocell Configuration 27 bits *
N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 RegCom Oe:4 Tm Slw Pu*
L012464 000001111001100111011111101*
L012491 010101111001110111011111101*
L012518 010101111001110111011111101*
L012545 010101111001111100000000011*
L012572 010101111001111101100000011*
L012599 010101111001111101100000011*
L012626 010101111001110111011111101*
L012653 000101111000010000011111001*
L012680 010101111001111101100000011*
L012707 010101111001110101011111001*
L012734 010101111001111101100000011*
L012761 010101111001111101100000011*
L012788 010101111001111101100000011*
L012815 010101111001111101100000011*
L012842 010101111001111100100000011*
L012869 010101111001111100100000011*
Note Block 2 *
Note Block 2 ZIA *
L012896 1100111011111111*
L012912 1100111011111111*
L012928 1010111011111111*
L012944 1111111111111111*
L012960 1110011011111111*
L012976 1111111011010111*
L012992 1010111011111111*
L013008 0110111011111111*
L013024 1111111111111111*
L013040 1100111011111111*
L013056 1111111111111111*
L013072 1111111011100111*
L013088 1111111011100111*
L013104 1111111111111111*
L013120 1100111011111111*
L013136 1100111011111111*
L013152 1111111111111111*
L013168 1010111011111111*
L013184 1111111111111111*
L013200 1111111111111111*
L013216 1111111111111111*
L013232 1111111111111111*
L013248 1110110011111111*
L013264 1111111111111111*
L013280 1111111111111111*
L013296 1111111111111111*
L013312 1111111111111111*
L013328 1111111111111111*
L013344 1111111111111111*
L013360 1111111111111111*
L013376 1111111111111111*
L013392 1111111111111111*
L013408 1111111111111111*
L013424 1111111111111111*
L013440 1111111111111111*
L013456 1111111111111111*
L013472 1111111111111111*
L013488 1111111111111111*
L013504 1111111111111111*
L013520 1111111111111111*
Note Block 2 PLA AND array *
L013536 11111111110111111111111010111111111111111111011111111111111111111111111111111111*
L013616 11111111110111011111111011111111111111111111011111111111111111111111111111111111*
L013696 11111111011011111111111010111111111111111111111111111111111111111111111111111111*
L013776 11111111011011011111111011111111111111111111111111111111111111111111111111111111*
L013856 11111111110111111111111111110111111111111111101111111111111111111111111111111111*
L013936 11111111101011111111111111110111111111111111111111111111111111111111111111111111*
L014016 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014096 11111111111011111111111111111111111111111111111111111111111111111111111111111111*
L014176 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014256 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014336 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014416 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014496 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014576 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014656 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014736 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014816 11111111111011111111111111111111111111111111111111111111111111111111111111111111*
L014896 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014976 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015056 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015136 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015216 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015296 11011111111011111111111111111111111111111111111111111111111111111111111111111111*
L015376 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015456 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015536 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015616 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015696 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015776 01010111111001111101111111111101110111111111111111111111111111111111111111111111*
L015856 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015936 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016016 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016096 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016176 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016256 11011111111011111111111111111101111111111111111111111111111111111111111111111111*
L016336 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016416 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016496 01011111111011111111111111111101111111111111111111111111111111111111111111111111*
L016576 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016656 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016736 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016816 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016896 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016976 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017056 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017136 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017216 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017296 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017376 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017456 01011111111011111101111111111101111111111111111111111111111111111111111111111111*
L017536 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017616 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017696 01011111111011111101111111111101110111111111111111111111111111111111111111111111*
L017776 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017856 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017936 01010111111011111101111111111101110111111111111111111111111111111111111111111111*
Note Block 2 PLA OR array *
L018016 0111111111111111*
L018032 0111111111111111*
L018048 0111111111111111*
L018064 0111111111111111*
L018080 0111111111111111*
L018096 0111111111111111*
L018112 1111111111111111*
L018128 1111111111111111*
L018144 1111111111111111*
L018160 1111111111111111*
L018176 1111111111111111*
L018192 1111111111111111*
L018208 1111111111111111*
L018224 1111111111111111*
L018240 1111111111111111*
L018256 1111111111111111*
L018272 1111111111111111*
L018288 1111111111111111*
L018304 1111111111111111*
L018320 1111111111111111*
L018336 1111111111111111*
L018352 1111111111111111*
L018368 1111111111111111*
L018384 1111111111111111*
L018400 1111111111111111*
L018416 1111111111111111*
L018432 1111111111111111*
L018448 1111111111111111*
L018464 1111111111111111*
L018480 1111111111111111*
L018496 1111111111111111*
L018512 1111111111111111*
L018528 1111111111111111*
L018544 1111111111111111*
L018560 1111111111111111*
L018576 1111111111111111*
L018592 1111111111111111*
L018608 1111111111111111*
L018624 1111111111111111*
L018640 1111111111111111*
L018656 1111111111111111*
L018672 1111111111111111*
L018688 1111111111111111*
L018704 1111111111111111*
L018720 1111111111111111*
L018736 1111111111111111*
L018752 1111111111111111*
L018768 1111111111111111*
L018784 1111111111111111*
L018800 1111111111111111*
L018816 1111111111111111*
L018832 1111111111111111*
L018848 1111111111111111*
L018864 1111111111111111*
L018880 1111111111111111*
L018896 1111111111111111*
Note Block 2 I/O Macrocell Configuration 27 bits *
N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 RegCom Oe:4 Tm Slw Pu*
L018912 000101111001110100000000011*
L018939 000001111000011100011111000*
L018966 000101111100010101001000011*
L018993 000001111001111110011111100*
L019020 000101111100010101001000011*
L019047 000001111001111110011111100*
L019074 000101111100011101001000011*
L019101 000001111000011100011111000*
L019128 000101111100010101001000011*
L019155 000101111100010101001000011*
L019182 000001111000011100011111000*
L019209 000001111000011100011111000*
L019236 000001111001111110011111100*
L019263 000101111100010101001000011*
L019290 000101111100010101001000011*
L019317 000101111100010101001000011*
Note Block 3 *
Note Block 3 ZIA *
L019344 1111111111111111*
L019360 1111111111111111*
L019376 1111111111111111*
L019392 1111111111111111*
L019408 1111111111111111*
L019424 1111111111111111*
L019440 1111111011100111*
L019456 1111111010110111*
L019472 1111111111111111*
L019488 1111111111111111*
L019504 1111111111111111*
L019520 1111111111111111*
L019536 1111111111111111*
L019552 1111111111111111*
L019568 1111111111111111*
L019584 1111111111111111*
L019600 1111111111111111*
L019616 1111111111111111*
L019632 1111111111111111*
L019648 1111111111111111*
L019664 1111111111111111*
L019680 1111111111111111*
L019696 1111111111111111*
L019712 1111111111111111*
L019728 1111111111111111*
L019744 1111111111111111*
L019760 1111111111111111*
L019776 1111111111111111*
L019792 1111111111111111*
L019808 1111111111111111*
L019824 1111111111111111*
L019840 1111111111111111*
L019856 1111111111111111*
L019872 1111111111111111*
L019888 1111111111111111*
L019904 1111111111111111*
L019920 1111111111111111*
L019936 1111111111111111*
L019952 1111111111111111*
L019968 1111111111111111*
Note Block 3 PLA AND array *
L019984 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020064 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020144 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020224 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020304 11111111111111011111111111111111111111111111111111111111111111111111111111111111*
L020384 11111111111101111111111111111111111111111111111111111111111111111111111111111111*
L020464 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020544 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020624 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020704 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020784 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020864 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020944 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021024 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021104 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021184 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021264 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021344 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021424 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021504 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021584 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021664 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021744 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021824 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021904 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021984 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022064 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022144 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022224 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022304 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022384 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022464 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022544 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022624 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022704 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022784 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022864 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022944 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023024 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023104 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023184 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023264 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023344 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023424 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023504 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023584 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023664 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023744 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023824 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023904 11111111111110111111111111111111111111111111111111111111111111111111111111111111*
L023984 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024064 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024144 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024224 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024304 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024384 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
Note Block 3 PLA OR array *
L024464 1111111111111111*
L024480 1111111111111111*
L024496 1111111111111111*
L024512 1111111111111111*
L024528 1111111111111111*
L024544 1111111111111111*
L024560 1111111111111111*
L024576 1111111111111111*
L024592 1111111111111111*
L024608 1111111111111111*
L024624 1111111111111111*
L024640 1111111111111111*
L024656 1111111111111111*
L024672 1111111111111111*
L024688 1111111111111111*
L024704 1111111111111111*
L024720 1111111111111111*
L024736 1111111111111111*
L024752 1111111111111111*
L024768 1111111111111111*
L024784 1111111111111111*
L024800 1111111111111111*
L024816 1111111111111111*
L024832 1111111111111111*
L024848 1111111111111111*
L024864 1111111111111111*
L024880 1111111111111111*
L024896 1111111111111111*
L024912 1111111111111111*
L024928 1111111111111111*
L024944 1111111111111111*
L024960 1111111111111111*
L024976 1111111111111111*
L024992 1111111111111111*
L025008 1111111111111111*
L025024 1111111111111111*
L025040 1111111111111111*
L025056 1111111111111111*
L025072 1111111111111111*
L025088 1111111111111111*
L025104 1111111111111111*
L025120 1111111111111111*
L025136 1111111111111111*
L025152 1111111111111111*
L025168 1111111111111111*
L025184 1111111111111111*
L025200 1111111111111111*
L025216 1111111111111111*
L025232 1111111111111111*
L025248 1111111111111111*
L025264 1111111111111111*
L025280 1111111111111111*
L025296 1111111111111111*
L025312 1111111111111111*
L025328 1111111111111111*
L025344 1111111111111111*
Note Block 3 I/O Macrocell Configuration 27 bits *
N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 RegCom Oe:4 Tm Slw Pu*
L025360 000001111001111110011111100*
L025387 000001111001111110011111100*
L025414 000001111001111110011111100*
L025441 000001111001111110011111100*
L025468 000001111001111110011111100*
L025495 000001111001111110011111100*
L025522 000001111001111110011111100*
L025549 000001111001111110011111100*
L025576 000001111001111110011111100*
L025603 000001111001111110011111100*
L025630 000001111001111110011111100*
L025657 000001111001111110011111100*
L025684 101101011000010000011111101*
L025711 000001111001111101010000011*
L025738 000001111001111110011111100*
L025765 000001111001111110011111100*
Note Globals *
Note Global Clock Mux *
L025792 001*
Note Global Set/Reset Mux *
L025795 00*
Note Global OE Mux *
L025797 11111111*
Note Global Termination *
L025805 1*
Note Input Voltage Standard for IOB *
L025806 0*
Note Output Voltage Standard for IOB *
L025807 0*
Note I/O Bank 0 Vcci *
L025808 0*
Note I/O Bank 0 Vcco *
L025809 0*
Note I/O Bank 1 Vcci *
L025810 0*
Note I/O Bank 1 Vcco *
L025811 0*
CED50*
AA1E

74
Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_debug/top.ucf Normal file
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#
# Copyright 2012 Jared Boone
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK;
TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 25 ns;
TIMEGRP "adc_data" OFFSET = IN 16 ns BEFORE "CODEC_X2_CLK";
TIMEGRP "dac_data" OFFSET = OUT 15 ns AFTER "CODEC_X2_CLK";
TIMEGRP "to_host" OFFSET = OUT 20 ns AFTER "CODEC_X2_CLK";
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "CODEC_CLK" LOC = "P23" ;
NET "CODEC_X2_CLK" LOC = "P27" ;
NET "DA<0>" LOC = "P43" ;
NET "DA<1>" LOC = "P42" ;
NET "DA<2>" LOC = "P41" ;
NET "DA<3>" LOC = "P40" ;
NET "DA<4>" LOC = "P39" ;
NET "DA<5>" LOC = "P37" ;
NET "DA<6>" LOC = "P36" ;
NET "DA<7>" LOC = "P35" ;
NET "DD<0>" LOC = "P34" ;
NET "DD<1>" LOC = "P33" ;
NET "DD<2>" LOC = "P32" ;
NET "DD<3>" LOC = "P30" ;
NET "DD<4>" LOC = "P29" ;
NET "DD<5>" LOC = "P28" ;
NET "DD<6>" LOC = "P24" ;
NET "DD<7>" LOC = "P19" ;
NET "DD<8>" LOC = "P18" ;
NET "DD<9>" LOC = "P17" ;
NET "HOST_CAPTURE" LOC = "P91" ;
NET "HOST_DATA<0>" LOC = "P89" ;
NET "HOST_DATA<1>" LOC = "P79" ;
NET "HOST_DATA<2>" LOC = "P74" ;
NET "HOST_DATA<3>" LOC = "P72" ;
NET "HOST_DATA<4>" LOC = "P67" ;
NET "HOST_DATA<5>" LOC = "P64" ;
NET "HOST_DATA<6>" LOC = "P61" ;
NET "HOST_DATA<7>" LOC = "P77" ;
NET "HOST_DIRECTION" LOC = "P71" ;
NET "HOST_DISABLE" LOC = "P76" ;
NET "HOST_Q_INVERT" LOC = "P70" ;
NET "HOST_SYNC_EN" LOC = "P90" ;
NET "HOST_SYNC" LOC = "P55" | PULLUP ;
NET "HOST_SYNC_CMD" LOC = "P56" ;
NET "B2AUX1" LOC = "13" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

180
Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_debug/top.vhd Normal file
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--
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_SYNC_EN : in std_logic;
HOST_SYNC_CMD : out std_logic;
HOST_SYNC : in std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic;
B2AUX1 : out std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_rx_i : std_logic;
signal codec_clk_tx_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal host_sync_enable : std_logic := '0';
signal host_sync_o : std_logic := '0';
signal host_sync_i : std_logic := '0';
signal host_sync_latched : std_logic := '0';
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal compare_counter : std_logic_vector(7 downto 0);
signal glitch_detected_o : std_logic;
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
HOST_CAPTURE <= host_data_capture_o;
host_sync_enable <= HOST_SYNC_EN;
host_sync_i <= HOST_SYNC;
HOST_SYNC_CMD <= host_sync_o;
B2AUX1 <= glitch_detected_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
------------------------------------------------
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7f" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
codec_clk_rx_i <= CODEC_CLK;
adc_data_i <= DA(7 downto 0);
if (transfer_direction_i = from_adc) then
data_to_host_o <= data_to_host_o + 1;
end if;
end if;
end process;
process(host_clk_i)
begin
if falling_edge(host_clk_i) then
codec_clk_tx_i <= CODEC_CLK;
data_from_host_i <= HOST_DATA;
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
if data_from_host_i /= compare_counter then
glitch_detected_o <= '1';
else
glitch_detected_o <= '0';
end if;
compare_counter <= data_from_host_i + 1;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process (host_data_enable_i, host_sync_i)
begin
host_sync_o <= host_data_enable_i;
if host_data_enable_i = '1' then
if rising_edge(host_sync_i) then
host_sync_latched <= host_sync_i;
end if;
else
host_sync_latched <= '0';
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
else
if codec_clk_rx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
end if;
end if;
end process;
end Behavioral;

132
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--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
COMPONENT top
PORT(
HOST_DATA : INOUT std_logic_vector(7 downto 0);
HOST_CAPTURE : OUT std_logic;
HOST_DISABLE : IN std_logic;
HOST_DIRECTION : IN std_logic;
HOST_DECIM_SEL : IN std_logic_vector(2 downto 0);
DA : IN std_logic_vector(7 downto 0);
DD : OUT std_logic_vector(9 downto 0);
CODEC_CLK : IN std_logic;
CODEC_X2_CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal DA : std_logic_vector(7 downto 0) := (others => '0');
signal CODEC_CLK : std_logic := '0';
signal CODEC_X2_CLK : std_logic := '0';
signal HOST_DISABLE : std_logic := '1';
signal HOST_DIRECTION : std_logic := '0';
signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010";
--BiDirs
signal HOST_DATA : std_logic_vector(7 downto 0);
--Outputs
signal DD : std_logic_vector(9 downto 0);
signal HOST_CAPTURE : std_logic;
begin
uut: top PORT MAP (
HOST_DATA => HOST_DATA,
HOST_CAPTURE => HOST_CAPTURE,
HOST_DISABLE => HOST_DISABLE,
HOST_DIRECTION => HOST_DIRECTION,
HOST_DECIM_SEL => HOST_DECIM_SEL,
DA => DA,
DD => DD,
CODEC_CLK => CODEC_CLK,
CODEC_X2_CLK => CODEC_X2_CLK
);
clk_process :process
begin
CODEC_CLK <= '1';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
CODEC_CLK <= '0';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
end process;
adc_proc: process
begin
wait until rising_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000000";
wait until falling_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000001";
end process;
sgpio_proc: process
begin
HOST_DATA <= (others => 'Z');
HOST_DIRECTION <= '0';
HOST_DISABLE <= '1';
wait for 135 ns;
HOST_DISABLE <= '0';
wait for 1000 ns;
HOST_DISABLE <= '1';
wait for 100 ns;
HOST_DIRECTION <= '1';
wait for 100 ns;
HOST_DISABLE <= '0';
for i in 0 to 10 loop
HOST_DATA <= (others => '0');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
HOST_DATA <= (others => '1');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
end loop;
wait;
end process;
end;

47
Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_if/Makefile Normal file
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# xst -intstyle ise -ifn top.xst -ofn top.syr
# ngdbuild -intstyle ise -dd _ngo -uc top.ucf -p xc2c64a-VQ100-7 top.ngc top.ngd
# cpldfit -intstyle ise -p xc2c64a-7-VQ100 -ofmt vhdl -optimize density -loc on -slew slow -init low -inputs 32 -pterms 28 -unused pullup -terminate float -iostd LVCMOS33 top.ngd
# tsim -intstyle ise top top.nga
# taengine -intstyle ise -f top -l top.tim -e {taengine.err}
# hprep6 -s IEEE1149 -i top
# vhdtdtfi -prj sgpio_if -o top.vhi -module top -template /opt/Xilinx/14.7/ISE_DS/ISE/data/vhdlinst.tft -deleteonerror -lib work top.vhd
DESIGN=top
DEVICE=xc2c64a
DEVICE_SPEED=7
DEVICE_PACKAGE=VQ100
OUTFILES_XST=$(DESIGN).ngc $(DESIGN).syr $(DESIGN).ngr $(DESIGN)_xst.xrpt $(DESIGN).lso _xmsgs/xst.xmsgs
OUTFILES_NGDBUILD=$(DESIGN).ngd $(DESIGN).bld $(DESIGN)_ngdbuild.xrpt _xmsgs/ngdbuild.xmsgs _ngo/netlist.lst xlnx_auto_0_xdb/cst.xbcd
OUTFILES_CPLDFIT=$(DESIGN).vm6 $(DESIGN).tspec t6.phd t6.dat t55.phd t55.dat t1.phd t1.dat $(DESIGN).log $(DESIGN).chk $(DESIGN).rpt $(DESIGN).xml $(DESIGN)_build.xml $(DESIGN).pad $(DESIGN)_pad.csv $(DESIGN).pnx $(DESIGN).mfd $(DESIGN).cxt $(DESIGN).gyd _xmsgs/cpldfit.xmsgs
OUTFILES_HPREP6=$(DESIGN).jed tmperr.err _xmsgs/hprep6.xmsgs
OUTFILES_IMPACT_SVF=default.svf _impactbatch.log
OUTFILES_IMPACT_XSVF=default.xsvf _impactbatch.log
all: default.svf default.xsvf
$(DESIGN).ngc: $(DESIGN).xst $(DESIGN).prj
mkdir -p xst/projnav.tmp
xst -intstyle ise -ifn $(DESIGN).xst -ofn $(DESIGN).syr
$(DESIGN).ngd: $(DESIGN).ngc $(DESIGN).ucf
ngdbuild -intstyle ise -dd _ngo -uc $(DESIGN).ucf -p $(DEVICE)-$(DEVICE_PACKAGE)-$(DEVICE_SPEED) $(DESIGN).ngc $(DESIGN).ngd
$(DESIGN).vm6: $(DESIGN).ngd
cpldfit -intstyle ise -p $(DEVICE)-$(DEVICE_SPEED)-$(DEVICE_PACKAGE) -ofmt vhdl -optimize speed -loc on -slew slow -init low -inputs 32 -pterms 36 -unused pullup -terminate float -iostd LVCMOS33 $(DESIGN).ngd
$(DESIGN).jed: $(DESIGN).vm6
hprep6 -s IEEE1149 -i $(DESIGN).vm6
default.svf: $(DESIGN).jed batch_svf
impact -batch batch_svf
default.xsvf: $(DESIGN).jed batch_xsvf
impact -batch batch_xsvf
.PHONY: clean
clean:
rm -f $(OUTFILES_XST) $(OUTFILES_NGDBUILD) $(OUTFILES_CPLDFIT) $(OUTFILES_HPREP6) $(OUTFILES_IMPACT_SVF) $(OUTFILES_IMPACT_XSVF)
rm -rf xlnx_auto_0_xdb/ _ngo/ _xmsgs/ xst/

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Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_if/README.md Normal file
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CPLD interface between LPC43xx microcontroller SGPIO peripheral and MAX5864
RF codec.
CPLD-based triggered capture
============================
To build this VHDL project and produce an SVF file for flashing the CPLD:
* Xilinx WebPACK 13.4 for Windows or Linux.
Generate an XSVF
================
After generating a programming file:
* In the ISE Project Navigator, "Processes: top - Behavioral" pane, double-click "Configure Target Device".
* Click "OK" to open iMPACT.
* Ctrl-N to create a "New Project".
* "Yes" to automatically create and save a project file.
* Select "Prepare a Boundary-Scan File", choose "XSVF".
* Select file name "default.xsvf".
* Click "OK" to start adding devices.
* Assign new configuration file: "top.jed".
* Right-click the "xc2c64a top.jed" icon and select "Erase". Accept defaults.
* Right-click the "xc2c64a top.jed" icon and select "Program".
* Right-click the "xc2c64a top.jed" icon and select "Verify".
* Choose menu "Output" -> "XSVF File" -> "Stop Writing to XSVF File".
* Close iMPACT.
To Program
==========
$ hackrf_cpldjtag -x default.xsvf

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Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_if/batch_svf Normal file
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setMode -bscan
setCable -port svf -file default.svf
addDevice -p 1 -file top.jed
Erase -p 1
Program -p 1 -e -v
Verify -p 1
quit

7
Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_if/batch_xsvf Normal file
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setMode -bscan
setCable -port xsvf -file default.xsvf
addDevice -p 1 -file top.jed
Erase -p 1
Program -p 1 -e -v
Verify -p 1
quit

BIN
Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_if/default.xsvf Normal file
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Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_if/sgpio_if.xise Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="36" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="Default.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc2c64a" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="CoolRunner2 CPLDs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-7" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS33" xil_pn:valueState="non-default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Speed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="top" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Slow" xil_pn:valueState="non-default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="VQ100" xil_pn:valueState="non-default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="top_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="top" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="top.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Pullup" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="E:/Xilinx/14.1/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|top_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="sgpio_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xbr" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-04-29T12:49:49" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8998E598855F452AB5BAE34A005D4FD5" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

757
Software/portapack-mayhem/hackrf/firmware/cpld/sgpio_if/top.jed Normal file
View File

@ -0,0 +1,757 @@
Programmer Jedec Bit Map
Date Extracted: Mon Jan 21 16:17:38 2019
QF25812*
QP100*
QV0*
F0*
X0*
J0 0*
N VERSION P.20131013*
N DEVICE XC2C64A-7-VQ100*
Note Block 0 *
Note Block 0 ZIA *
L000000 1111111111111111*
L000016 1111111011010111*
L000032 1111111011010111*
L000048 1111111011010111*
L000064 1111111011010111*
L000080 1111111111111111*
L000096 1111111111111111*
L000112 1111111111111111*
L000128 1111111111111111*
L000144 1111111011010111*
L000160 1111111011100111*
L000176 1111111111111111*
L000192 1111111111111111*
L000208 1111111111111111*
L000224 1111111011100111*
L000240 1111111011110011*
L000256 1111111011100111*
L000272 1111111111111111*
L000288 1111111111111111*
L000304 1111111111111111*
L000320 1111111111111111*
L000336 1111111111111111*
L000352 1111111111111111*
L000368 1111111111111111*
L000384 1111111111111111*
L000400 1111111111111111*
L000416 1111111111111111*
L000432 1111111111111111*
L000448 1111111111111111*
L000464 1111111111111111*
L000480 1111111111111111*
L000496 1111111111111111*
L000512 1111111111111111*
L000528 1111111111111111*
L000544 1111111111111111*
L000560 1111111111111111*
L000576 1111111111111111*
L000592 1111111111111111*
L000608 1111111111111111*
L000624 1111111111111111*
Note Block 0 PLA AND array *
L000640 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L000720 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L000800 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L000880 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L000960 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001040 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001120 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001200 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001280 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001360 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001440 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001520 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001600 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001680 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001760 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001840 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L001920 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002000 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002080 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002160 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002240 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002320 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002400 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002480 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002560 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002640 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002720 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002800 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002880 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L002960 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003040 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003120 11111111111111111111111111110111111111111111111111111111111111111111111111111111*
L003200 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003280 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003360 11011111111111111111111111111111111111111111111111111111111111111111111111111111*
L003440 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003520 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003600 11110111111111111111111111111111111111111111111111111111111111111111111111111111*
L003680 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003760 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L003840 11111111011111111111111111111111111111111111111111111111111111111111111111111111*
L003920 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004000 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004080 11111101111111111111111111111111111111111111111111111111111111111111111111111111*
L004160 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004240 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004320 11111111111111111101111111111111111111111111111111111111111111111111111111111111*
L004400 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004480 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004560 11111111111111111111011111111111111111111111111111111111111111111111111111111111*
L004640 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004720 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004800 11111111111111111111111111111111011111111111111111111111111111111111111111111111*
L004880 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L004960 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L005040 11111111111111111111111111111101111111111111111111111111111111111111111111111111*
Note Block 0 PLA OR array *
L005120 1111111111111111*
L005136 1111111111111111*
L005152 1111111111111111*
L005168 1111111111111111*
L005184 1111111111111111*
L005200 1111111111111111*
L005216 1111111111111111*
L005232 1111111111111111*
L005248 1111111111111111*
L005264 1111111111111111*
L005280 1111111111111111*
L005296 1111111111111111*
L005312 1111111111111111*
L005328 1111111111111111*
L005344 1111111111111111*
L005360 1111111111111111*
L005376 1111111111111111*
L005392 1111111111111111*
L005408 1111111111111111*
L005424 1111111111111111*
L005440 1111111111111111*
L005456 1111111111111111*
L005472 1111111111111111*
L005488 1111111111111111*
L005504 1111111111111111*
L005520 1111111111111111*
L005536 1111111111111111*
L005552 1111111111111111*
L005568 1111111111111111*
L005584 1111111111111111*
L005600 1111111111111111*
L005616 1111111111111111*
L005632 1111111111111111*
L005648 1111111111111111*
L005664 1111111111111111*
L005680 1111111111111111*
L005696 1111111111111111*
L005712 1111111111111111*
L005728 1111111111111111*
L005744 1111111111111111*
L005760 1111111111111111*
L005776 1111111111111111*
L005792 1111111111111111*
L005808 1111111111111111*
L005824 1111111111111111*
L005840 1111111111111111*
L005856 1111111111111111*
L005872 1111111111111111*
L005888 1111111111111111*
L005904 1111111111111111*
L005920 1111111111111111*
L005936 1111111111111111*
L005952 1111111111111111*
L005968 1111111111111111*
L005984 1111111111111111*
L006000 1111111111111111*
Note Block 0 I/O Macrocell Configuration 27 bits *
N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 RegCom Oe:4 Tm Slw Pu*
L006016 000001111001111110011111100*
L006043 000001111001111110011111100*
L006070 000001111001111110011111100*
L006097 000001111001111110011111100*
L006124 000001111001111110011111100*
L006151 000001111001111110011111100*
L006178 000001111001111110011111100*
L006205 010101111001110111011111101*
L006232 010101111001110111011111101*
L006259 010101111001110111011111101*
L006286 010101111001110111011111101*
L006313 010101111001110111011111101*
L006340 010101111001110111011111101*
L006367 010101111001110111011111101*
L006394 010101111001110111011111101*
L006421 010101111001110111011111101*
Note Block 1 *
Note Block 1 ZIA *
L006448 1111111111111111*
L006464 1110101011111111*
L006480 1110101011111111*
L006496 1110101011111111*
L006512 1111111111111111*
L006528 1111111011010111*
L006544 1110101011111111*
L006560 1111111111111111*
L006576 1110101011111111*
L006592 1110101011111111*
L006608 1110101011111111*
L006624 1111111111111111*
L006640 1111111111111111*
L006656 1110110011111111*
L006672 1111111111111111*
L006688 1111111111111111*
L006704 1110110011111111*
L006720 1111111111111111*
L006736 1111111011010111*
L006752 1111111111111111*
L006768 1111111111111111*
L006784 1111111111111111*
L006800 1111111111111111*
L006816 1111111111111111*
L006832 1111111111111111*
L006848 1111111111111111*
L006864 1111111111111111*
L006880 1111111111111111*
L006896 1111111111111111*
L006912 1111111111111111*
L006928 1111111111111111*
L006944 1111111111111111*
L006960 1111111111111111*
L006976 1111111111111111*
L006992 1111111111111111*
L007008 1111111111111111*
L007024 1111111111111111*
L007040 1111111111111111*
L007056 1111111111111111*
L007072 1111111111111111*
Note Block 1 PLA AND array *
L007088 11011111110111111111111111111111111101111111111111111111111111111111111111111111*
L007168 11111111111011111111111111111111111111111111111111111111111111111111111111111111*
L007248 11011111111111111111111111111111111101111111111111111111111111111111111111111111*
L007328 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007408 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007488 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007568 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007648 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007728 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007808 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007888 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L007968 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008048 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008128 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008208 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008288 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008368 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008448 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008528 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008608 11111111110111111111111111101111111111111111111111111111111111111111111111111111*
L008688 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008768 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L008848 11111111110111111111111111111111101111111111111111111111111111111111111111111111*
L008928 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009008 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009088 11111011110111111111111111111111111111111111111111111111111111111111111111111111*
L009168 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009248 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009328 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009408 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009488 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009568 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009648 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009728 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009808 11111111110111111110111111111111111111111111111111111111111111111111111111111111*
L009888 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L009968 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010048 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010128 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010208 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010288 11111110110111111111111111111111111111111111111111111111111111111111111111111111*
L010368 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010448 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010528 11111111110111111111101111111111111111111111111111111111111111111111111111111111*
L010608 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010688 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010768 11111111110110111111111111111111111111111111111111111111111111111111111111111111*
L010848 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L010928 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011008 11111111110111111011111111111111111111111111111111111111111111111111111111111111*
L011088 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011168 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011248 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011328 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011408 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L011488 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
Note Block 1 PLA OR array *
L011568 1110001101000011*
L011584 1111111111111100*
L011600 1111111111111100*
L011616 1111111111111111*
L011632 1111111111111111*
L011648 1111111111111111*
L011664 1111111111111111*
L011680 1111111111111111*
L011696 1111111111111111*
L011712 1111111111111111*
L011728 1111111111111111*
L011744 1111111111111111*
L011760 1111111111111111*
L011776 1111111111111111*
L011792 1111111111111111*
L011808 1111111111111111*
L011824 1111111111111111*
L011840 1111111111111111*
L011856 1111111111111111*
L011872 1111111111111111*
L011888 1111111111111111*
L011904 1111111111111111*
L011920 1111111111111111*
L011936 1111111111111111*
L011952 1111111111111111*
L011968 1111111111111111*
L011984 1111111111111111*
L012000 1111111111111111*
L012016 1111111111111111*
L012032 1111111111111111*
L012048 1111111111111111*
L012064 1111111111111111*
L012080 1111111111111111*
L012096 1111111111111111*
L012112 1111111111111111*
L012128 1111111111111111*
L012144 1111111111111111*
L012160 1111111111111111*
L012176 1111111111111111*
L012192 1111111111111111*
L012208 1111111111111111*
L012224 1111111111111111*
L012240 1111111111111111*
L012256 1111111111111111*
L012272 1111111111111111*
L012288 1111111111111111*
L012304 1111111111111111*
L012320 1111111111111111*
L012336 1111111111111111*
L012352 1111111111111111*
L012368 1111111111111111*
L012384 1111111111111111*
L012400 1111111111111111*
L012416 1111111111111111*
L012432 1111111111111111*
L012448 1111111111111111*
Note Block 1 I/O Macrocell Configuration 27 bits *
N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 RegCom Oe:4 Tm Slw Pu*
L012464 000001111001111110011111100*
L012491 000001111001111110011111100*
L012518 000001111001111110011111100*
L012545 010101111001111101000000011*
L012572 010101111001111100100000011*
L012599 010101111001111100100000011*
L012626 000001111001111110011111100*
L012653 000101111000010000011111001*
L012680 010101111001111100100000011*
L012707 000001111001111100011111000*
L012734 010101111001111100100000011*
L012761 010101111001111100100000011*
L012788 010101111001111100100000011*
L012815 010101111001111100100000011*
L012842 010101111001111100000000011*
L012869 010101111001111100000000011*
Note Block 2 *
Note Block 2 ZIA *
L012896 0110111011111111*
L012912 0110111011111111*
L012928 0110111011111111*
L012944 1010111011111111*
L012960 1010111011111111*
L012976 1111111011010111*
L012992 1010111011111111*
L013008 0110111011111111*
L013024 1111111011010111*
L013040 1010111011111111*
L013056 1100111011111111*
L013072 1110011011111111*
L013088 1010111011111111*
L013104 1010111011111111*
L013120 1100111011111111*
L013136 1100111011111111*
L013152 1111111111111111*
L013168 1010111011111111*
L013184 1100111011111111*
L013200 1100111011111111*
L013216 1010111011111111*
L013232 1100111011111111*
L013248 1111111111111111*
L013264 1111111111111111*
L013280 1111111111111111*
L013296 1111111111111111*
L013312 1111111111111111*
L013328 1111111111111111*
L013344 1111111111111111*
L013360 1111111011100111*
L013376 1111111111111111*
L013392 1110101011111111*
L013408 1111111011100111*
L013424 1111111111111111*
L013440 1111111111111111*
L013456 1111111111111111*
L013472 1111111111111111*
L013488 1111111111111111*
L013504 1111111111111111*
L013520 1111111111111111*
Note Block 2 PLA AND array *
L013536 11111111110111111111111111111111111111111111111111111111111011011011111111111111*
L013616 11111111111011111111110111111111111111111111111111111111111011111011111111111111*
L013696 11111111110111011111111111111111111111111111111111111111111111011011111111111111*
L013776 11111111111011011111110111111111111111111111111111111111111111111011111111111111*
L013856 11111111110111111111111111110111111111111111111111111111111111101111111111111111*
L013936 11111111111011111111111011110111111111111111111111111111111111111111111111111111*
L014016 11111111111011111011111011111111111111111111111111111111111111111111111111111111*
L014096 11111111111011111111111111111111111111111111111111111111111111111111111111111111*
L014176 11111111110111111111111111111111111111011111111111111111111111111111111111111111*
L014256 11111111110111111111111111111101111111111111111111111111111111111111111111111111*
L014336 11111111110111111111111111111111111111111101111111111111111111111111111111111111*
L014416 11111111110111111111111111111111111101111111111111111111111111111111111111111111*
L014496 11111111110111111111111111111111110111111111111111111111111111111111111111111111*
L014576 11111111110111111111111111111111111111110111111111111111111111111111111111111111*
L014656 11111111110101111111111111111111111111111111111111111111111111111111111111111111*
L014736 11111111110111111111011111111111111111111111111111111111111111111111111111111111*
L014816 11110111111011111111111111111111111111111111111111111111111111111111111111111111*
L014896 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L014976 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015056 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015136 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015216 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015296 11011111111011111111111111111111111111111111111111111111111111111111111111111111*
L015376 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015456 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015536 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015616 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015696 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015776 11111110111011111111111111111111111111111111111111111111111111111111111111111111*
L015856 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L015936 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016016 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016096 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016176 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016256 01111111111011111111111111111111111111111111111111111111111111111111111111111111*
L016336 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016416 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016496 11111111111011111111111101111111111111111111111111111111111111111111111111111111*
L016576 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016656 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016736 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016816 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016896 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L016976 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017056 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017136 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017216 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017296 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017376 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017456 11111111011011111111111111111111111111111111111111111111111111111111111111111111*
L017536 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017616 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017696 11111111111011111111111111011111111111111111111111111111111111111111111111111111*
L017776 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017856 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L017936 11111111111011111101111111111111111111111111111111111111111111111111111111111111*
Note Block 2 PLA OR array *
L018016 0111111111111111*
L018032 0111111111111111*
L018048 0111111111111111*
L018064 0111111111111111*
L018080 0111111111111111*
L018096 0111111111111111*
L018112 1101010100111000*
L018128 1111111111111111*
L018144 1101111111111111*
L018160 1111011111111111*
L018176 1111111101111111*
L018192 1111111110111111*
L018208 1111111111111011*
L018224 1111111111111101*
L018240 1111111111111110*
L018256 1111110111111111*
L018272 1111111111111111*
L018288 1111111111111111*
L018304 1111111111111111*
L018320 1111111111111111*
L018336 1111111111111111*
L018352 1111111111111111*
L018368 1111111111111111*
L018384 1111111111111111*
L018400 1111111111111111*
L018416 1111111111111111*
L018432 1111111111111111*
L018448 1111111111111111*
L018464 1111111111111111*
L018480 1111111111111111*
L018496 1111111111111111*
L018512 1111111111111111*
L018528 1111111111111111*
L018544 1111111111111111*
L018560 1111111111111111*
L018576 1111111111111111*
L018592 1111111111111111*
L018608 1111111111111111*
L018624 1111111111111111*
L018640 1111111111111111*
L018656 1111111111111111*
L018672 1111111111111111*
L018688 1111111111111111*
L018704 1111111111111111*
L018720 1111111111111111*
L018736 1111111111111111*
L018752 1111111111111111*
L018768 1111111111111111*
L018784 1111111111111111*
L018800 1111111111111111*
L018816 1111111111111111*
L018832 1111111111111111*
L018848 1111111111111111*
L018864 1111111111111111*
L018880 1111111111111111*
L018896 1111111111111111*
Note Block 2 I/O Macrocell Configuration 27 bits *
N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 RegCom Oe:4 Tm Slw Pu*
L018912 000101111001110100000000011*
L018939 000001111000011100011111000*
L018966 000101111000010101001000011*
L018993 000001111001111110011111100*
L019020 000101111000010101001000011*
L019047 000001111001111110011111100*
L019074 000101111000010101001000011*
L019101 000001111000011100011111000*
L019128 000101111000010101001000011*
L019155 000101111000010101001000011*
L019182 000001111000011100011111000*
L019209 000001111000011100011111000*
L019236 000001111001111110011111100*
L019263 000101111000010101001000011*
L019290 000101111000010101001000011*
L019317 000101111000010101001000011*
Note Block 3 *
Note Block 3 ZIA *
L019344 1111111111111111*
L019360 1111111111111111*
L019376 1111111111111111*
L019392 1111111111111111*
L019408 1111111111111111*
L019424 1111111111111111*
L019440 1111111011100111*
L019456 1111111010110111*
L019472 1111111111111111*
L019488 1111111111111111*
L019504 1111111111111111*
L019520 1111111111111111*
L019536 1111111111111111*
L019552 1111111111111111*
L019568 1111111111111111*
L019584 1111111111111111*
L019600 1111111111111111*
L019616 1111111111111111*
L019632 1111111111111111*
L019648 1111111111111111*
L019664 1111111111111111*
L019680 1111111111111111*
L019696 1111111111111111*
L019712 1111111111111111*
L019728 1111111111111111*
L019744 1111111111111111*
L019760 1111111111111111*
L019776 1111111111111111*
L019792 1111111111111111*
L019808 1111111111111111*
L019824 1111111111111111*
L019840 1111111111111111*
L019856 1111111111111111*
L019872 1111111111111111*
L019888 1111111111111111*
L019904 1111111111111111*
L019920 1111111111111111*
L019936 1111111111111111*
L019952 1111111111111111*
L019968 1111111111111111*
Note Block 3 PLA AND array *
L019984 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020064 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020144 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020224 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020304 11111111111111011111111111111111111111111111111111111111111111111111111111111111*
L020384 11111111111101111111111111111111111111111111111111111111111111111111111111111111*
L020464 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020544 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020624 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020704 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020784 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020864 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L020944 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021024 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021104 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021184 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021264 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021344 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021424 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021504 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021584 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021664 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021744 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021824 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021904 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L021984 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022064 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022144 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022224 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022304 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022384 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022464 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022544 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022624 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022704 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022784 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022864 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L022944 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023024 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023104 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023184 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023264 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023344 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023424 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023504 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023584 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023664 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023744 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023824 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L023904 11111111111110111111111111111111111111111111111111111111111111111111111111111111*
L023984 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024064 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024144 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024224 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024304 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
L024384 11111111111111111111111111111111111111111111111111111111111111111111111111111111*
Note Block 3 PLA OR array *
L024464 1111111111111111*
L024480 1111111111111111*
L024496 1111111111111111*
L024512 1111111111111111*
L024528 1111111111111111*
L024544 1111111111111111*
L024560 1111111111111111*
L024576 1111111111111111*
L024592 1111111111111111*
L024608 1111111111111111*
L024624 1111111111111111*
L024640 1111111111111111*
L024656 1111111111111111*
L024672 1111111111111111*
L024688 1111111111111111*
L024704 1111111111111111*
L024720 1111111111111111*
L024736 1111111111111111*
L024752 1111111111111111*
L024768 1111111111111111*
L024784 1111111111111111*
L024800 1111111111111111*
L024816 1111111111111111*
L024832 1111111111111111*
L024848 1111111111111111*
L024864 1111111111111111*
L024880 1111111111111111*
L024896 1111111111111111*
L024912 1111111111111111*
L024928 1111111111111111*
L024944 1111111111111111*
L024960 1111111111111111*
L024976 1111111111111111*
L024992 1111111111111111*
L025008 1111111111111111*
L025024 1111111111111111*
L025040 1111111111111111*
L025056 1111111111111111*
L025072 1111111111111111*
L025088 1111111111111111*
L025104 1111111111111111*
L025120 1111111111111111*
L025136 1111111111111111*
L025152 1111111111111111*
L025168 1111111111111111*
L025184 1111111111111111*
L025200 1111111111111111*
L025216 1111111111111111*
L025232 1111111111111111*
L025248 1111111111111111*
L025264 1111111111111111*
L025280 1111111111111111*
L025296 1111111111111111*
L025312 1111111111111111*
L025328 1111111111111111*
L025344 1111111111111111*
Note Block 3 I/O Macrocell Configuration 27 bits *
N Aclk ClkOp Clk:2 ClkFreq R:2 P:2 RegMod:2 INz:2 FB:2 InReg St XorIn:2 RegCom Oe:4 Tm Slw Pu*
L025360 000101111001110000011111001*
L025387 000101111001110000011111001*
L025414 000101111001110000011111001*
L025441 000101111001110000011111001*
L025468 000101111001110000011111001*
L025495 000101111001110000011111001*
L025522 000101111001110000011111001*
L025549 000101111001110000011111001*
L025576 000001111001111110011111100*
L025603 000001111001111110011111100*
L025630 000001111001111110011111100*
L025657 000001111001111110011111100*
L025684 101101011000010000011111101*
L025711 000001111001111101010000011*
L025738 000001111001111110011111100*
L025765 000001111001111110011111100*
Note Globals *
Note Global Clock Mux *
L025792 001*
Note Global Set/Reset Mux *
L025795 00*
Note Global OE Mux *
L025797 11111111*
Note Global Termination *
L025805 1*
Note Input Voltage Standard for IOB *
L025806 0*
Note Output Voltage Standard for IOB *
L025807 0*
Note I/O Bank 0 Vcci *
L025808 0*
Note I/O Bank 0 Vcco *
L025809 0*
Note I/O Bank 1 Vcci *
L025810 0*
Note I/O Bank 1 Vcco *
L025811 0*
C035D*
AA97

72
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#
# Copyright 2012 Jared Boone
#
# This file is part of HackRF.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; see the file COPYING. If not, write to
# the Free Software Foundation, Inc., 51 Franklin Street,
# Boston, MA 02110-1301, USA.
NET "CODEC_X2_CLK" TNM_NET = CODEC_X2_CLK;
TIMESPEC TS_codec_x2_data = PERIOD "CODEC_X2_CLK" 25 ns;
TIMEGRP "adc_data" OFFSET = IN 16 ns BEFORE "CODEC_X2_CLK";
TIMEGRP "dac_data" OFFSET = OUT 15 ns AFTER "CODEC_X2_CLK";
TIMEGRP "to_host" OFFSET = OUT 20 ns AFTER "CODEC_X2_CLK";
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "CODEC_CLK" LOC = "P23" ;
NET "CODEC_X2_CLK" LOC = "P27" ;
NET "DA<0>" LOC = "P43" ;
NET "DA<1>" LOC = "P42" ;
NET "DA<2>" LOC = "P41" ;
NET "DA<3>" LOC = "P40" ;
NET "DA<4>" LOC = "P39" ;
NET "DA<5>" LOC = "P37" ;
NET "DA<6>" LOC = "P36" ;
NET "DA<7>" LOC = "P35" ;
NET "DD<0>" LOC = "P34" ;
NET "DD<1>" LOC = "P33" ;
NET "DD<2>" LOC = "P32" ;
NET "DD<3>" LOC = "P30" ;
NET "DD<4>" LOC = "P29" ;
NET "DD<5>" LOC = "P28" ;
NET "DD<6>" LOC = "P24" ;
NET "DD<7>" LOC = "P19" ;
NET "DD<8>" LOC = "P18" ;
NET "DD<9>" LOC = "P17" ;
NET "HOST_CAPTURE" LOC = "P91" ;
NET "HOST_DATA<0>" LOC = "P89" ;
NET "HOST_DATA<1>" LOC = "P79" ;
NET "HOST_DATA<2>" LOC = "P74" ;
NET "HOST_DATA<3>" LOC = "P72" ;
NET "HOST_DATA<4>" LOC = "P67" ;
NET "HOST_DATA<5>" LOC = "P64" ;
NET "HOST_DATA<6>" LOC = "P61" ;
NET "HOST_DATA<7>" LOC = "P77" ;
NET "HOST_DIRECTION" LOC = "P71" ;
NET "HOST_DISABLE" LOC = "P76" ;
NET "HOST_Q_INVERT" LOC = "P70" ;
NET "HOST_SYNC_EN" LOC = "P90" ;
NET "HOST_SYNC" LOC = "P55" | PULLUP ;
NET "HOST_SYNC_CMD" LOC = "P56" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE

172
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--
-- Copyright 2012 Jared Boone
-- Copyright 2013 Benjamin Vernoux
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity top is
Port(
HOST_DATA : inout std_logic_vector(7 downto 0);
HOST_CAPTURE : out std_logic;
HOST_SYNC_EN : in std_logic;
HOST_SYNC_CMD : out std_logic;
HOST_SYNC : in std_logic;
HOST_DISABLE : in std_logic;
HOST_DIRECTION : in std_logic;
HOST_Q_INVERT : in std_logic;
DA : in std_logic_vector(7 downto 0);
DD : out std_logic_vector(9 downto 0);
CODEC_CLK : in std_logic;
CODEC_X2_CLK : in std_logic
);
end top;
architecture Behavioral of top is
signal codec_clk_rx_i : std_logic;
signal codec_clk_tx_i : std_logic;
signal adc_data_i : std_logic_vector(7 downto 0);
signal dac_data_o : std_logic_vector(9 downto 0);
signal host_clk_i : std_logic;
type transfer_direction is (from_adc, to_dac);
signal transfer_direction_i : transfer_direction;
signal host_data_enable_i : std_logic;
signal host_data_capture_o : std_logic;
signal host_sync_enable : std_logic := '0';
signal host_sync_o : std_logic := '0';
signal host_sync_i : std_logic := '0';
signal host_sync_latched : std_logic := '0';
signal data_from_host_i : std_logic_vector(7 downto 0);
signal data_to_host_o : std_logic_vector(7 downto 0);
signal q_invert : std_logic;
signal rx_q_invert_mask : std_logic_vector(7 downto 0);
signal tx_q_invert_mask : std_logic_vector(7 downto 0);
begin
------------------------------------------------
-- Codec interface
DD(9 downto 0) <= dac_data_o;
------------------------------------------------
-- Clocks
BUFG_host : BUFG
port map (
O => host_clk_i,
I => CODEC_X2_CLK
);
------------------------------------------------
-- SGPIO interface
HOST_DATA <= data_to_host_o when transfer_direction_i = from_adc
else (others => 'Z');
HOST_CAPTURE <= host_data_capture_o;
host_sync_enable <= HOST_SYNC_EN;
host_sync_i <= HOST_SYNC;
HOST_SYNC_CMD <= host_sync_o;
host_data_enable_i <= not HOST_DISABLE;
transfer_direction_i <= to_dac when HOST_DIRECTION = '1'
else from_adc;
------------------------------------------------
q_invert <= HOST_Q_INVERT;
rx_q_invert_mask <= X"80" when q_invert = '1' else X"7f";
tx_q_invert_mask <= X"7f" when q_invert = '1' else X"80";
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
codec_clk_rx_i <= CODEC_CLK;
adc_data_i <= DA(7 downto 0);
if (transfer_direction_i = from_adc) then
if codec_clk_rx_i = '1' then
-- I: non-inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor X"80";
else
-- Q: inverted between MAX2837 and MAX5864
data_to_host_o <= adc_data_i xor rx_q_invert_mask;
end if;
end if;
end if;
end process;
process(host_clk_i)
begin
if falling_edge(host_clk_i) then
codec_clk_tx_i <= CODEC_CLK;
data_from_host_i <= HOST_DATA;
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
dac_data_o <= (data_from_host_i xor tx_q_invert_mask) & tx_q_invert_mask(0) & tx_q_invert_mask(0);
else
dac_data_o <= (data_from_host_i xor X"80") & "00";
end if;
else
dac_data_o <= (dac_data_o'high => '0', others => '1');
end if;
end if;
end process;
process (host_data_enable_i, host_sync_i)
begin
host_sync_o <= host_data_enable_i;
if host_data_enable_i = '1' then
if rising_edge(host_sync_i) then
host_sync_latched <= host_sync_i;
end if;
else
host_sync_latched <= '0';
end if;
end process;
process(host_clk_i)
begin
if rising_edge(host_clk_i) then
if transfer_direction_i = to_dac then
if codec_clk_tx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
else
if codec_clk_rx_i = '1' then
host_data_capture_o <= host_data_enable_i and (host_sync_latched or not host_sync_enable);
end if;
end if;
end if;
end process;
end Behavioral;

132
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--
-- Copyright 2012 Jared Boone
--
-- This file is part of HackRF.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
COMPONENT top
PORT(
HOST_DATA : INOUT std_logic_vector(7 downto 0);
HOST_CAPTURE : OUT std_logic;
HOST_DISABLE : IN std_logic;
HOST_DIRECTION : IN std_logic;
HOST_DECIM_SEL : IN std_logic_vector(2 downto 0);
DA : IN std_logic_vector(7 downto 0);
DD : OUT std_logic_vector(9 downto 0);
CODEC_CLK : IN std_logic;
CODEC_X2_CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal DA : std_logic_vector(7 downto 0) := (others => '0');
signal CODEC_CLK : std_logic := '0';
signal CODEC_X2_CLK : std_logic := '0';
signal HOST_DISABLE : std_logic := '1';
signal HOST_DIRECTION : std_logic := '0';
signal HOST_DECIM_SEL : std_logic_vector(2 downto 0) := "010";
--BiDirs
signal HOST_DATA : std_logic_vector(7 downto 0);
--Outputs
signal DD : std_logic_vector(9 downto 0);
signal HOST_CAPTURE : std_logic;
begin
uut: top PORT MAP (
HOST_DATA => HOST_DATA,
HOST_CAPTURE => HOST_CAPTURE,
HOST_DISABLE => HOST_DISABLE,
HOST_DIRECTION => HOST_DIRECTION,
HOST_DECIM_SEL => HOST_DECIM_SEL,
DA => DA,
DD => DD,
CODEC_CLK => CODEC_CLK,
CODEC_X2_CLK => CODEC_X2_CLK
);
clk_process :process
begin
CODEC_CLK <= '1';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
CODEC_CLK <= '0';
CODEC_X2_CLK <= '1';
wait for 12.5 ns;
CODEC_X2_CLK <= '0';
wait for 12.5 ns;
end process;
adc_proc: process
begin
wait until rising_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000000";
wait until falling_edge(CODEC_CLK);
wait for 9 ns;
DA <= "00000001";
end process;
sgpio_proc: process
begin
HOST_DATA <= (others => 'Z');
HOST_DIRECTION <= '0';
HOST_DISABLE <= '1';
wait for 135 ns;
HOST_DISABLE <= '0';
wait for 1000 ns;
HOST_DISABLE <= '1';
wait for 100 ns;
HOST_DIRECTION <= '1';
wait for 100 ns;
HOST_DISABLE <= '0';
for i in 0 to 10 loop
HOST_DATA <= (others => '0');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
HOST_DATA <= (others => '1');
wait until rising_edge(CODEC_CLK) and HOST_CAPTURE = '1';
end loop;
wait;
end process;
end;