39 lines
1.1 KiB
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39 lines
1.1 KiB
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Clocking Signals
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HackRF clock signals are generated by the Si5351. The plan so far:
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* crystal frequency: 25 MHz (supports 25 or 27 MHz)
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* optional clock input frequency: 10 MHz recommended (supports 10 to 40 MHz, or higher with division)
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* VCO frequency: 800 MHz (supports 600 to 900 MHz)
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* MAX2837 clock: 40 MHz
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* preferred MAX5864 clocks: 8, 10, 12.5, 16, 20 MHz
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* A clock at double the MAX5864 rate will be delivered to the CPLD and SGPIO.
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* LPC43xx clock: 12 MHz (from separate crystal so the ROM-based USB DFU will work)
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Lemondrop+Jellybean Si5351 output mapping:
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* CLK0 -> MAX2837
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* CLK1 -> MAX5864/CPLD
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* CLK2 -> CPLD
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* CLK3 -> CPLD
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* CLK4 -> LPC4330
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* CLK5 -> RFFC5072
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* CLK6 -> extra
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* CLK7 -> extra
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Jawbreaker output mapping:
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* CLK0 -> MAX5864/CPLD
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* CLK1 -> CPLD
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* CLK2 -> SGPIO
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* CLK3 -> external clock output
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* CLK4 -> RFFC5072
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* CLK5 -> MAX2837
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* CLK6 -> none
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* CLK7 -> LPC4330 (but LPC4330 will start up on its own crystal)
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