383 lines
6.7 KiB
Python
383 lines
6.7 KiB
Python
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#!/usr/bin/env python
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# Copyright 2013 Jared Boone
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#
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# Display the LPC43xx Clock Generation Unit (CGU) registers in an
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# easy-to-read format.
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#
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# This file is part of HackRF.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; see the file COPYING. If not, write to
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# the Free Software Foundation, Inc., 51 Franklin Street,
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# Boston, MA 02110-1301, USA.
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"""
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In GDB:
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dump binary memory cgu.bin 0x40050014 0x400500cc
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"""
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import sys
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from struct import unpack
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address = 0x40050014
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f = open(sys.argv[1], 'read')
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d = '\x00' * 20 + f.read()
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length = len(d)
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f.close()
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def print_data(d):
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for i in range(0, length, 16):
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values = unpack('<IIII', d[i:i+16])
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values = ['%08x' % v for v in values]
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values_str = ' '.join(values)
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line = '%08x: %s' % (address + i, values_str)
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print(line)
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#print_data(d)
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#sys.exit(0)
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data = {}
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for i in range(0, length, 4):
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data[i] = unpack('<I', d[i:i+4])[0]
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registers = {
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0x14: {
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'name': 'FREQ_MON',
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'fields': (
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('RCNT', 0, 9),
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('FCNT', 9, 14),
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('MEAS', 23, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x18: {
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'name': 'XTAL_OSC_CONTROL',
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'fields': (
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('ENABLE', 0, 1),
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('BYPASS', 1, 1),
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('HF', 2, 1)
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),
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},
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0x1c: {
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'name': 'PLL0USB_STAT',
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'fields': (
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('LOCK', 0, 1),
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('FR', 1, 1),
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),
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},
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0x20: {
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'name': 'PLL0USB_CTRL',
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'fields': (
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('PD', 0, 1),
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('BYPASS', 1, 1),
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('DIRECTI', 2, 1),
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('DIRECTO', 3, 1),
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('CLKEN', 4, 1),
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('FRM', 6, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x24: {
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'name': 'PLL0USB_MDIV',
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'fields': (
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('MDEC', 0, 17),
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('SELP', 17, 5),
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('SELI', 22, 6),
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('SELR', 28, 4),
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),
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},
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0x28: {
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'name': 'PLL0USB_NP_DIV',
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'fields': (
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('PDEC', 0, 7),
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('NDEC', 12, 10),
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),
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},
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0x40: {
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'name': 'PLL1_STAT',
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'fields': (
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('LOCK', 0, 1),
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),
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},
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0x44: {
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'name': 'PLL1_CTRL',
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'fields': (
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('PD', 0, 1),
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('BYPASS', 1, 1),
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('FBSEL', 6, 1),
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('DIRECT', 7, 1),
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('PSEL', 8, 2),
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('AUTOBLOCK', 11, 1),
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('NSEL', 12, 2),
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('MSEL', 16, 8),
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('CLK_SEL', 24, 5),
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),
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},
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0x48: {
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'name': 'IDIVA_CTRL',
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'fields': (
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('PD', 0, 1),
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('IDIV', 2, 2),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x4C: {
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'name': 'IDIVB_CTRL',
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'fields': (
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('PD', 0, 1),
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('IDIV', 2, 4),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x50: {
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'name': 'IDIVC_CTRL',
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'fields': (
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('PD', 0, 1),
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('IDIV', 2, 4),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x54: {
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'name': 'IDIVD_CTRL',
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'fields': (
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('PD', 0, 1),
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('IDIV', 2, 4),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x58: {
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'name': 'IDIVE_CTRL',
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'fields': (
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('PD', 0, 1),
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('IDIV', 2, 8),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x5C: {
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'name': 'BASE_SAFE_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x60: {
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'name': 'BASE_USB0_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x64: {
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'name': 'BASE_PERIPH_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x68: {
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'name': 'BASE_USB1_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x6C: {
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'name': 'BASE_M4_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x70: {
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'name': 'BASE_SPIFI_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x74: {
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'name': 'BASE_SPI_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x78: {
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'name': 'BASE_PHY_RX_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x7C: {
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'name': 'BASE_PHY_TX_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x80: {
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'name': 'BASE_APB1_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x84: {
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'name': 'BASE_APB3_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x88: {
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'name': 'BASE_LCD_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x8C: {
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'name': 'BASE_VADC_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x90: {
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'name': 'BASE_SDIO_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x94: {
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'name': 'BASE_SSP0_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x98: {
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'name': 'BASE_SSP1_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0x9C: {
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'name': 'BASE_UART0_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0xA0: {
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'name': 'BASE_UART1_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0xA4: {
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'name': 'BASE_UART2_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0xA8: {
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'name': 'BASE_UART3_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0xAC: {
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'name': 'BASE_OUT_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0xC0: {
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'name': 'BASE_APLL_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0xC4: {
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'name': 'BASE_CGU_OUT0_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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0xC8: {
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'name': 'BASE_CGU_OUT1_CLK',
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'fields': (
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('PD', 0, 1),
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('AUTOBLOCK', 11, 1),
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('CLK_SEL', 24, 5),
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),
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},
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# TODO: Add other CGU registers. I did the ones that were
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# valuable to me to debug CPU clock issues.
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}
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for address in sorted(registers):
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register = registers[address]
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name = register['name']
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fields = register['fields']
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value = data[address]
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bits = bin(value)[2:].zfill(32)
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print('%03x %20s %s = %08x' % (address, name, bits, value))
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for field in fields:
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name, low_bit, count = field
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field_value = (value >> low_bit) & ((1 << count) - 1)
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field_bits = bin(field_value)[2:].zfill(count) + ' ' * low_bit
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field_bits = field_bits.rjust(32)
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print('%03s %20s %s = %8x %s' % ('', '', field_bits, field_value, name))
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