292 lines
8.9 KiB
C
292 lines
8.9 KiB
C
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/*
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* Copyright 2012 Michael Ossmann <mike@ossmann.com>
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* Copyright 2012 Jared Boone <jared@sharebrained.com>
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*
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* This file is part of HackRF.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "si5351c.h"
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enum pll_sources active_clock_source = PLL_SOURCE_UNINITIALIZED;
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/* External clock output default is deactivated as it creates noise */
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uint8_t clk3_ctrl = SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE;
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/* write to single register */
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void si5351c_write_single(si5351c_driver_t* const drv, uint8_t reg, uint8_t val)
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{
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const uint8_t data_tx[] = { reg, val };
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si5351c_write(drv, data_tx, 2);
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}
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/* read single register */
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uint8_t si5351c_read_single(si5351c_driver_t* const drv, uint8_t reg)
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{
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const uint8_t data_tx[] = { reg };
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uint8_t data_rx[] = { 0x00 };
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i2c_bus_transfer(drv->bus, drv->i2c_address, data_tx, 1, data_rx, 1);
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return data_rx[0];
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}
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/*
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* Write to one or more contiguous registers. data[0] should be the first
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* register number, one or more values follow.
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*/
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void si5351c_write(si5351c_driver_t* const drv, const uint8_t* const data, const size_t data_count)
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{
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i2c_bus_transfer(drv->bus, drv->i2c_address, data, data_count, NULL, 0);
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}
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/* Disable all CLKx outputs. */
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void si5351c_disable_all_outputs(si5351c_driver_t* const drv)
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{
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uint8_t data[] = { 3, 0xFF };
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si5351c_write(drv, data, sizeof(data));
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}
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/* Turn off OEB pin control for all CLKx */
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void si5351c_disable_oeb_pin_control(si5351c_driver_t* const drv)
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{
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uint8_t data[] = { 9, 0xFF };
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si5351c_write(drv, data, sizeof(data));
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}
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/* Power down all CLKx */
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void si5351c_power_down_all_clocks(si5351c_driver_t* const drv)
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{
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uint8_t data[] = { 16
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN
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, SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE
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, SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE
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};
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si5351c_write(drv, data, sizeof(data));
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}
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/*
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* Register 183: Crystal Internal Load Capacitance
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* Reads as 0xE4 on power-up
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* Set to 8pF based on crystal specs and HackRF One testing
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*/
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void si5351c_set_crystal_configuration(si5351c_driver_t* const drv)
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{
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uint8_t data[] = { 183, 0x80 };
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si5351c_write(drv, data, sizeof(data));
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}
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/*
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* Register 187: Fanout Enable
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* Turn on XO and MultiSynth fanout only.
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*/
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void si5351c_enable_xo_and_ms_fanout(si5351c_driver_t* const drv)
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{
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uint8_t data[] = { 187, 0xD0 };
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si5351c_write(drv, data, sizeof(data));
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}
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/*
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* Register 15: PLL Input Source
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* CLKIN_DIV=0 (Divide by 1)
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* PLLA_SRC=0 (XTAL)
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* PLLB_SRC=1 (CLKIN)
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*/
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void si5351c_configure_pll_sources(si5351c_driver_t* const drv)
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{
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uint8_t data[] = { 15, 0x08 };
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si5351c_write(drv, data, sizeof(data));
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}
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/* MultiSynth NA (PLLA) and NB (PLLB) */
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void si5351c_configure_pll_multisynth(si5351c_driver_t* const drv)
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{
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/*PLLA: 25MHz XTAL * (0x0e00+512)/128 = 800mhz -> int mode */
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uint8_t data[] = { 26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00 };
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si5351c_write(drv, data, sizeof(data));
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/*PLLB: 10MHz CLKIN * (0x2600+512)/128 = 800mhz */
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data[0] = 34;
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data[4] = 0x26;
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si5351c_write(drv, data, sizeof(data));
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}
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void si5351c_reset_pll(si5351c_driver_t* const drv)
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{
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/* reset PLLA and PLLB */
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uint8_t data[] = { 177, 0xA0 };
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si5351c_write(drv, data, sizeof(data));
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}
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void si5351c_configure_multisynth(si5351c_driver_t* const drv,
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const uint_fast8_t ms_number,
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const uint32_t p1, const uint32_t p2, const uint32_t p3,
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const uint_fast8_t r_div)
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{
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/*
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* TODO: Check for p3 > 0? 0 has no meaning in fractional mode?
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* And it makes for more jitter in integer mode.
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*/
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/*
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* r is the r divider value encoded:
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* 0 means divide by 1
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* 1 means divide by 2
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* 2 means divide by 4
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* ...
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* 7 means divide by 128
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*/
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const uint_fast8_t register_number = 42 + (ms_number * 8);
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uint8_t data[] = {
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register_number,
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(p3 >> 8) & 0xFF,
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(p3 >> 0) & 0xFF,
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(r_div << 4) | (0 << 2) | ((p1 >> 16) & 0x3),
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(p1 >> 8) & 0xFF,
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(p1 >> 0) & 0xFF,
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(((p3 >> 16) & 0xF) << 4) | (((p2 >> 16) & 0xF) << 0),
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(p2 >> 8) & 0xFF,
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(p2 >> 0) & 0xFF };
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si5351c_write(drv, data, sizeof(data));
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}
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void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll_sources source)
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{
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uint8_t pll;
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#ifdef RAD1O
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(void) source;
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/* PLLA on XTAL */
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pll = SI5351C_CLK_PLL_SRC_A;
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#endif
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#if (defined JAWBREAKER || defined HACKRF_ONE)
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if (source == PLL_SOURCE_CLKIN) {
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/* PLLB on CLKIN */
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pll = SI5351C_CLK_PLL_SRC_B;
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} else {
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/* PLLA on XTAL */
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pll = SI5351C_CLK_PLL_SRC_A;
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}
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#endif
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/* Clock to CPU is deactivated as it is not used and creates noise */
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/* External clock output is kept in current state */
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uint8_t data[] = {16
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,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA) | SI5351C_CLK_INV
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
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,clk3_ctrl
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) | SI5351C_CLK_INV
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,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA)
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,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
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,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
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};
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si5351c_write(drv, data, sizeof(data));
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}
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#define SI5351C_CLK_ENABLE(x) (0<<x)
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#define SI5351C_CLK_DISABLE(x) (1<<x)
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#define SI5351C_REG_OUTPUT_EN (3)
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#define SI5351C_REG_CLK3_CTRL (19)
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void si5351c_enable_clock_outputs(si5351c_driver_t* const drv)
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{
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/* Enable CLK outputs 0, 1, 2, 4, 5 only. */
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/* 7: Clock to CPU is deactivated as it is not used and creates noise */
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/* 3: External clock output is deactivated by default */
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// uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))};
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uint8_t data[] = { SI5351C_REG_OUTPUT_EN,
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SI5351C_CLK_ENABLE(0) |
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SI5351C_CLK_ENABLE(1) |
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SI5351C_CLK_ENABLE(2) |
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SI5351C_CLK_DISABLE(3) |
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SI5351C_CLK_ENABLE(4) |
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SI5351C_CLK_ENABLE(5) |
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SI5351C_CLK_DISABLE(6) |
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SI5351C_CLK_DISABLE(7)
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};
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si5351c_write(drv, data, sizeof(data));
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}
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void si5351c_set_int_mode(si5351c_driver_t* const drv, const uint_fast8_t ms_number, const uint_fast8_t on){
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uint8_t data[] = {16, 0};
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if(ms_number < 8){
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data[0] = 16 + ms_number;
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data[1] = si5351c_read_single(drv, data[0]);
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if(on)
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data[1] |= SI5351C_CLK_INT_MODE;
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else
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data[1] &= ~(SI5351C_CLK_INT_MODE);
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si5351c_write(drv, data, 2);
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}
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}
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void si5351c_set_clock_source(si5351c_driver_t* const drv, const enum pll_sources source)
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{
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if( source != active_clock_source ) {
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si5351c_configure_clock_control(drv, source);
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active_clock_source = source;
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}
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}
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bool si5351c_clkin_signal_valid(si5351c_driver_t* const drv) {
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return (si5351c_read_single(drv, 0) & SI5351C_LOS) == 0;
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}
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void si5351c_clkout_enable(si5351c_driver_t* const drv, uint8_t enable)
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{
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/* Set optput in output enable register */
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uint8_t output_enable = si5351c_read_single(drv, 3);
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output_enable = output_enable & !SI5351C_CLK_DISABLE(3);
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if(enable)
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output_enable = output_enable | SI5351C_CLK_ENABLE(3);
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else
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output_enable = output_enable | SI5351C_CLK_DISABLE(3);
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uint8_t oe_data[] = {SI5351C_REG_OUTPUT_EN, output_enable};
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si5351c_write(drv, oe_data, 2);
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/* Configure clock to 10MHz (TODO customisable?) */
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si5351c_configure_multisynth(drv, 3, 80*128-512, 0, 1, 0);
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/* Set power up/doen in CLK3 control register*/
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uint8_t pll;
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#ifdef RAD1O
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/* PLLA on XTAL */
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pll = SI5351C_CLK_PLL_SRC_A;
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#endif
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#if (defined JAWBREAKER || defined HACKRF_ONE)
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if (active_clock_source == PLL_SOURCE_CLKIN) {
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/* PLLB on CLKIN */
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pll = SI5351C_CLK_PLL_SRC_B;
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} else {
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/* PLLA on XTAL */
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pll = SI5351C_CLK_PLL_SRC_A;
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}
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#endif
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if(enable)
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clk3_ctrl = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA);
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else
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clk3_ctrl = SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE;
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uint8_t clk3_data[] = {SI5351C_REG_CLK3_CTRL, clk3_ctrl};
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si5351c_write(drv, clk3_data, 2);
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}
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