34 lines
1.1 KiB
Markdown
34 lines
1.1 KiB
Markdown
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CPLD interface between LPC43xx microcontroller SGPIO peripheral and MAX5864
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RF codec.
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CPLD-based triggered capture
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============================
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To build this VHDL project and produce an SVF file for flashing the CPLD:
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* Xilinx WebPACK 13.4 for Windows or Linux.
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Generate an XSVF
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================
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After generating a programming file:
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* In the ISE Project Navigator, "Processes: top - Behavioral" pane, double-click "Configure Target Device".
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* Click "OK" to open iMPACT.
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* Ctrl-N to create a "New Project".
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* "Yes" to automatically create and save a project file.
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* Select "Prepare a Boundary-Scan File", choose "XSVF".
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* Select file name "default.xsvf".
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* Click "OK" to start adding devices.
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* Assign new configuration file: "top.jed".
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* Right-click the "xc2c64a top.jed" icon and select "Erase". Accept defaults.
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* Right-click the "xc2c64a top.jed" icon and select "Program".
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* Right-click the "xc2c64a top.jed" icon and select "Verify".
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* Choose menu "Output" -> "XSVF File" -> "Stop Writing to XSVF File".
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* Close iMPACT.
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To Program
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==========
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$ hackrf_cpldjtag -x default.xsvf
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