485 lines
18 KiB
C++
485 lines
18 KiB
C++
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/*
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* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "clock_manager.hpp"
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#include "portapack_persistent_memory.hpp"
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#include "portapack_io.hpp"
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#include "hackrf_hal.hpp"
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using namespace hackrf::one;
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#include "lpc43xx_cpp.hpp"
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using namespace lpc43xx;
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constexpr uint32_t si5351_vco_f = 800000000;
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constexpr si5351::Inputs si5351_inputs {
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.f_xtal = si5351_xtal_f,
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.f_clkin = si5351_clkin_f,
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.clkin_div = 1,
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};
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static_assert(si5351_inputs.f_xtal == si5351_xtal_f, "XTAL output frequency wrong");
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static_assert(si5351_inputs.f_clkin_out() == si5351_clkin_f, "CLKIN output frequency wrong");
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constexpr si5351::PLLInputSource::Type si5351_pll_input_sources {
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si5351::PLLInputSource::PLLA_Source_XTAL
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| si5351::PLLInputSource::PLLB_Source_CLKIN
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| si5351::PLLInputSource::CLKIN_Div1
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};
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constexpr si5351::PLL si5351_pll_xtal_25m {
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.f_in = si5351_inputs.f_xtal,
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.a = 32,
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.b = 0,
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.c = 1,
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};
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constexpr auto si5351_pll_a_xtal_reg = si5351_pll_xtal_25m.reg(0);
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constexpr si5351::PLL si5351_pll_clkin_10m {
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.f_in = si5351_inputs.f_clkin_out(),
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.a = 80,
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.b = 0,
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.c = 1,
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};
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constexpr auto si5351_pll_b_clkin_reg = si5351_pll_clkin_10m.reg(1);
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static_assert(si5351_pll_xtal_25m.f_vco() == si5351_vco_f, "PLL XTAL frequency wrong");
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static_assert(si5351_pll_xtal_25m.p1() == 3584, "PLL XTAL P1 wrong");
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static_assert(si5351_pll_xtal_25m.p2() == 0, "PLL XTAL P2 wrong");
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static_assert(si5351_pll_xtal_25m.p3() == 1, "PLL XTAL P3 wrong");
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static_assert(si5351_pll_clkin_10m.f_vco() == si5351_vco_f, "PLL CLKIN frequency wrong");
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static_assert(si5351_pll_clkin_10m.p1() == 9728, "PLL CLKIN P1 wrong");
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static_assert(si5351_pll_clkin_10m.p2() == 0, "PLL CLKIN P2 wrong");
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static_assert(si5351_pll_clkin_10m.p3() == 1, "PLL CLKIN P3 wrong");
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/*
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constexpr si5351::MultisynthFractional si5351_ms_18m432 {
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.f_src = si5351_vco_f,
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.a = 43,
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.b = 29,
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.c = 72,
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.r_div = 1,
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};
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*/
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/*
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constexpr si5351::MultisynthFractional si5351_ms_0_20m {
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.f_src = si5351_vco_f,
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.a = 20,
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.b = 0,
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.c = 1,
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.r_div = 1,
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};
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constexpr auto si5351_ms_0_20m_reg = si5351_ms_0_20m.reg(0);
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*/
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constexpr si5351::MultisynthFractional si5351_ms_0_8m {
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.f_src = si5351_vco_f,
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.a = 50,
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.b = 0,
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.c = 1,
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.r_div = 1,
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};
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constexpr auto si5351_ms_0_8m_reg = si5351_ms_0_8m.reg(clock_generator_output_codec);
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constexpr si5351::MultisynthFractional si5351_ms_group {
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.f_src = si5351_vco_f,
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.a = 80, /* Don't care */
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.b = 0,
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.c = 1,
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.r_div = 0,
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};
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constexpr auto si5351_ms_1_group_reg = si5351_ms_group.reg(clock_generator_output_cpld);
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constexpr auto si5351_ms_2_group_reg = si5351_ms_group.reg(clock_generator_output_sgpio);
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constexpr si5351::MultisynthFractional si5351_ms_10m {
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.f_src = si5351_vco_f,
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.a = 80,
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.b = 0,
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.c = 1,
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.r_div = 0,
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};
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constexpr auto si5351_ms_3_10m_reg = si5351_ms_10m.reg(3);
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constexpr si5351::MultisynthFractional si5351_ms_40m {
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.f_src = si5351_vco_f,
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.a = 20,
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.b = 0,
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.c = 1,
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.r_div = 0,
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};
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constexpr auto si5351_ms_rffc5072 = si5351_ms_40m;
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constexpr auto si5351_ms_max2837 = si5351_ms_40m;
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constexpr auto si5351_ms_4_reg = si5351_ms_rffc5072.reg(clock_generator_output_first_if);
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constexpr auto si5351_ms_5_reg = si5351_ms_max2837.reg(clock_generator_output_second_if);
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static_assert(si5351_ms_10m.f_out() == 10000000, "MS 10MHz f_out wrong");
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static_assert(si5351_ms_10m.p1() == 9728, "MS 10MHz p1 wrong");
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static_assert(si5351_ms_10m.p2() == 0, "MS 10MHz p2 wrong");
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static_assert(si5351_ms_10m.p3() == 1, "MS 10MHz p3 wrong");
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static_assert(si5351_ms_rffc5072.f_out() == rffc5072_reference_f, "RFFC5072 reference f_out wrong");
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// static_assert(si5351_ms_50m.p1() == 2048, "MS 50MHz P1 wrong");
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// static_assert(si5351_ms_50m.p2() == 0, "MS 50MHz P2 wrong");
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// static_assert(si5351_ms_50m.p3() == 1, "MS 50MHz P3 wrong");
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static_assert(si5351_ms_max2837.f_out() == max2837_reference_f, "MAX2837 reference f_out wrong");
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// static_assert(si5351_ms_50m.p1() == 2048, "MS 40MHz P1 wrong");
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// static_assert(si5351_ms_50m.p2() == 0, "MS 40MHz P2 wrong");
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// static_assert(si5351_ms_50m.p3() == 1, "MS 40MHz P3 wrong");
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constexpr si5351::MultisynthInteger si5351_ms_int_off {
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.f_src = si5351_vco_f,
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.a = 255,
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.r_div = 0,
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};
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constexpr si5351::MultisynthInteger si5351_ms_int_mcu_clkin {
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.f_src = si5351_vco_f,
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.a = 20,
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.r_div = 0,
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};
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constexpr auto si5351_ms6_7_off_mcu_clkin_reg = si5351::ms6_7_reg(si5351_ms_int_off, si5351_ms_int_mcu_clkin);
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static_assert(si5351_ms_int_off.f_out() == 3137254, "MS int off f_out wrong");
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static_assert(si5351_ms_int_off.p1() == 255, "MS int off P1 wrong");
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static_assert(si5351_ms_int_mcu_clkin.f_out() == mcu_clkin_f, "MS int MCU CLKIN f_out wrong");
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// static_assert(si5351_ms_int_mcu_clkin.p1() == 20, "MS int MCU CLKIN P1 wrong");
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using namespace si5351;
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static constexpr ClockControl::MultiSynthSource get_reference_clock_generator_pll(const ClockManager::ReferenceSource reference_source) {
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return (reference_source == ClockManager::ReferenceSource::Xtal)
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? ClockControl::MultiSynthSource::PLLA
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: ClockControl::MultiSynthSource::PLLB
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;
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}
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constexpr ClockControls si5351_clock_control_common { {
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{ ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Group, ClockControl::ClockInvert::Invert, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Group, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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} };
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ClockManager::Reference ClockManager::get_reference() const {
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return reference;
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}
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static void portapack_tcxo_enable() {
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portapack::io.reference_oscillator(true);
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/* Delay >10ms at 96MHz clock speed for reference oscillator to start. */
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/* Delay an additional 1ms (arbitrary) for the clock generator to detect a signal. */
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volatile uint32_t delay = 240000 + 24000;
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while(delay--);
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}
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static void portapack_tcxo_disable() {
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portapack::io.reference_oscillator(false);
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}
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#include "hackrf_gpio.hpp"
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using namespace hackrf::one;
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void ClockManager::init_clock_generator() {
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clock_generator.reset();
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clock_generator.set_crystal_internal_load_capacitance(CrystalInternalLoadCapacitance::XTAL_CL_8pF);
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clock_generator.enable_fanout();
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clock_generator.set_pll_input_sources(si5351_pll_input_sources);
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clock_generator.set_clock_control(
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clock_generator_output_mcu_clkin,
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si5351_clock_control_common[clock_generator_output_mcu_clkin].clk_src(ClockControl::ClockSource::CLKIN).clk_pdn(ClockControl::ClockPowerDown::Power_On)
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);
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clock_generator.enable_output(clock_generator_output_mcu_clkin);
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reference = choose_reference();
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clock_generator.disable_output(clock_generator_output_mcu_clkin);
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const auto ref_pll = get_reference_clock_generator_pll(reference.source);
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const ClockControls si5351_clock_control = ClockControls { {
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si5351_clock_control_common[0].ms_src(ref_pll),
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si5351_clock_control_common[1].ms_src(ref_pll),
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si5351_clock_control_common[2].ms_src(ref_pll),
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si5351_clock_control_common[3].ms_src(ref_pll),
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si5351_clock_control_common[4].ms_src(ref_pll),
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si5351_clock_control_common[5].ms_src(ref_pll),
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si5351_clock_control_common[6].ms_src(ref_pll),
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si5351_clock_control_common[7].ms_src(ref_pll),
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} };
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clock_generator.set_clock_control(si5351_clock_control);
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clock_generator.write(si5351_pll_a_xtal_reg);
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clock_generator.write(si5351_pll_b_clkin_reg);
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clock_generator.write(si5351_ms_0_8m_reg);
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clock_generator.write(si5351_ms_1_group_reg);
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clock_generator.write(si5351_ms_2_group_reg);
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clock_generator.write(si5351_ms_3_10m_reg);
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clock_generator.write(si5351_ms_4_reg);
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clock_generator.write(si5351_ms_5_reg);
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clock_generator.write(si5351_ms6_7_off_mcu_clkin_reg);
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clock_generator.reset_plls();
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// Wait for both PLLs to lock.
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// TODO: Disable the unused PLL?
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const uint8_t device_status_mask = (ref_pll == ClockControl::MultiSynthSource::PLLB) ? 0x40 : 0x20;
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while((clock_generator.device_status() & device_status_mask) != 0);
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clock_generator.set_clock_control(
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clock_generator_output_mcu_clkin,
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si5351_clock_control_common[clock_generator_output_mcu_clkin].ms_src(ref_pll).clk_pdn(ClockControl::ClockPowerDown::Power_On)
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);
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clock_generator.enable_output(clock_generator_output_mcu_clkin);
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}
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uint32_t ClockManager::measure_gp_clkin_frequency() {
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// Measure Si5351B CLKIN frequency against LPC43xx IRC oscillator
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start_frequency_monitor_measurement(cgu::CLK_SEL::GP_CLKIN);
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wait_For_frequency_monitor_measurement_done();
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return get_frequency_monitor_measurement_in_hertz();
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}
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ClockManager::ReferenceSource ClockManager::detect_reference_source() {
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if( clock_generator.clkin_loss_of_signal() ) {
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// No external reference. Turn on PortaPack reference (if present).
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portapack_tcxo_enable();
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if( clock_generator.clkin_loss_of_signal() ) {
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// No PortaPack reference was detected. Choose the HackRF crystal as the reference.
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return ReferenceSource::Xtal;
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} else {
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return ReferenceSource::PortaPack;
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}
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} else {
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return ReferenceSource::External;
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}
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}
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ClockManager::Reference ClockManager::choose_reference() {
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const auto detected_reference = detect_reference_source();
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if( (detected_reference == ReferenceSource::External) ||
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(detected_reference == ReferenceSource::PortaPack) ) {
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const auto frequency = measure_gp_clkin_frequency();
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if( (frequency >= 9850000) && (frequency <= 10150000) ) {
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return { detected_reference, 10000000 };
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}
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}
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portapack_tcxo_disable();
|
||
|
|
return { ReferenceSource::Xtal, 10000000 };
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::shutdown() {
|
||
|
|
clock_generator.reset();
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::enable_codec_clocks() {
|
||
|
|
clock_generator.enable_clock(clock_generator_output_codec);
|
||
|
|
clock_generator.enable_clock(clock_generator_output_cpld);
|
||
|
|
clock_generator.enable_clock(clock_generator_output_sgpio);
|
||
|
|
/* Turn on all outputs at the same time. This probably doesn't ensure
|
||
|
|
* their phase relationships. For example, clocks that output frequencies
|
||
|
|
* in a 2:1 relationship may start with the slower clock high or low?
|
||
|
|
*/
|
||
|
|
clock_generator.enable_output_mask(
|
||
|
|
(1U << clock_generator_output_codec)
|
||
|
|
| (1U << clock_generator_output_cpld)
|
||
|
|
| (1U << clock_generator_output_sgpio)
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::disable_codec_clocks() {
|
||
|
|
/* Turn off outputs before disabling clocks. It seems the clock needs to
|
||
|
|
* be enabled for the output to come to rest at the state specified by
|
||
|
|
* CLKx_DISABLE_STATE.
|
||
|
|
*/
|
||
|
|
clock_generator.disable_output_mask(
|
||
|
|
(1U << clock_generator_output_codec)
|
||
|
|
| (1U << clock_generator_output_cpld)
|
||
|
|
| (1U << clock_generator_output_sgpio)
|
||
|
|
);
|
||
|
|
clock_generator.disable_clock(clock_generator_output_codec);
|
||
|
|
clock_generator.disable_clock(clock_generator_output_cpld);
|
||
|
|
clock_generator.disable_clock(clock_generator_output_sgpio);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::enable_first_if_clock() {
|
||
|
|
clock_generator.enable_clock(clock_generator_output_first_if);
|
||
|
|
clock_generator.enable_output_mask(1U << clock_generator_output_first_if);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::disable_first_if_clock() {
|
||
|
|
clock_generator.disable_output_mask(1U << clock_generator_output_first_if);
|
||
|
|
clock_generator.disable_clock(clock_generator_output_first_if);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::enable_second_if_clock() {
|
||
|
|
clock_generator.enable_clock(clock_generator_output_second_if);
|
||
|
|
clock_generator.enable_output_mask(1U << clock_generator_output_second_if);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::disable_second_if_clock() {
|
||
|
|
clock_generator.disable_output_mask(1U << clock_generator_output_second_if);
|
||
|
|
clock_generator.disable_clock(clock_generator_output_second_if);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::set_sampling_frequency(const uint32_t frequency) {
|
||
|
|
/* Codec clock is at sampling frequency, CPLD and SGPIO clocks are at
|
||
|
|
* twice the frequency, and derived from the MS0 synth. So it's only
|
||
|
|
* necessary to change the MS0 synth frequency, and ensure the output
|
||
|
|
* is divided by two.
|
||
|
|
*/
|
||
|
|
clock_generator.set_ms_frequency(clock_generator_output_codec, frequency * 2, si5351_vco_f, 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::set_reference_ppb(const int32_t ppb) {
|
||
|
|
/* NOTE: This adjustment only affects PLLA, which is derived from the 25MHz crystal.
|
||
|
|
* It is assumed an external clock coming in to PLLB is sufficiently accurate as to not need adjustment.
|
||
|
|
* TODO: Revisit the above policy. It may be good to allow adjustment of the external reference too.
|
||
|
|
*/
|
||
|
|
constexpr uint32_t pll_multiplier = si5351_pll_xtal_25m.a;
|
||
|
|
constexpr uint32_t denominator = 1000000 / pll_multiplier;
|
||
|
|
const uint32_t new_a = (ppb >= 0) ? pll_multiplier : (pll_multiplier - 1);
|
||
|
|
const uint32_t new_b = (ppb >= 0) ? (ppb / 1000) : (denominator + (ppb / 1000));
|
||
|
|
const uint32_t new_c = (ppb == 0) ? 1 : denominator;
|
||
|
|
|
||
|
|
const si5351::PLL pll {
|
||
|
|
.f_in = si5351_inputs.f_xtal,
|
||
|
|
.a = new_a,
|
||
|
|
.b = new_b,
|
||
|
|
.c = new_c,
|
||
|
|
};
|
||
|
|
const auto pll_a_reg = pll.reg(0);
|
||
|
|
clock_generator.write(pll_a_reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::start_frequency_monitor_measurement(const cgu::CLK_SEL clk_sel) {
|
||
|
|
// Measure a clock input for 480 cycles of the LPC43xx IRC.
|
||
|
|
LPC_CGU->FREQ_MON = LPC_CGU_FREQ_MON_Type {
|
||
|
|
.RCNT = 480,
|
||
|
|
.FCNT = 0,
|
||
|
|
.MEAS = 0,
|
||
|
|
.CLK_SEL = toUType(clk_sel),
|
||
|
|
.RESERVED0 = 0
|
||
|
|
};
|
||
|
|
LPC_CGU->FREQ_MON.MEAS = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::wait_For_frequency_monitor_measurement_done() {
|
||
|
|
// FREQ_MON mechanism fails to finish if there's no clock present on selected input?!
|
||
|
|
while(LPC_CGU->FREQ_MON.MEAS == 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t ClockManager::get_frequency_monitor_measurement_in_hertz() {
|
||
|
|
// Measurement is only as accurate as the LPC43xx IRC oscillator,
|
||
|
|
// which is +/- 1.5%. Measurement is for 480 IRC clcocks. Scale
|
||
|
|
// the cycle count to get a value in Hertz.
|
||
|
|
return LPC_CGU->FREQ_MON.FCNT * 25000;
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::start_audio_pll() {
|
||
|
|
cgu::pll0audio::ctrl({
|
||
|
|
.pd = 1,
|
||
|
|
.bypass = 0,
|
||
|
|
.directi = 0,
|
||
|
|
.directo = 0,
|
||
|
|
.clken = 0,
|
||
|
|
.frm = 0,
|
||
|
|
.autoblock = 1,
|
||
|
|
.pllfract_req = 0,
|
||
|
|
.sel_ext = 1,
|
||
|
|
.mod_pd = 1,
|
||
|
|
.clk_sel = cgu::CLK_SEL::GP_CLKIN,
|
||
|
|
});
|
||
|
|
|
||
|
|
/* For 40MHz clock source, 48kHz audio rate, 256Fs MCLK:
|
||
|
|
* Fout=12.288MHz, Fcco=491.52MHz
|
||
|
|
* PSEL=20, NSEL=125, MSEL=768
|
||
|
|
* PDEC=31, NDEC=45, MDEC=30542
|
||
|
|
*/
|
||
|
|
cgu::pll0audio::mdiv({
|
||
|
|
.mdec = 30542,
|
||
|
|
});
|
||
|
|
cgu::pll0audio::np_div({
|
||
|
|
.pdec = 31,
|
||
|
|
.ndec = 45,
|
||
|
|
});
|
||
|
|
|
||
|
|
cgu::pll0audio::frac({
|
||
|
|
.pllfract_ctrl = 0,
|
||
|
|
});
|
||
|
|
|
||
|
|
cgu::pll0audio::power_up();
|
||
|
|
while( !cgu::pll0audio::is_locked() );
|
||
|
|
cgu::pll0audio::clock_enable();
|
||
|
|
|
||
|
|
set_base_audio_clock_divider(1);
|
||
|
|
|
||
|
|
LPC_CGU->BASE_AUDIO_CLK.AUTOBLOCK = 1;
|
||
|
|
LPC_CGU->BASE_AUDIO_CLK.CLK_SEL = toUType(cgu::CLK_SEL::IDIVD);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::set_base_audio_clock_divider(const size_t divisor) {
|
||
|
|
LPC_CGU->IDIVD_CTRL.word =
|
||
|
|
(0 << 0)
|
||
|
|
| ((divisor - 1) << 2)
|
||
|
|
| (1 << 11)
|
||
|
|
| (toUType(cgu::CLK_SEL::PLL0AUDIO) << 24)
|
||
|
|
;
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::stop_audio_pll() {
|
||
|
|
cgu::pll0audio::clock_disable();
|
||
|
|
cgu::pll0audio::power_down();
|
||
|
|
while( cgu::pll0audio::is_locked() );
|
||
|
|
}
|
||
|
|
|
||
|
|
void ClockManager::enable_clock_output(bool enable) {
|
||
|
|
if(enable) {
|
||
|
|
clock_generator.enable_output(clock_generator_output_clkout);
|
||
|
|
if(portapack::persistent_memory::clkout_freq() < 1000) {
|
||
|
|
clock_generator.set_ms_frequency(clock_generator_output_clkout, portapack::persistent_memory::clkout_freq() * 128000, si5351_vco_f, 7);
|
||
|
|
} else {
|
||
|
|
clock_generator.set_ms_frequency(clock_generator_output_clkout, portapack::persistent_memory::clkout_freq() * 1000, si5351_vco_f, 0);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
clock_generator.disable_output(clock_generator_output_clkout);
|
||
|
|
}
|
||
|
|
|
||
|
|
if(enable)
|
||
|
|
clock_generator.set_clock_control(clock_generator_output_clkout, si5351_clock_control_common[clock_generator_output_clkout].ms_src(get_reference_clock_generator_pll(reference.source)).clk_pdn(ClockControl::ClockPowerDown::Power_On));
|
||
|
|
else
|
||
|
|
clock_generator.set_clock_control(clock_generator_output_clkout, ClockControl::power_off());
|
||
|
|
}
|